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Where Are We (Fall 2000)?

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Where Are We (Fall 2000)? High Performance Microprocessors André Seznec IRISA/INRIA http://www.irisa.fr/caps André Seznec Caps Team 1 IRISA/INRIA Where are we (Fall 2000)? § 400 Mhz to 1.1 Ghz § 1 cycle = crossing the ALU + bypassing § a floating point operation = 2-4 cycles § register file read/write : 1 cycle è 2 -3 in next generation § L1 cache read/write: 1-3 cycles Performance Microprocessors Performance ètrade-off size-associativity-hit time André Seznec High 2 Caps Team Irisa 1 Where are we (Fall 2000) ? § Integration : 0.25m, 0.18m, 0.125m (2001) § 10 -20 millions of transistors in logic § Memory structures: up to 150 millions of transistors § 20 to 60 Watts è > 100 W soon Performance Microprocessors Performance § 400-600 pins è > 1000 soon André Seznec High 3 Caps Team Irisa Where are we (Fall 2000) ? § Processors x86 : èlow end : 500 Mhz, <100 $ èhigh end : 1 Ghz, 1000 $ § DRAM : 1$ per Mbyte § SRAM : 50$ per Mbyte Performance Microprocessors Performance André Seznec High 4 Caps Team Irisa 2 Binary compatibility § 300 000 000 PCs ! è Introducing a new ISA: a risky business !! § It might change : è embedded applications (cell phones, automotive, ..) Performance Microprocessors Performance è64 bits architectures are needed § André Seznec High 5 Caps Team Irisa 32 or 64 bits architecture § Virtual addresses computed on 32 bits è PowerPC, x86, § Virtual addresses computed on 64 bits è MIPS III, Alpha, Ultrasparc, HP-PA 2.x, IA64 è In 2005: Games ? Word ? § Can ’t be avoided : è x86 ? Performance Microprocessors Performance André Seznec High 6 Caps Team Irisa 3 Which instruction set ? § CISC: x86 § RISC: Sparc, Mips, Alpha, PowerPC, HP-PA § EPIC: IA-64 § does it matter ? Performance Microprocessors Performance André Seznec High 7 Caps Team Irisa RISC ISA § a single instruction width : 32 bits è simple decode è next address § Load/store architecture § Simple addressing : based and indexed § register-register Performance Microprocessors Performance § Advantage: very simple to pipeline André Seznec High 8 Caps Team Irisa 4 RISC (2) § general registers + floating point registers § memory access: 1-8 bytes ALIGNED § limited support to speculative execution Performance Microprocessors Performance André Seznec High 9 Caps Team Irisa CISC x86 § variable instruction size § operands in registers and in memory § destructive code: write one of its operand § non-deterministic instruction execution time Performance Microprocessors Performance André Seznec High 10 Caps Team Irisa 5 EPIC IA64 § EPIC IA64 = è RISC è + lot of registers (128 INT , 128 FP) è + 3 instructions encoded on 128 bits bundle è + 64 predicate registers è + hardware interlocks è + (?) Advanced Loads Performance Microprocessors Performance § The compiler is in charge of the ILP André Seznec High 11 Caps Team Irisa EPIC IA 64 § Not so good : è - ISA support for software pipeline • Rotating registers • Loop management è -Register windows: with variable size ! è -No based addressing è - post-incremented addressing è - (?) Advanced Loads Performance Microprocessors Performance André Seznec High 12 Caps Team Irisa 6 ISA: does it matter? § 32 or 64 bits: ètowards x86 death (or mutation !) § Performances: èx86 ? :=) è floating point !! èAt equal technology ? Performance Microprocessors Performance André Seznec High 13 Caps Team Irisa ISA: does it matter (2) ? § x86: translation in mOp è 4 lost cycles ! è Or use a trace cache § x86: too few floating point registers § Alpha 21264: 2 operands 1 result è + performant RISC § Itanium: IA 64 in order Performance Microprocessors Performance è 800 Mhz in 0.18 m è Alpha 21164 700 Mhz 0.35m (1997) André Seznec High 14 Caps Team Irisa 7 So ? § x86: + installed base, + Intel, - must mute to 64 bits § IA64: + spéculative excution , + Intel § Alpha: + « clean » ISA , - what is Compaq strategy ? § Sparc: = ISA, + SUN Performance Microprocessors Performance § Power(PC):complex ISA, =IBM and Motorola André Seznec High 15 Caps Team Irisa The architect challenge § 400 mm2 of silicon § 3 technology generations ahead § What will you use for performance ? è Pipeline è ILP è Speculative execution è Memory hierarchy Performance Microprocessors Performance è Thread parallelism André Seznec High 16 Caps Team Irisa 8 Deeper and deeper pipeline § Less gates crossing in a single cycle. § 1 cycle = ALU crossing + feeding back § Longer and longer intra-CPU communications : è several cycles to cross the chip § More and more complex control: è more instructions in // è more speculation Performance Microprocessors Performance André Seznec High 17 Caps Team Irisa A few pipeline depths § 12-14 cycles on lIntel Pentium III § 10-12 cycles on AMD Athlon § 7-9 cycles on Alpha 21264 § 9 cycles on UltraSparc § 10 cycles on Itanium § 20 cycles on Willlamette Performance Microprocessors Performance § And it is likely to continue !! André Seznec High 18 Caps Team Irisa 9 Instruction Level Parallelism § Superscalar: è the hardware is responsible for the parallel issuing § binary compatibility § All general purpose processors are superscalar Performance Microprocessors Performance André Seznec High 19 Caps Team Irisa The superscalar degree § Hard to define è« performance that can not be exceeded » § 4 inst / cycles on almost all existing processors § 6 inst / cycles on Itanium Performance Microprocessors Performance § 8 inst / cycles on (future) Alpha 21464 § 16 -32 on Alpha 21964 ?? En 2012 ? :=) André Seznec High 20 Caps Team Irisa 10 Superscalar: the difficulties § ILP is limited on applications:: 3 to 8 instructions per cycle § Register files : ènumber of ports is increasing èaccess is becoming a critical path § How to feed FUs with instructions ? with Performance Microprocessors Performance operands? § How to manage data dependencies § branch issues André Seznec High 21 Caps Team Irisa In order or out of order execution § In order execution : è Ah! If all latencies were statically known .. § In order execution: è UltraSparc 3, Itanium è The compiler must do the work § Out-of-order execution è Alpha 21264, Pentium III, Athlon, Power (PC), Performance Microprocessors Performance HP-PA 8500 André Seznec High 22 Caps Team Irisa 11 Why in order execution § simple to implement èless transistors èshorter design cycle èfaster clock (maybe) § shorter pipeline § the compiler « sees » everything: Performance Microprocessors Performance èmicro-architecture è application André Seznec High 23 Caps Team Irisa Why out-of-order execution § Static ILP is limited on non-regular codes § The compiler does not see everything : èunknown latencies at compile time èmemory (in)dependencies unknown at compile time § No need for recompiling Performance Microprocessors Performance èhum !! André Seznec High 24 Caps Team Irisa 12 Out-of-order execution (1) § Principle : èexecute ASAP: available operands and FUs § Implementation : èlarge instruction window for selecting fireable instructions Performance Microprocessors Performance André Seznec High 25 Caps Team Irisa Out-of-order execution (2) § Sequencing consists of: è// read of instructions èmark dependencies èrename registers èdispatch to FUS èwaiting .. Performance Microprocessors Performance § Dependency managing use space and time André Seznec High 26 Caps Team Irisa 13 Renaming registers: removing false dependencies § WAW and WAR register hazards are not true dependencies. Performance Microprocessors Performance André Seznec High 27 Caps Team Irisa Memory dependencies § To execute a store, data to be stored is needed § Every subsequent load is potentially dependent on any previous store § Solution (old): è addresses are computed in program order è Loads bypass stores with hazards detection Performance Microprocessors Performance André Seznec High 28 Caps Team Irisa 14 Memory dependencies (2) § Solution (current): è optimistic execution (out-of-order) è Repaired when true dependency is encountered è Pb: repair cost § Next generation: dependencies are predicted è Moshovos et Sohi, Micro'30, 1997 Performance Microprocessors Performance è Chrysos et Emer, ISCA ’26, 1998 André Seznec High 29 Caps Team Irisa Control hazards § 15 -30% of instructions are branches § Target and direction are known very late in the pipeline : èCycle 7 on DEC 21264 èCycle 11 on Intel Pentium II èCycle 18 on Willamette Performance Microprocessors Performance § Don ’t waste (all) these cycles ! André Seznec High 30 Caps Team Irisa 15 Dynamic branch prediction § Use history to predict the branch and fetch subsequent instructions § Implementation: tables read in // with the I-Cache § Will be predicted: è conditional branch target and direction è procedure returns è indirect branches Performance Microprocessors Performance André Seznec High 31 Caps Team Irisa Dynamic branch prediction § 1992: DEC 21064, 1 bit scheme § 1993: Pentium, 2 bits scheme § 1995: PentiumPro, local history § 1998: DEC 21264, hybrid predictor Performance Microprocessors Performance André Seznec High 32 Caps Team Irisa 16 Dynamic branch prediction : general trend § More and more complex schemes § target prediction and direction prediction are decoupled § Return stack for procedures § ISA support for speculative execution èCMOV Performance Microprocessors Performance èIA64 predicates André Seznec High 33 Caps Team Irisa Out-of-order execution: « undoing » § uncorrect branch prediction § uncorrect independency prediction § Interruption, exception § Validate in program order § No definitive action out-of-order Performance Microprocessors Performance André Seznec High 34 Caps Team Irisa 17 Being able to « undo » § A copy
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