I.C.D. Integrated Circuit Design

Assessment • 10% Coursework (L-Edit Gate Layout) Integrated Circuit Design 90% Examination Books • Digital Integrated Circuits Iain McNally Jan Rabaey 12 lectures Prentice-Hall ≈ Integrated Circuit Design a.k.a. Principles of CMOS VLSI Design - A Circuits and Systems Perspective Koushik Maharatna Neil Weste & David Harris Pearson 2011 12 lectures ≈ Notes & Resources • http://users.ecs.soton.ac.uk/bim/notes/icd

1001 1003

Integrated Circuit Design History

Iain McNally 1947 First Transistor Content John Bardeen, Walter Brattain, and William Shockley (Bell Labs) • – Introduction 1952 Integrated Circuits Proposed – Overview of Technologies Geoffrey Dummer (Royal Radar Establishment) - prototype failed... – Layout 1958 First Integrated Circuit – Design Rules and Abstraction Jack Kilby (Texas Instruments) - Co-inventor – Cell Design and Euler Paths 1959 First Planar Integrated Circuit – System Design using Standard Cells Robert Noyce (Fairchild) - Co-inventor – Pass Transistor Circuits 1961 First Commercial ICs – Storage Simple logic functions from TI and Fairchild – PLAs 1965 Moore’s Law – Wider View Gordon Moore (Fairchild) observes the trends in integration.

1002 1004 History History

Moore’s Law Moore’s Law; a Self-fulfilling Prophesy Predicts exponential growth in the number of components per chip. The whole industry uses the Moore’s Law curve to plan new fabrication facilities. 1965 - 1975 Doubling Every Year In 1965 Gordon Moore observed that the number of components per chip had doubled every year since 1959 and predicted that the trend would continue Slower - wasted investment through to 1975. 2 Moore describes his initial growth predictions as ”ridiculously precise”. Must keep up with the Joneses .

1975 - 201? Doubling Every Two Years Faster - too costly In 1975 Moore revised growth predictions to doubling every two years. Growth would now depend only on process improvements rather than on Cost of capital equipment to build ICs doubles approximately ev- more efficient packing of components. ery 4 years. In 2000 he predicted that the growth would continue at the same rate for an- other 10-15 years before slowing due to physical limits. 2or the Intels 1005 1007

History

Moore’s Law at Intel1

Dual Core Itantium 2 1,000,000,000 Itantium 2 Itantium 100,000,000 Pentium 4 Pentium III 10,000,000 Pentium II Pentium 1,000,000 486 DX 286 386 100,000 8086

10,000 4004 8080 8008 1,000 1970 1980 1990 2000 2010

1Intel was founded by Gordon Moore and Robert Noyce from Fairchild 1006 Overview of Technologies Overview of Technologies

Components for Logic All functions can be realized with a single NOR base gate.1 Diode

PN

Bipolar Transistors

N P P N N P

MOS Transistors

Enhancement Depletion Silicon Oxide Insulator

G G N−Channel

SD SDNNP SUB SUB P−Channel

Field induced N−channel 1NAND gates could be used instead. 2001 2003

Overview of Technologies Overview of Technologies

Other Bipolar Technologies TTL NAND Gate ECL OR/NOR Gate A A Z Z B B Z

RTL Inverter and NOR gate VCC VCC

Z

VCC A VCC A A Z Z Z Z B B AB

Z Z

A AB VEE

TTL gives faster switching than RTL at the expense of greater complexity2. The • characteristic multi-emitter transistor reduces the overall component count. ECL is a very high speed, high power, non-saturating technology. • 2Most TTL families are more complex than the basic version shown here 2002 2004 Overview of Technologies Digital CMOS Circuits

NMOS - a VLSI technology. Alternative representations for CMOS transistors VDD VDD

A A Z Z B B VDD P−Channel Z Z

A N−Channel

AB B

Various shorthands are used for simplifying CMOS circuit diagrams. Circuit function determined by series/parallel combination of devices. In general substrate connections are not drawn where they connect to Vdd • • Depletion transistor acts as non-linear load resistor. (PMOS) and Gnd (NMOS). • Resistance increases as the enhancement device turns on, thus reducing power All CMOS devices are enhancement mode. • consumption. Transistors act as simple digitally controlled switches. • The low output voltage is determined by the size ratio of the devices. •

2005 2007

Overview of Technologies Digital CMOS Circuits

CMOS logic CMOS - state of the art VLSI. Static CMOS complementary gates

VDD A A A Z B Z B Z B C C

V DD

AZ A Z

An active PMOS device complements the NMOS device giving: • – rail to rail output swing. For any set of inputs there will exist either a path to Vdd or a path to Gnd. • – negligible static power consumption.

2006 2008 Digital CMOS Circuits Digital CMOS Circuits

Compound Gates Compound Gate Example

A A B B Z C V D Z DD C E F Pull Up Network

,,, Symbol

A B Z C D Pull Down Network

,,,

All compound gates are inverting. • GND Realisable functions are arbitrary AND/OR expressions with inverted output. •

2009 2010 Components for Digital IC Design Components for Digital IC Design

Diodes and Bipolar Transistors MOS Transistors

Diode Simple NMOS Transistor Thin Oxide Polysilicon G Thick Oxide PN G G S D P N

NN SD S NNP D P−substrate SUB SUB SUB P N

G Ideal structure - 1D Polysilicon Mask • SD Real structure - 3D • Active Area Mask Depth controlled implants. •

3001 3003

Components for Digital IC Design Components for Digital IC Design

Diodes and Bipolar Transistors Simple NMOS Transistor

NPN Transistor Active Area mask defines extent of Thick Oxide. • EBC Polysilicon mask also controls extent of Thin Oxide (alias Gate Oxide). • N PN N N-type implant has no extra mask. P N • – It is blocked by thick oxide and by polysilicon. – The implant is Self Aligned. Substrate connection is to bottom of wafer. • EBC – All substrates to ground. NPN Gate connection not above transistor area. • – Design Rule.

Two n-type implants. •

3002 3004 Components for Digital IC Design CMOS Process

MOS Transistors CMOS Inverter

NMOS Transistor G N SUB S D

P

P +NN + + P well P

N G P

N P well mask N−well Active Area P+ implant mask N implant N SUB SD P implant P Polysilicon Contact Window Metal N+ implant mask

3005 3007

Components for Digital IC Design CMOS Process

NMOS Transistor CMOS Inverter Where it is not suitable for substrate connections to be shared, a more complex process is used.

Five masks must be used to define the transistor: The process described here is an N Well process since it has only an N Well. • • – P Well P Well and Twin Tub processes also exist. – Active Area Note that the P-N junction between chip substrate and N Well will remain re- • – Polysilicon verse biased. – N+ implant Thus the transistors remain isolated. – P+ implant N implant defines NMOS source/drain and PMOS substrate contact. • P Well, for isolation. P implant defines PMOS source/drain and NMOS substrate contact. • • Top substrate connection. • P+/N+ implants produce good ohmic contacts. •

3006 3008 N−well P N Active Area defines Thick Oxide P N Polysilicon defines Thin Oxide P N N implant NN N aligned to AA and Poly PN P implant PNNPPN aligned to AA and Poly PN Contact Window PNNPPN PN

Metal PNNPPN PN

3009 Photolithography Design Rules

To prevent chip failure, designs must conform to design rules: Photoresist Exposure Single layer rules UV Light Contact/Proximity Mask • Glass Mask Mask Pattern (chrome)

Silicon Wafer Photoresist Development

Oxide Growth Oxide Etch Multi-layer rules • SiO 2

Photoresist Deposition Photoresist Photoresist Strip (positive)

4001 4003

Mask Making Derivation of Design Rules

Reticle written by scanning Pattern reproduced on wafer (or contact/proximity mask) electron beam by step and repeat with optical reduction

Isotropic Etching Mask Misalignment Optical Focus over 3D terrain UV Light Reticle Mask Reticle Mask Lens

Lateral Diffusion

Misalignment can be Cumulative N

NN

is aligned to NN is aligned to

Optical reduction allows narrower line widths. •

4002 4004 Design Rules Abstraction - Stick Diagrams

0.5 µm CMOS inverter

Stick diagrams give us many of the benefits of abstraction: N−well Much easier/faster than full mask specification. • Active Area Process independent (valid for any CMOS process). • P implant Easy to change. = NOT{ N implant } • Polysilicon while avoiding some of the problems: Contact Window Optimized layout may be generated much more easily from a stick diagram • than from transistor or gate level designs.1 Metal 1note that all IC designs must end at the mask level. 4005 4007

Abstraction Digital CMOS Design

Levels of Abstraction Stick Diagrams

Mask Level Design • – Laborious Technology/Process dependent. Metal – Design rules may change during a design! Polysilicon N+ Transistor Level Design P+ • Contact – Process independent, Technology dependent. Tap Combined contact Gate Level Design & tap • – Process/Technology independent.

4006 4008 Digital CMOS Design Sticks and CAD - Symbolic Capture

Stick Diagrams

L=0.5 W=2.2

L=0.5 W=1.1

Transistors are placed and explicitly sized. • - components are joined with zero width wires. - contacts are automatically selected as required. A semi-automatic compaction process will create DRC correct layout. • 4009 4011

Digital CMOS Design Sticks and CAD - Magic

Stick Diagrams

Explore your Design Space. •

– Implications of crossovers.

– Number of contacts.

– Arrangement of devices and connections.

Process independent layout. Log style design (sticks with width) - DRC errors are flagged immediately. • • - again contacts are automatically selected as required. Easy to expand to a full layout for a particular process. On-line DRC leads to rapid generation of correct designs. • • - symbolic capture style compaction is available if desired.

4010 4012 Digital CMOS Design Digital CMOS Design

A logical approach to gate layout. Finding an Euler Path Computer Algorithms

All complementary gates may be designed using a single row of n-transistors above or • It is relatively easy for a computer to consider all possible arrangements of below a single row of p-transistors, aligned at common gate connections. • transistors in search of a suitable Euler path. This is not so easy for the human designer.

One Human Algorithm

Find a path which passes through all n-transistors exactly once. • Express the path in terms of the gate connections. • Is it possible to follow a similarly labelled path through the p-transistors? • – Yes – you’ve succeeded. – No – try again (you may like to try a p path first this time).

5001 5003

Digital CMOS Design Digital CMOS Design

Euler Path Finding an Euler Path

For the majority of these gates we can find an arrangement of transistors such • that we can butt adjoining transistors. A C – Careful selection of transistor ordering. Z B – Careful orientation of transistor source and drain. Referred to as line of diffusion. •

Here there are four possible Euler paths.

5002 5004 Digital CMOS Design Digital CMOS Design

Finding an Euler Path Finding an Euler Path

A B C D Z E F

No possible path through n-transistors!

5005 5007

Digital CMOS Design Digital CMOS Design

Euler Path Example Finding an Euler Path

1 2 3 4 5

1 2 3 4 5

1. Find Euler path 3. Route power nodes 5. Route remaining nodes 2. Label poly columns 4. Route output node 6. Add taps1 for PMOS and NMOS A combined contact and tap, , may be used only where a power contact exists at the end of a line of diffusion. Where this is not the case a simple tap, , should be used. 11 tap is good for about 6 transistors – insufficient taps may leave a chip vulnerable to latch-up 5006 5008 Digital CMOS Design

Finding an Euler Path

A D E B F Z G C H I

No possible path through p-transistors. No re-arrangement will create a solution!

5009 Digital CMOS Design Digital CMOS Design

Multiple gates Two-layer Metal

SABZ

1 METAL 2 METAL LAYER LAYERS

A Z B

S

Most modern VLSI processes support two or more metal layers. The norm is to use only metal for inter-cell routing. SABZ Metal1 horizontal (and for power rails) usually for inter-cell routing Metal2 vertical (and for cell inputs and outputs).

6001 6003

Digital CMOS Design Standard Cell Design

Multiple gates Many ICs are designed using the standard cell method.

Cell Library Creation • Gates should all be of same height. A cell library, containing commonly used logic gates, is created for a process. • – Power and ground rails will then line up when butted. This is often carried out by or on behalf of the foundry. ASIC1 Design • All gate inputs and outputs are available at top and bottom. The ASIC designer must design a circuit using the logic gates available in the • library. – All routing is external to cells. The ASIC designer usually has no access to the full layout of the standard cells – Preserves the benefits of hierarchy. and doesn’t create any new cells for the library. Layout work performed by the ASIC designer is divided into two stages: Interconnect is via two conductor routing. • – Placement – In this case Polysilicon vertically and Metal horizontally. – Routing

1Application Specific Integrated Circuit 6002 6004 Placement & Routing Placement & Routing

Placement Two conductor routing

Conductor A horizontal for inter-cell routing 2 • Conductor B vertical This logical approach means that we should never have to worry about signals • crossing. This makes life considerably easier for a computer (or even a human) to com- plete the routing. We must only ensure that two signals will not meet in the same horizontal or • vertical channel. Computer algorithms can be used to ensure placement of cells such that wires • are short.3 Further computer algorithms can be used to optimize the routing itself. • Cells are placed in one or several equal length lines with inter-digitated power and 2In the two-metal example Conductor A is Metal1 and Conductor B is Metal2 ground rails. 3In VLSI circuits we often find that inter-cell wiring occupies more area than the cells themselves. 6005 6007

Placement & Routing Standard Cell Design

Routing More Metal Layers With three or more metal layers it is possible to take a different approach. The simplest example uses three metal layers. Standard Cells • Use only metal1 except for I/O which is in metal2 Two Conductor Routing • Uses metal2 and metal3

Vdd! Vdd!

ABZ ABZ ABZ

In the routing channels between the cells we route metal1 horizontally and metal2 GND! GND! vertically. LAYOUT ABSTRACT ROUTING

6006 6008 Standard Cell Design Standard Cell Design

More Metal Layers Alternative Placement Style

Vdd! Vdd! Vdd! Vdd!

GND! GND! GND! GND! GND! GND! GND! GND! GND!

Vdd! Vdd! Vdd! Vdd! Vdd! Vdd! Vdd! Vdd! Vdd! Vdd!

GND! GND! GND! GND! GND! GND! GND! GND! GND!

Vdd! Vdd! Vdd! Vdd!

By flipping every second row it may be possible to eliminate gaps between rows. N-wells are merged and power or ground rails are shared. This approach is normally associated with sparse rows and non channel based With this approach we can route safely over the cell to the specified pins leading routing algorithms. to much smaller gaps between cell rows.

6009 6010 Static CMOS Complementary Gates Pass Transistor Circuits

Vdd Transmission Gate PUN • – For static circuits we would normally use a CMOS transmission gates: OUT

PDN EN

GND IN OUT Static • After the appropriate propagation delay the ouput becomes valid and remains valid.1 EN Complementary • For any set of inputs there will exist either a path to Vdd or a path to GND. - - balanced n and p pass transistors Where this condition is not met we have either a high impedence output or a - - faster pull-up conflict in which the strongest path succeeds. Static CMOS Non-complementary - - slower pull-down gates make use of these possibilities.

1c.f. Dynamic logic which uses circuit capicitance to store state for a short time. 7001 7003

Pass Transistor Circuits Pass Transistor Circuits

Pass Transistor Transmission Gate Layout • • IN OUT EN

ENABLE EN

IN OUT IN OUT IN OUT – Provides very compact circuits. EN – Good transmission of logic ‘0’.

– Poor transmission of logic ‘1’. EN EN EN - - slow rise time - - degradation of logic value – note that these circuits are not fully complementary3 hence they do not im- mediately lend themselves to a line of diffusion implementation. The pass transistor is used in many dynamic CMOS circuits2.

2where pull-up is performed by an alternative method 3since there are sets of inputs for which the output is neither pulled low nor high 7002 7004 Pass Transistor Circuits Bus Distributed Multiplexing

Transmission Gate Multiplexor Decoder • & 0 1 Sequencer MUX S fn ALU IN1 Operation Code IN1 IN1 PC ACC OUT S OUT OUT IR IN0 IN0 Operand IN0 S S MAR MDR S S

– very few transistors 4 (+2 for inverter) ME Address Data WR – difficult layout may offset this advantage OE RAM - - prime candidate for 2 level metal Ideal for signals with many drivers from different modules.

7005 7007

Pass Transistor Circuits Bus Distributed Multiplexing

Bus Wiring Implementation of bitslice ALU:5 • A[n] M[n] A[n+1] A[n−1]

A0 B0 C0 Subtract

A1 B1 C1 0

C[n−1] C[n] A2 B2 C2 FA

A3 B3 C3

AS AS BSBS CS CS A[n]’ A M 0 A+M A&M A|M A^M A>>1 A<<1 A−M – distributed multiplexing4 Separate circuit for each function – only one inverter required per bank of transmission gates • Connected via distributed multiplexor – greatly simplifies global wiring • 5Note that transmission gates have no drive capability in themselves. Here a good drive is 4internal chip bus should never be allowed to float high impedance ensured by providing buffers. 7006 7008 Bus Distributed Multiplexing Pass Transistor Circuits

A[n] M[n] Functions Supported: Tristate Inverter A A+M A>>1 ~A • F5 0 1 M A−M A<<1 ~M F4 0 A&M F3 A|M A^M ~(A^M) A&~M A|~M EN C[n−1] C[n] FA IN OUT EN A[n+1]

F2 F1 0 1 2 3 4 F0 3

A[n]’ – Alternatively the transmission gate may be incorporated into the gate. Single optimized ALU module - - one connection is removed - easier to layout • Multiplexing is not distributed - - also easier to simulate! • Multiplexor implementation may use transmission gates • 7009 7011

Pass Transistor Circuits Pass Transistor Circuits

Tristate Inverter Tristate Inverter Layout • •

EN

IN OUT

EN

– Any gate may have a tri-state output by combining it with a transmission gate. INEN EN OUT EN IN OUT

7010 7012 Pass Transistor Circuits

Tristate Inverter Bus Driver •

A0 B0 C0

A1 B1 C1

A2 B2 C2

A3 B3 C3

AS AS BSBS CS CS

– a tristate inverting buffer is often used to drive high capacitance bus signals – transistors may be sized as required

7013 Latches and Flip-Flops Latches and Flip-Flops

A simpler layout may be achieved using tristate inverters. • CMOS transmission gate latch •

D D 1 Q 0 Q D Q LOAD

LOAD LD LD

A simple transparent latch can be build around a transmission gate multiplexor D LD LD Q – transparent when load is high – latched when load is low – this design requires two additional transistors but may well be more com- – two inverters are required since the transmission gate cannot drive itself pact.

8001 8003

Latches and Flip-Flops Latches and Flip-Flops

For use in simple synchronous circuits we use a pair of latches in a master slave • Transmission gate latch layout configuration. •

D 1 1 Q 0 0 D Q CLOCK CLOCK

LD LD

DQLD LD – this avoids the race condition in which a transparent latch drives a second transparent latch operating on the same clock phase. – the circuit behaves as a rising edge triggered D type flip-flop. – a compact layout is possible using 2 layer metal

8002 8004 Latches and Flip-Flops Latches and Flip-Flops

Transmission gate implementation Layout of master slave D type. • •

D Q

CLK D CLK 16 Transistors Q D Q

Tristate inverter implementation • CLK D CLK 16 Transistors

Q CLK CLK CLK CLK

– very compact using alternative configuration. CLK CLK 20 Transistors

8005 8007

Latches and Flip-Flops Latches and Flip-Flops

Alternative configuration For the same functionality we could use an edge triggered D type: • • CLK D Q D 1 1 Q 0 0

CLOCK CLOCK D

Q – Implementation

CLK 26 Transistors D Q

– a few more transistors CLK – more complex wiring CLK 16 Transistors – simpler clock distribution

8006 8008 Register File

Where we have large amounts of storage the use of individual latches can lead to space saving.

Z

A D Q Reg1 ENAr1 LDr1 Load D Q B ENBr1 Clock D Q Reg2 ENAr2 LDr2 Load Reg1 Clock ENBr2 Reg2 D Q Reg3 Reg1 ENAr3 LDr3 Load AB Z ENBr3

Load signals must be glitch free with tightly controlled timing. • Edge Triggered D-type prevents a race condition (Reg1 Reg1 + Reg2). • ←

8009 PLAs, ROMs and RAMs PLAs, ROMs and RAMs

PLA structures PLA structure

Programmable Logic Array structures provide a logical and compact method of P4 implementing multiple SOP (Sum of Products) or POS expressions. P1 A X P3 SOP = AND−OR AND plane OR plane P2 B Y P2 P1 P1 P3 C Z A X A X P2 P2 P4 P1 B Y B Y P3 P3 C Z C Z P4 P4

ABCXYZ

Most PLA structures employ pseudo-NMOS NOR gates using a P-channel device A regular layout is employed, with columns for inputs and outputs and rows in place of the NMOS depletion load. • for intermediate expressions.

9001 9003

PLAs, ROMs and RAMs PLAs, ROMs and RAMs

Pseudo-NMOS NOR gate PLA structure

AND plane cells OR plane cells

P4

OUT P3 I1 I2 I3 I4 I5 I6 I7 P2 Peripheral cells

P1 Unlike complementary CMOS circuits, these gates will dissipate power under • static conditions (since the P device is always on). The P and N channel devices must be ratioed in order to create the required • low output voltage. ABCXYZ

This ratioing results in a slower gate, although there is a trade-off between gate Layout is simply a matter of selecting and placing rectangular cells from a lim- • • speed and static power dissipation. ited set.

9002 9004 PLAs, ROMs and RAMs PLAs, ROMs and RAMs

PLA structure Static RAM

VDD GND VDD GND Used for high density storage on a standard CMOS process. • P4 P4 Short lived conflict during write - NMOS transistors offer stronger path. • P3 Differential amplifiers are used for speedy read. P3 • P2 P2 BIT BIT BIT BIT Vdd P1 P1 ACACB B

ACACB B

Only AND plane cells are shown here

WORD WORD

GND Conversion to sticks is straight forward with opportunities for further opti- • mization. Standard 6 transistor static RAM cell.

9005 9007

PLAs, ROMs and RAMs SRAM Structure

ROMs A ROM may simply be a PLA with fixed decoder plane1 and programmable • data plane. Din[0] Dout[0] Decode Plane Data Plane

W7 Din[1] Dout[1] W6

W5

W4 Din[2] Dout[2] Word Lines W3

W2 nWE

W1

W0 A[0]

A[1] A2 A2 A1 A1 A0 A0 D3 D2 D1 D0 Address Lines Data Lines nOE 1RAM structures can make use of the same decode plane. 9006 9008 System Design Choices Programmable Logic

Programmable Logic • – PLD e.g. PAL 22V10, ICT PEEL22CV10, Lattice ispGAL22V10 – Field Programmable Gate Array (FPGA) e.g. Xilinx XC4013, Altera Cyclone EP1C12

Semi-Custom Design • – Mask Programmable Gate Array e.g. ECS CMOS Gate Array Altera HardCopy II structured ASICs – Standard Cell Design e.g. Alcatel Mietec MTC45000 0.35µm cell library One time use - Fuse programmable. • Full Custom Design • Reprogrammable - UV/Electrically Erasable. •

10001 10003

System Design Choices Field Programmable Gate Array – Xilinx XC4000

Programmable I/O Buffers Programmable Logic START HERE Interconnection • Point – Best possible design turnaround time CLB CLB – Cheapest for prototyping CLB CLB – Best time to market Switching Matrix

– Minimum skill required CLB Semi-Custom Design I/O Buffers I/O Buffers • Vertical Routing Channel Full Custom Design Horizontal Routing Channel • – Cheapest for mass production – Fastest I/O Buffers – Lowest Power 2 1 Configurable Logic Blocks & I/O Blocks – Highest Density • – Most skill required Programmable Interconnect •

1optimization limited by speed/power/area trade off 2Xilinx XC4013 has 576 (24 24) CLBs and up to 192 (4 48) user I/O pins. × × 10002 10004 Field Programmable Gate Array – Altera Cyclone Field Programmable Gate Array – Altera Cyclone LE

Logic Array Blocks, M4K Ram Blocks & I/O Elements3 • Programmable Interconnect •

3Altera Cyclone EP1C12 has 12060 Logic Elements (arranged as 1206 Logic Array Blocks) and and up to 249 user I/O pins. 10004 10005

Field Programmable Gate Array – Xilinx XC4000 CLB Mask Programmable Gate Array

9 Output Pads

VDD Pad

8 Input Pads 68 Gate Sites arranged as 4 columns of 17 sites each.

8 Input Pads

GND Pad

9 Output Pads

10005 10006 Mask Programmable Gate Array Full Custom

GND Vdd GND Vdd X X X X All design styles need full custom designers O O O O

C C C C to design the base programmable logic chips B B B B • to design building blocks for semi-custom A A A A •

Where large ASICs use full custom techniques they are likely to be used alongside semi-custom techniques. Vdd ACB e.g. Hand-held computer game chip O C Full custom bitslice datapath • B hand crafted for optimum area efficiency and low power consumption A GND Standard cell controller • Macro block RAM, ROM Customize Metal and Contact Window masks only. • •

10007 10009

Standard Cell Design

Logic Functions •

Auto Generated Macro Blocks • – PLA – ROM – RAM System Level Blocks • – Microprocessor core4

4Will support System On Chip applications. 10008