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The Synthesis of Stochastic Logic to Perform Multivariate Polynomial Arithmetic* Weikang Qian and Marc D

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The Synthesis of Stochastic Logic to Perform Multivariate Polynomial Arithmetic* Weikang Qian and Marc D The Synthesis of Stochastic Logic to Perform Multivariate Polynomial Arithmetic* Weikang Qian and Marc D. Riedel Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities fqianx030, [email protected] Abstract—As the feature size of integrated circuits scales to [0, 1] correspond to the probability of occurrence of logical ever smaller regimes, maintaining the paradigm of determin- one versus logical zero in an observation interval. In this istic Boolean computation is increasingly challenging. Indeed, way, computations in the deterministic Boolean domain are mounting concerns over noise and uncertainty in signal values motivate a new approach: the design of stochastic logic, that transformed into probabilistic computations in the real domain. is to say, digital circuitry that processes signals probabilistically, Stochastic logic has the advantage that basic arithmetic and so can cope with errors and uncertainty. In this paper, we operations can be performed with simple logic circuits [4]. present a general methodology for synthesizing stochastic logic It suffers from small estimation errors due to the inherent for the computation of multivariate polynomials, a category that variance in the stochastic bit streams; however, this does not is important for applications such as digital signal processing. The method is based on converting polynomials into a particular hinder its applications in areas like artificial neural networks mathematical form – multivariate Bernstein polynomials – and and image processing where some inaccuracy can be toler- then implementing the computation with stochastic logic. The ated [1], [3], [5]. resulting logic processes serial or parallel streams that are Early work on the topic of stochastic logic discussed the im- random at the bit level. In the aggregate, the computation plementation of basic arithmetic operations like multiplication, becomes accurate, since the results depend only on the precision of the statistics. Experiments show that our method produces addition, division, etc., [4], [7], [11]. We have been studying circuits that are highly tolerant of errors in the input stream, the synthesis of stochastic logic more broadly. We described while the area-delay product of the circuit is comparable to that a procedure that, given a target Boolean function, builds of deterministic implementations. a multiplicative binary moment diagram (*BMD) and then synthesizes the stochastic circuit from the *BMD [9]. Also, we described a general method for synthesizing stochastic logic I. INTRODUCTION to compute univariate polynomials [10]. The successful paradigm for integrated circuit design has In this work, we generalize the method in [10]: we propose been to maintain a sharp boundary in abstraction between a method for synthesizing stochastic logic to perform multi- the physical and logical layers. From the logic level up, the variate polynomial computation. Given a target power-form computation consists of a deterministic sequence of zeros multivariate polynomial, we first convert it into a multivariate and ones. The precise Boolean functionality of a circuit is Bernstein polynomial. Then, we synthesize stochastic logic to prescribed; it is up to the physical layer to produce voltage compute that Bernstein polynomial. We present the results of values that can be interpreted as the exact logical values synthesis trials for bivariate polynomials. The results show that that are called for. This abstraction is firmly entrenched yet our method produces circuits that are highly tolerant of errors, costly: variability, uncertainty, noise – all must be compensated while the area-delay product of the circuit is comparable to for through ever more complex design and manufacturing. that of deterministic implementations. As technology continues to scale, with mounting concerns over noise and uncertainty in signal values, the cost of the abstraction is becoming untenable. A. Mathematical Model of Stochastic Logic We are developing a framework for digital IC design In a conventional interpretation, a combinational circuit based on the concept of stochastic logic. This paradigm has performs deterministic computation: the inputs are determin- been known in the literature for many years [6]. Instead istic Boolean values and we expect the outputs to be also of computing with deterministic signals, operations at the deterministic. In stochastic logic, the inputs to the circuit logic level are performed on random serial or parallel bit are random Boolean variables. Consequently, the outputs are streams. The streams are digital, consisting of zeros and ones; also random Boolean variables, with probability distribution they are processed by ordinary logic gates, such as AND determined by the probability distribution of the inputs. (In and OR. However, they convey values through the statistical general, stochastic logic can be implemented by sequential distribution of the logical values. Real values in the interval circuits Here, we only consider combinational circuits.) We can model stochastic logic as follows. ∗This work is supported by a grant from the Semiconductor Research Corporation’s Focus Center Research Program on Functional Engineered Assume that y = f(x1; x2; : : : ; xn) is an output Boolean Nano-Architectonics, contract No. 2003-NT-1107. function of a combinational logic circuit. Let X1;X2;:::;Xn be n independent random variables with Bernoulli distribution copy simultaneously. The choice between serial and parallel and assume that the probability of Xi being 1 is pXi . We write stochastic logic translates into a trade-off between time and P (Xi = 1) = pXi and P (Xi = 0) = 1 − pXi . area. When the Boolean function has Xi’s as its arguments, the Figure 1 illustrates a serial implementation with two inputs result is also a random variable Y = f(X1;X2;:::;Xn) with and one output. The inputs and output are stochastic bit Bernoulli distribution. We assume that the probability of Y streams that are 8 bits in length. For the output, there are being 1 is pY . We write P (Y = 1) = pY and P (Y = 0) = four 1’s out of a total of 8 bits. Thus, the estimate is 1 − pY . pY = 4=8 = 0:5. Evidently, pY is uniquely determined by the given n- tuple (p ; p ; : : : ; p ), which we write as p = X1 X2 Xn Y 1 0 1 0 1 0 1 1 F (p ; p ; : : : ; p ). The function F is the computation Combinational X1 X2 Xn 0 0 1 1 0 1 0 1 performed by the stochastic logic. Logic In [10] we showed that F is a specific kind of multivariate 0 1 1 0 1 0 0 1 polynomial on arguments pX1 ; pX2 ; : : : ; pXn : each product term of F has an integer coefficient and the degree of each Fig. 1. A serial implementation of stochastic logic with inputs and outputs as serial bit streams. variable in that term is less than or equal to 1. Mathematically, F is of the form 1 1 n ! X X Y F (p ; : : : ; p ) = ··· α pik ; II. SYNTHESIS OF STOCHASTIC LOGIC FOR X1 Xn i1:::in Xk (1) ULTIVARIATE OLYNOMIAL RITHMETIC i1=0 in=0 k=1 M P A where αi1:::in ’s are integer coefficients. Stochastic logic generally implements a specific type of As an example, we consider stochastic logic built on a multivariate polynomial F on arguments pX1 ; pX2 ; : : : ; pXn . multiplexer. The Boolean function of the multiplexer is If we associate some of the pXi ’s in the polynomial F (pX ; pX ; : : : ; pX ) with real constants in the unit interval, y = f(x1; x2; s) = (x1 ^ s) _ (x2 ^ :s); 1 2 n some with a variable t1, some with a variable t2 and so on, where ^ means logical AND, _ means logical OR and : then the function F becomes a real-coefficient multivariate means logical negation. From the definition of pY , we have polynomial. Specifically, if we set pY = F (pX1 ; pX2 ; pS) pX1 = a1; pX2 = a2; ··· ; pXr = ar1 ; = P (X = 1;S = 1) + P (X = 1;S = 0) 1 1 2 p = ··· = p = t ; (2) Xr1+1 Xr2 1 = pX1 pS + pX2 (1 − pS) pX = ··· = pX = t2; = p + p p − p p ; r2+1 r3 X2 X1 S X2 S ··· which confirms that F is an integer-coefficient polynomial on p = ··· = p = t ; Xrd+1 Xn d the arguments pX1 ; pX2 and pS and the degree of each variable in each product term is less than or equal to 1. we obtain a real-coefficient multivariate polynomial g(t1; t2; : : : ; td). For example, consider B. Implementation of Stochastic Logic y = F (p ; p ; : : : ; p ) If we want to implement stochastic logic based on a Boolean X1 X2 X6 = p p − p p p + p p p − p p p p : function f(x1; x2; : : : ; xn), we first build a combinational cir- X1 X3 X1 X3 X4 X2 X5 X6 X2 X3 X5 X6 cuit implementing the Boolean function f. Then, we generate If we set pX1 = 0:4; pX2 = 0:7; pX3 = t1; pX4 = pX5 = n independent stochastic bit streams X1;X2;:::;Xn, each pX6 = t2, then we obtain a multivariate polynomial consisting of N bits. Each bit in the stream Xi equals logical p 2 2 1 with independent probability Xi . The stream is fed into g(t1; t2) = 0:4t1 − 0:4t1t2 + 0:7t2 − 0:7t1t2: the corresponding input xi. Thus, in a statistical sense, each bit stream represents a random Boolean variable. In this way, With different choices of the original Boolean function f and when we measure the rate of the occurrence of 1 in the output different settings of the probabilities pXi ’s, we obtain different bit stream, it gives us an estimate of pY . If the bit stream polynomials g(t1; t2; : : : ; td). is sufficiently long, we can get an accurate estimate of pY . For applications, we need to perform the computation of We assume that the input and output of the circuit are directly specific polynomials. Given an arbitrary multivariate polyno- usable in this form. For instance, in sensor applications, analog mial, how can we synthesize stochastic logic to implement voltage discriminating circuits might be used to transform real- it? valued input and output values into and out of probabilistic bit In what follows, we first introduce the concept of a mul- streams.
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