Outline
Memory Management ❚ Virtual memory ❚ Page-based memory management Ø Page table and address translation ❚ Multi-level page table Instructor: Dr. Tongping Liu ❚ Translation lookaside buffer (TLB) ❚ Demand paging ❚ Thrashing and working set ❚ Page replacement ❚ Kernel memory management ❚ User-space memory management
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Memory Virtual Memory
N ❚ The ideal memory is ❚ Basic idea: allow OS to allocate 2 Ø Very large more memory than the real Auxiliary Ø Very fast regions Ø Non-volatile (doesn’t go away when power is turned off) ❚ Program uses virtual addresses ❚ The real memory is Ø Addresses local to the process Ø Limited by # of bits in address (32/64) Ø Not very large Stack Ø 32 bits: 4GB Ø Not very fast Ø 64 bits (actually 48 bits): 256TB Ø Affordable (cost) ! ❚ Virtual memory >> physical memory Heap ⇒ Pick any two… ❚ Memory management goal: make the reality Text similar to the idea world as much as possible J 0
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1 Motivations for Virtual Memory Virtual and Physical Addresses
❚ Efficient Use of Limited Memory ❚ Virtual address space CPU chip Ø Keep only active address space in the memory Ø Determined by the instruction width Ø Some non-active parts can be stored on the disk CPU MMU Ø Same for all processes ❚ Simplify Memory Management Virtual addresses ❚ Physical memory indexed by Ø Each process “gets” the same full, linear address space from CPU to MMU physical addresses ❚ Isolates Executions of Multiple Processes Memory Ø Limited by bus size (# of bits) Ø One process can’t interfere with another’s memory Ø Amount of available memory ü They operate in different address spaces Physical addresses Ø User process cannot access privileged information on bus, in memory ü Different sections of address spaces have different permissions Disk controller
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Outline Page-Based Memory Management
❚ Virtual memory ❚ Virtual address 60–64K - 56–60K - ❚ Page-based memory management Ø Divided into pages 52–56K - ❚ Physical memory 48–52K - Ø Page table and address translation 44–48K 5 Ø Divided into frames 40–44K 1 36–40K - ❚ Multi-level page table 32–36K - 28–32K 3 7 28–32K ❚ Translation lookaside buffer (TLB) ❚ Page vs. Frame 24–28K - 6 24–28K Ø Same size address block 20–24K - 5 20–24K ❚ Demand paging 16–20K 0 4 16–20K Ø Unit of mapping/allocation 12–16K - 3 12–16K 8–12K - 2 8–12K ❚ Thrashing and working set 4–8K 4 1 4–8K ❚ Page replacement ❚ A page is mapped to a frame 0–4K 7 0 0–4K Virtual space Physical Ø All addresses in the same virtual memory ❚ Kernel memory management page are in the same physical frame ❚ User-space memory management à offset in a page
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2 Page Table Translate Virtual to Physical Address
❚ Each process has one page table 15 ❚ Split virtual address (from CPU) into two pieces Ø Map page number à physical frame number Ø Page number (p) ❚ Number of PTEs in page table Ø Page offset (d) Ø Number of total pages in virtual space Frame 6 Ø Not just the pages in use Frame 1 ❚ Page number ❚ Page table is checked for Ø Index into an entry of the page table that holds the every address translation Frame 3 corresponding physical frame number Ø Where to store page table? ❚ Page offset Frame 0 ❚ Not all pages need to be mapped to frames Ø Position inside a page at the same time ❚ Page size = 2d bytes: determined by offset size ❚ Not all physical frames need to be used 1 Frame 4 0 Frame 7 Page table
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Logic Address An Example of Virtual/Physical Addresses n Suppose logical address space is 2m and page size is ❚ Example: 2n, so the number of pages is 2m / 2 n , which is 2m-n Ø 64 KB virtual memory Ø 32 KB physical memory ❚ Logical Address (m bits) is divided into: Ø 4 KB page/frame size à 12 bits as offset (d) Ø Page number (p) – used as an index into a page table which contains frame number of physical memory Page #:4bits Offset: 12 bits Ø Page offset (d) – combined with base address to define the Virtual address: 16 bits How many virtual pages? physical memory address that is sent to the memory unit
page number page offset Frame #:3bits Offset: 12 bits p d physical address: 15 bits m - n! n! How many physical frames? Department of Computer Science @ UTSA 12
3 In-Class Exercise In-Class Exercise
❚ For an embedded small computer supporting up ❚ For an embedded small computer supporting up to 1k bytes physical memory, where its virtual to 1k bytes physical memory, where its virtual address is 12 bits. Suppose that the size of address is 12 bits. Suppose that the size of page/frame is 128 bytes. Use a figure to page/frame is 128 bytes. Use a figure to illustrate the physical and virtual address that illustrate the physical and virtual address that shows the number of bits for offset and shows the number of bits for offset and frame/page number for one level page table. frame/page number for one level page table. • What is the number of virtual pages for each process? • How many physical frames in total? • How many entries in page table for each process?
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In-Class Exercise Address Translation
❚ # of virtual pages: ❚ Example: Page #:5bits Offset: 7 bits 2^12/128= 2^5 = 32 Ø 64 KB virtual memory Virtual address: 12 bits Ø 32 KB physical memory Ø 4 KB page/frame size à 12 bits as offset (d) ❚ # of physical frames 1K/128=8 Page #:4bits Offset: 12 bits Frame #:3bits Offset: 7 bits Virtual address: 16 bits How many virtual pages? physical address: 10 bits Address ❚ # of page table entries Translation 32 Frame #:3bits Offset: 12 bits physical address: 15 bits How many physical frames? Department of Computer Science @ UTSA 15 Department of Computer Science @ UTSA 16
4 Address Translation Architecture Computing Physical Address
frame number page number page offset 1. Compute the page number
0 2. Check the page table, get physical CPU p d f d 1 frame number . page table . 0 f-1 1 3. Compute the starting address of Virtual address f . physical frame . physical address f+1 p-1 f+2 . p f . 4. Compute the physical address . . . physical memory
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Computing Physical Address Computing Physical Address
Virtual address 0x44, offset 0x44 Virtual address 0x224, offset 0x24 1. Compute the page number 1. Compute the page number Page number is #0 Page number is #4 2. Check the page table, get physical 2. Check the page table, get physical frame number frame number Frame number is #2 Frame number is #3 3. Compute the starting address of 3. Compute the starting address of physical frame physical frame Start Address = 2 * 0x80 = 0x100 Start Address = 3 * 0x80 = 0x180 4. Compute the physical address 4. Compute the physical address PhysicalAddress = 0x100 + 0x44 = 0x144 PhysicalAddress = 0x180 + 0x24 = 0x1A4
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5 . Limitations of One-level Page Table Page/Frame Size
❚ Page table should contain all pages of virtual space ❚ Determine the number of bits in offset! Ø Otherwise, some addresses can’t be accessed. ❚ Smaller page size Ø + Less internal fragmentation ❚ All entries should be physically continuous Ø - Larger page table: require more than one frame, hard to allocate! Ø Proof by contradiction. If the index is not continuous, we will need another mechanism to tell us where has a hole or ❚ Larger page size not Ø + Smaller page table and less overhead to track them Ø + More efficient to transfer to/from disk Ø - More internal fragmentation, wasting memory
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. Size of Page Table Size of Page Table
❚ If a computer has 22 bits of logical address (4 MB), ❚ Modern Machine and supports the physical memory up to 1 MB. The Ø 32 bits virtual address page/frame size is 1KB. Ø Size of one page/frame is 4KB (12 bits) ❚ Page table size Virtual addr: P#:12 bits Offset: 10 bits Ø # of virtual pages: 32 – 12 = 20 bits à 220 PTEs Ø Page table size = PTE size * 220 = 4 MB per process à 210 frames Physical addr: F#:10 bits Offset: 10 bits Ø Number of pages: 12 bits à 4K pages ❚ If there are 128 processes, and physical memory is 1 GB Ø Size of page table: Ø Page tables occupy 128 * 4MB = 512 MB § Each page entry must have at least 10 bits à 2 bytes Ø 50% of memory will be used by page tables § 4K * 2 bytes = 8KB à requires 8 consecutive frames How can we get smaller page table?!
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6 Outline Two-Level Page Tables . . ❚ Solution: multi-level page tables 220 ❚ Virtual memory . ❚ Virtual address: three parts 657 . ❚ Page-based memory management . Ø Level-one page number (10 bits) . . . . Ø Page table and address translation Ø Level-two page number (10 bits) 401. . . ❚ Multi-level page table Ø Offset (12 bits) 125 . . . ❚ Translation lookaside buffer (TLB) . 613 ❚ PTE in 1st level page table . . . . . ❚ Demand paging contains the address of physical . frame for 2nd level page table 961 . 1st level . ❚ Thrashing and working set . . page table . . ❚ Page replacement ❚ PTE in 2nd level page table has the . . ❚ Kernel memory management actual physical frame number 884 . main 2nd level 960 ❚ User-space memory management . memory page tables . Department of Computer Science @ UTSA 25 Department of Computer Science @ UTSA 955 26
Two-Level Page Tables Example: 2-level Address Translation . . ❚ We don’t have to allocate all 220 page number page offset . entries initially 657 . . p1 = 10 bits p2 = 10 bits offset = 12 bits . . frame ❚ They don’t have to continuous . number 401. . . 0 125 . Page physical address 1 . . . 613 table 18 12 . . . . . . base . . 0 961 . 0 1st level . 1 . page table . . 1 . . . p . main memory . 1 884 . . p2 18 main . . 2nd level 960 . . . memory . Which tables should page tables . 1st level page table 2nd level page table Department of Computer Science @ UTSA be in memory? 28 955
7 Memory Requirement of Page Tables Memory Requirement of Page Tables
❚ Only the 1st level page table and the required 2nd ❚ Only the 1st level page table and the required 2nd level page tables need to be in memory level page tables need to be in memory
❚ Example: if a process accesses 32 MB virtual memory on such a machine, what is the minimum ❚ 32bit machine, page size 4k, each entry 4 bytes, memory required for the page table using two-level page table (with 10bit-10bit-12bit Ø 4KB / page à process has 8K (8*210) virtual pages design), what is the size for the full page table Ø One 2nd level page table maps 210 pages; Ø Level-0: 1024 entries*4bytes Ø Number (minimum) of 2nd level page table needed: Ø Level-1: 1024*1024entries=1M entries * 4bytes 8*2^10/2^10 = 8 Ø Total: 4M+4K Ø Total (minimum) memory for page table: 1st level page table + 8; in total of 9 page tables à 9 X 4KB = 36 KB
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Memory Requirement of Page Tables Other Questions
❚ Only the 1st level page table and the required 2nd level page tables need to be in memory ❚ If we have two pages (0x00000000 and 0x0020100)), what is the size of page table? ❚ Example: if a process accesses 32 MB virtual memory on such a machine, what is the maximum ❚ 32bit machine, page size 4k, each entry 4 bytes, memory required for the page table two level page table (two pages:0x0000000, and Ø 4KB / page à process has 8K (8*210) virtual pages 0xFFFFF000) Ø We will have at most 2^10 (defining by 10 bits of 1st level) pages/frames in 2nd level Ø Therefore, all of these frames at minimum can have one entry inside. Ø Total (maximum) memory for page table: 1st level page table + 1024 2nd level page tableà 1025 X 4KB 31 Department of Computer Science @ UTSA 32
8 Linux’s 3 level page table Designing of 2-level page table
Linear Address converted to physical address using 3 levels 1. Determine number of bits of page offset (12Bità4KB) 2. Determine the size of each page table entry 3. Determine the number of bits for 2nd level page table Index into Index into Index into Page One principle: page table à fit into one frame Page Dir. Page Middle Page Table Offset Dir. 4. Determine the number of bits for 1st level page table
What are the benefits to use 3-level page table? What are the shortcomings?
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Page Table Entry (PTE) Designing of 2-level Page Table
❚ Each entry in the page table contains ❚ Suppose that a system has a 24-bit logical address Ø Frame number: bits depends on # of frames in physical memory space and is byte-addressable. Physical address Ø Valid bit: set if this logical page number has a corresponding physical frame in memory has 20 bits, and the size of a page/frame is 1K ü If not valid, remainder of this PTE is irrelevant bytes. How to design a two-level page table? Ø Referenced bit: set if data on the page has been accessed 1. The size of page table entry will be 2 bytes (larger Ø Dirty (modified) bit: set if data on the page has been modified Ø Protection information: read-only/read-write than 15 bits) ❚ Size of each PTE: at least frame number plus 4/5 bits 2. One page can hold 512 entries (1K/2=512) nd Protection D R V Frame number 3. Thus, we need 9 bits for the 2 level page table
5 bits 9 bits 10 bits Dirty bit Referenced bit Valid bit
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9 Designing of 2-level Page Table Designing of 2-level Page Table (2)
❚ Suppose that a system has a 24-bit logical address ❚ Suppose that a system has a 18-bit logical address space and is byte-addressable. Physical address space and is byte-addressable. The amount of has 20 bits, and the size of a page/frame is 1K physical memory is 64KB (i.e., the physical bytes. How to design a two-level page table? address has 16 bits) and the size of a page/frame is 128 bytes. How to design a two-level page table? 4 bits 10 bits 10 bits 1. The size of page table entry will be 2 bytes (larger than 11 bits) Second level 10 bits, can’t be fitted into one page. 2. One page can hold 64 entries (128/2=64) Then we may need to have multiple pages (2 pages) 3. Thus, we need 6 bits for the 2nd level page table that are continuous, which increases the complexity of OS design 5 bits 6 bits 7 bits
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How Many Levels are Needed? Outline
❚ New architecture with 64-bits address? ❚ Virtual memory Ø Suppose 4KB page(frame) size (12-bit offset) ❚ Page-based memory management Ø One-level page table, with 264 / 212 = 252 entries!!!! Ø Two-level page table, then inner page table could be one page, Ø Page table and address translation containing 1K entries (10-bit) (assuming PTE size is 4 bytes), then outer page ❚ Multi-level page table needs to contain 242 entries !!!
Ø In total, we will have 6-level paging (7 memory accesses)! ❚ Translation lookaside buffer (TLB) ❚ Problems with multiple-level page table ❚ Demand paging Ø One additional memory access for each level added! ❚ Thrashing and working set Ø Multiple levels are possible; but prohibitive after a few levels ❚ Page replacement Are there any other alternatives to manage the page table, in order to reduce access time? ❚ Kernel memory management ❚ User-space memory management
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10 Translation Look-ahead Buffers (TLB) Translation Lookaside Buffer (TLB)
❚ Translation Look-ahead buffers (TLB) ❚ Small Hardware: fast Logical Physical page # frame # Ø A special fast-lookup hardware cache: associative memory! ❚ Store recent mapping of page à frame (64 ~ 1024 entries) 8 3 Ø Access by content à parallel search: if in TLB, get frame # ❚ If desired logical page number is unused Ø Otherwise, access the page table in memory, and get frame # found, get frame number from TLB 2 1 and put it into TLB ❚ If not, 3 0 ü (if TLB is full, replace an old entry.) Ø Get frame number from page table in 12 12 memory 29 6 Page # Frame # Ø Use standard cache technique 22 11 Ø Replace an entry in the TLB with the logical & physical page number from 7 4 this reference If found Example TLB Target Page # Target Frame # Ø May contain complete page table entries for processes with small number of pages
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Paging Hardware With TLB Address Translation with TLB
page number page offset frame number frame number CPU p d 0 Virtual address f d 1 . p f physical address . Base reg 0 f-1 in PCB TLB/hardware 1 f . . f+1 f+2 p f . P+1 . n Page fault: valid bit physical memory page table (in mem) What happens when cpu performs a context switch? 44
11 Integrating VM and Cache Integrating TLB, Cache with Memory
VA PA miss “ ” Trans- Main ❚ Translation Lookaside Buffer (TLB) Cache CPU lation Memory hit hit data VA PA miss TLB Main ❚ Modern caches are “physically addressed” CPU Cache Ø Allows multiple processes to have data in the cache Lookup Memory simultaneously. Otherwise, every context switch will require to miss hit flush the cache Trans- Ø Cache doesn’t need to be associated with protection issues lation ü Access rights checked as part of address translation ❚ Perform address translation before cache lookup data Ø Could involve memory access (to get PTE) Ø So page table entries can also be cached
Basic overflow Memory Accesses Time
1. CPU will generate a virtual address ❚ Assuming: 2. Check the TLB at first to find the mapping of this page. If the Ø TLB lookup time = a corresponding entry exists, then we could get the PA Ø Memory access time = m address directly. Otherwise, we will go through the slow address translation, and then save the mapping into TLB ❚ Hit ratio (h) is percentage of time that a logical page (typically after the translation). number is found in the TLB 3. After getting a PA address, check whether the Ø More TLB entries usually means higher h corresponding cache line is in the cache or not. If yes, then ❚ Effective Access Time (EAT) is calculated (don’t we will have a cache hit. The value of the corresponding include cache effect) memory unit will be returned to CPU. Ø EAT = (m + a)h + (m + m + a)(1-h) = a + (2-h)m 4. Otherwise, it is a cache miss. The cache line will be fetched into the cache at first. Then the value will be sent back to ❚ Interpretation back to the CPU Ø Reference always requires TLB lookup, 1 memory access Department of Computer Science @ UTSA 47 Ø TLB misses also requireDepartment ofan Computer additional Science @ UTSA memory reference 48
12 Effective Access Time: An Example Outline
n TLB Lookup = 20 nanosecond ❚ Virtual memory n Memory cycle time is 100 nanosecond ❚ Page-based memory management n Hit ratio = 80% Ø Page table and address translation n Effective Access Time (EAT) would be EAT = (20+100) 0.8 + ❚ Multi-level page table (20+100+100)(1 – 0.8) ❚ Translation lookaside buffer (TLB) = 140 nanosecond ❚ Demand paging n 40% slow down ❚ Thrashing and working set n What is the EAT with 98% hit rate? ❚ Page replacement ❚ Kernel memory management ❚ User-space memory management
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Page Table Entry (PTE) Valid (v) or Invalid (i) Bit
❚ Each entry in the page table contains Ø Frame number: bits depends on # of frames in physical memory Ø Valid bit: set if this logical page number has a corresponding physical frame in memory ü If not valid, remainder of this PTE is irrelevant Ø Referenced bit: set if data on the page has been accessed Ø Dirty (modified) bit: set if data on the page has been modified Ø Protection information: read-only/read-write ❚ Size of each PTE: at least frame number plus 4/5 bits
Protection D R V Frame number
Dirty bit Referenced bit Valid bit
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13 Paging and Demand Paging Demand Paging
❚ Paging: ❚ Bring a page into memory Ø Paging is a memory management scheme by which a only when it is needed computer stores and retrieves data from secondary storage Ø Less I/O needed for use in main memory with the same-size blocks called Ø Less memory needed pages. Ø Faster response Ø Paging lets programs exceed the size of available physical Ø More users memory. ❚ Demand Paging: ❚ Page is needed ⇒ Ø Pages are loaded only when they are referenced. reference to it Ø invalid reference ⇒ abort The valid bit allows the implementation of demand paging. Ø not-in-memory ⇒ bring to memory
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Valid-Invalid Bit Page Fault
❚ With each page table entry 1. Reference to a page, a valid–invalid bit is If Invalid reference ⇒ abort associated, 2. If not in memory, page ❚ v ⇒ in-memory, fault occurs (trap to OS) !i ⇒ not-in-memory 3. OS allocates an empty ❚ Initially bit is set to i on all frame
entries 4. Swap page into frame ❚ During address translation, 5. Reset page tables, if valid–invalid bit in page set validation bit = v table entry 6. Restart the instruction is i ⇒ page fault (trap) that caused the page fault
14 Performance of Demand Paging Demand Paging Example
❚ Page Fault Rate 0 ≤ p ≤ 1.0 ❚ Memory access time = 200 nanoseconds
Ø if p = 0 no page faults ❚ Average page-fault service time = 8 milliseconds Ø if p = 1, every reference is a fault ❚ EAT = (1 – p) x 200 + p (8 milliseconds) ❚ Effective Access Time (EAT) = (1 – p) x 200 + p x 8,000,000
EAT = (1 – p) x memory_access + p x page_fault_time = 200 + p x 7,999,800 ❚ page_fault_time depends on several factors ❚ If one out of 1,000 access causes a page fault, then Ø Save user reg and proc state, check page ref, read from the EAT = 8199.8 nanoseconds. disk there might be a queue, (CPU can be given to another This is a slowdown by a factor of 40!! proc), get interrupt, save other user reg and proc state, correct the page table, put this process into ready queue….. Due to ❚ If we want just 10% performance degradation, then p queues, the page_fault_time is a random variable should be 220 > (1 – p) x 200 + p (8 milliseconds) p < 0.0000025 , i.e., 1 page fault out of 400,000 accesses
Outline Thrashing
❚ Virtual memory ❚ If a process does not have “ ” ❚ Page-based memory management enough pages, the page- fault rate is very high. Ø Page table and address translation ❚ E.g. a process needs 6 ❚ Multi-level page table pages, but only have 5 ❚ Translation lookaside buffer (TLB) frames. Thus it will evict a ❚ Demand paging page from existing 5 pages. àfrequent faults ❚ Thrashing and working set This leads to: ❚ Page replacement Ø low CPU utilization ❚ Kernel memory management Ø OS increase the degree of multiprogramming ❚ User-space memory management Ø another process added to the system, worse case Department of Computer Science @ UTSA 59
15 Locality and Thrashing Why locality model
❚ To prevent thrashing we ❚ Suppose we allocate enough frames for a process to should give enough frames accommodate its locality to each process ❚ It will fault for the pages in its locality until all these pages
❚ But how much is “enough” are in memory. Then, it will not fault again until it changes Locality model: localityà a set of its localities. pages that are actively used Ø Process migrates from one ❚ Otherwise, if we do not allocate enough frames, the locality to another! process will thrash, since it cannot keep in memory all the Ø Localities may overlap pages that it is actively using. When Σ size of locality > total memory size ❚ The working-set model is based on the assumption of thrashing occurs… locality. Increase locality in your programs! Department of Computer Science @ UTSA 62
Working-Set Model Working-Set Definition
❚ Δ ≡ working-set window ≡ a fixed number of page ❚ Informal Definition: the collection of pages that a process is working references, example: 10,000 instruction with, and which must thus be resident if the process is to avoid thrashing. ❚ WSSi (working set of Process Pi) = total number of pages ❚ The idea is to use the recent needs of a process to predict its future referenced in the most recent Δ needs. Ø if Δ too small, will not encompass entire locality Ø Choose Δ, the working set parameter. At any given time, all pages referenced by a process in its last Δ seconds of execution are considered to Ø if Δ too large, will encompass localities comprise its working set Ø if Δ = ∞ ⇒ will encompass entire program Ø Pages outside the working set may be discarded at any time.
❚ D = Σ WSSi ≡ total demand frames if D > (available frames) m ⇒ Thrashing Thus, if D > m, then suspend one of the processes
16 Outline Page Replacement
❚ Virtual memory ❚ No free frames in memory, a page needs to be ❚ Page-based memory management replaced. Ø Page table and address translation ❚ Pages that are replaced might be needed again later. ❚ Multi-level page table ❚ We need algorithms to minimize the number of page ❚ Translation lookaside buffer (TLB) faults. ❚ ❚ Demand paging Include other improvements, e.g., use modify (dirty) bit to reduce overhead of page transfers – only ❚ Thrashing and working set modified pages are written to disk ❚ Page replacement ❚ Kernel memory management ❚ User-space memory management
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Basic Page Replacement Page Replacement Algorithms
❚ How to select the victim frame? ❚ Find the desired page on disk Ø You can select any frame, the page replacement will work; ❚ If there is a free frame, use it but the performance??? ❚ If there is no free frame, use a Ø Gives the lowest page-fault rate page replacement algorithm ❚ Evaluate an algorithm by running it on a particular 1. Select a victim frame, swap it out (use dirty bit to swap out only modified frames)! string of memory references (reference string) and 2. Bring the desired page into the (newly) compute the number of page faults on that string free frame; 3. update the page and frame tables In all our examples, we will have 3 frames and the ❚ Resume the process following reference string
17 First-In-First-Out (FIFO) Algorithm FIFO Illustrating Belady’s Anomaly
❚ Maintain an FIFO buffer Reference string (12 accesses) Ø + The page used before may not be needed 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 Ø - An array used early, might be used again and again ❚ Easy to implement ❚ Belady’s Anomaly: more frames ⇒ more page faults
Optimal Algorithm Least Recently Used (LRU) Algorithm
❚ Replace a page that will not be used for longest time ❚ Use recent past as an approximation of the future ❚ Select the page that is not used for a long time… Ø OPT if you look at from backward 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 1 1 Ø NO Belady’s Anomaly: so more frames ⇒ less page faults 2 2 3 3 4 X 5 ❚ How do you know the future? ❚ Used for measuring how well your algorithm performs
18 Implementing LRU Algorithm
Given the reference string of page accesses: 1 2 3 4 2 3 4 1 2 1 ❚ Counter (logical clock) implementation 1 3 1 4 and a system with three page frames, what is the final Ø Increase the counter every time a page is referenced configuration of the three frames after the true LRU algorithm is Ø Save it into time-of-use field applied? Ø Find one with the smallest time-of-use value Ø Problems: Counter overflow and linear search overhead ❚ Stack implementation – keep a stack of page numbers Problem of LRU: How to implement it efficiently? in a double link form: (1) Not good for the parallelism (lock) Full LRU needs to sort all references Ø Page referenced: (2) Hardware support ü move it to the top ü requires 6 pointer ops to be changed Ø No search for replacement ü Least recently used one is at the bottom
Second Chance Algorithm (LRU Approximation) Second Chance Algorithm (LRU Approximation)
❚ Uses one reference bit and one pointer Circular queue implementation: Ø The reference bit will be set to 1 if a page is referenced 1. A pointer indicates which page Ø Pointer pointing to the one that is be checked next will be replaced next Ø If ref bit is 0, 2. When a frame is needed, it ü replace that page ü Move the pointer to the next one advances its pointer until find one Ø If ref bit is 1, /* give a second chance */! with a 0 reference bit. ü set ref bit to 0 ü Leave page in memory ü go to next one What if all bits are 1? …. All pages will get second chance…. Degenerates FIFO
Linux uses the algorithm similar to this one. If a page is used often enough, it will be never replaced.
19 Second Chance Algorithm Example Global vs. Local Allocation
❚ Global replacement – process selects a replacement frame from the set of all frames; one process can take a frame from another Ø High priority processes can take all frames from low priority ones (cause thrashing) Ø A process cannot control its page fault rate ❚ Local replacement – each process selects from only its own set of allocated frames Ø Consistent performance Ø Lower utilization of memory and less throughput
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Summary: Page Replacement Algorithms Outline
❚ Virtual memory
Algorithm Comment ❚ Page-based memory management FIFO (First-In, First Out) Might throw out useful pages Ø Page table and address translation Second chance Big improvement over FIFO ❚ Multi-level page table LRU (Least Recently Used) Excellent, but hard to implement exactly OPT (Optimal) Not implementable, but useful as a benchmark ❚ Translation lookaside buffer (TLB) ❚ Demand paging ❚ Thrashing and working set ❚ Page replacement ❚ Kernel memory management ❚ User-space memory management
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20 Kernel Memory Allocation Buddy System (Dividing)
❚ E.g., Linux PCB (struct task_struct) ü > 1.7 Kbytes each ü Created on every fork and every thread create • clone() ü deleted on every exit
❚ Kernel memory allocators ü Buddy system ü Slab allocation
Two continuous blocks with the same size the first one will start as 2^n
Free Page’s List Page Allocation
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21 Buddy Allocation Buddy De-Allocation
❚ Example: Need to allocate 65 contiguous page frames. ❚ When blocks of page frames are released the kernel Ø Look in list of free 128-page-frame blocks. tries to merge pairs of “buddy” blocks of size b into Ø If free block exists, allocate it, else look in next highest blocks of size 2b. order list (here, 256-page-frame blocks). ❚ Two blocks are buddies if: Ø If first free block is in 256-page-frame list, allocate a 128- page-frame block and put remaining 128-page-frame block Ø They have equal size b. in lower order list. Ø They are located at contiguous physical addresses. Ø If first free block is in 512-page-frame list, allocate a 128- Ø The address of the first page frame in the first block is page-frame block and split remaining 384 page frames aligned on a multiple of 2b*212 (starting at 2b page) into 2 blocks of 256 and 128 page frames. These blocks ❚ The process repeats by attempting to merge buddies are allocated to the corresponding free lists. of size 2b, 4b, 8b etc…
❚ Question: What is the worst-case internal fragmentation?
Slab Allocator
❚ Performs the following functions Ø Allocate memory Ø Initialize objects/structures Ø Use objects/structures Ø Deconstruct objects/structures Ø Free memory ❚ /proc/slabinfo – gives full information about memory usage on the slab level. (see also /usr/bin/slabtop)
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22 Slab Allocator Outline
❚ Slab is one or more physically ❚ Virtual memory contiguous pages ❚ Cache consists of one or more slabs ❚ Page-based memory management ❚ Single cache for each unique kernel Ø Page table and address translation data structure (process descriptions, file objects, ❚ Multi-level page table semaphores)! Ø Each cache filled with objects – instantiations of the ❚ Translation lookaside buffer (TLB) data structure ❚ Demand paging ❚ When cache created, filled with objects
marked as free! ❚ Thrashing and working set ❚ When structures stored, objects marked Benefits include ❚ Page replacement as used! n no fragmentation, ❚ Kernel memory management ❚ If slab is full, next object is allocated n memory request is ❚ from empty slab. If no empty slabs, new slab allocated satisfied quickly User-space memory management
Department of Computer Science @ UTSA 90
Memory allocation (using mmap/brk) Memory allocation #include
23 Memory Mapping (mmap or brk) Memory Mapping (mmap or brk) #include
0804b000-0806c000 rw-p [heap] 0804b000-0806c000 rw-p [heap]
What We Learn Here Memory Allocator for Multithreaded Programs (Hoard)
❚ Typically, the user will ask one big block of memory Super Blocks and setup its page table. “Thread” 1 “Thread” n …… …… …… …… ❚ Then this block of memory will be managed by user space memory manager. Ø How to manage the memory inside user space?
Department of Computer Science @ UTSA 95 Department of Computer Science @ UTSA 96
24 Memory Allocator for Multithreaded Programs (Hoard) Default Linux Allocator
malloc_stat ❚ Designed to perform well e unused Ø Bump pointers + freelists ⋮ Shows the memory in-use allocate Ø Not designed for security purposes top d header Uses free-list to manage ❚ Prepends metadata before actual objects ⋮ allocate d available/freed objects ❚ Provides no randomization header Ø Result: easy to determine next object to be allocated free ❚ Poor handling of double/invalid frees header Heap segment
prev size cur size allocated prev size cur size ���������������� free space 16 32 space 32 24 fd bk
Linux allocator’s object metadata placement
Department of Computer Science @ UTSA 97
Outline
❚ Virtual memory ❚ Page-based memory management Ø Page table and address translation ❚ Multi-level page table ❚ Translation lookaside buffer (TLB) ❚ Demand paging ❚ Thrashing and working set ❚ Page replacement ❚ Kernel memory management ❚ User-space memory management
Department of Computer Science @ UTSA 99
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