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Memory Management ❚ Virtual Memory ❚ Page-Based Memory Management Ø Page Table and Address Translation ❚ Multi-Level Page Table Instructor: Dr

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Memory Management ❚ Virtual Memory ❚ Page-Based Memory Management Ø Page Table and Address Translation ❚ Multi-Level Page Table Instructor: Dr Outline Memory Management ❚ Virtual memory ❚ Page-based memory management Ø Page table and address translation ❚ Multi-level page table Instructor: Dr. Tongping Liu ❚ Translation lookaside buffer (TLB) ❚ Demand paging ❚ Thrashing and working set ❚ Page replacement ❚ Kernel memory management ❚ User-space memory management Department of Computer Science @ UTSA 1 Department of Computer Science @ UTSA 2 Memory Virtual Memory N ❚ The ideal memory is ❚ Basic idea: allow OS to allocate 2 Ø Very large more memory than the real Auxiliary Ø Very fast regions Ø Non-volatile (doesn’t go away when power is turned off) ❚ Program uses virtual addresses ❚ The real memory is Ø Addresses local to the process Ø Limited by # of bits in address (32/64) Ø Not very large Stack Ø 32 bits: 4GB Ø Not very fast Ø 64 bits (actually 48 bits): 256TB Ø Affordable (cost) ! ❚ Virtual memory >> physical memory Heap ⇒ Pick any two… ❚ Memory management goal: make the reality Text similar to the idea world as much as possible J 0 Department of Computer Science @ UTSA 3 Department of Computer Science @ UTSA 4 1 Motivations for Virtual Memory Virtual and Physical Addresses ❚ Efficient Use of Limited Memory" ❚! Virtual address space CPU chip Ø!Keep only active address space in the memory" Ø! Determined by the instruction width Ø!Some non-active parts can be stored on the disk " CPU MMU Ø! Same for all processes ❚! Simplify Memory Management" Virtual addresses" ❚! Physical memory indexed by Ø!Each process “gets” the same full, linear address space" from CPU to MMU physical addresses ❚! Isolates Executions of Multiple Processes" Memory Ø! Limited by bus size (# of bits) Ø!One process can’t interfere with another’s memory" Ø! Amount of available memory ü!They operate in different address spaces" Physical addresses" Ø!User process cannot access privileged information" on bus, in memory ü!Different sections of address spaces have different permissions" Disk" controller Department of Computer Science @ UTSA 6 Outline Page-Based Memory Management ❚! Virtual memory ❚! Virtual address 60–64K - 56–60K - ❚! Page-based memory management Ø! Divided into pages 52–56K - ❚! Physical memory 48–52K - Ø!Page table and address translation 44–48K 5 Ø! Divided into frames 40–44K 1 36–40K - ❚! Multi-level page table 32–36K - 28–32K 3 7 28–32K ❚! Translation lookaside buffer (TLB) ❚! Page vs. Frame 24–28K - 6 24–28K Ø! Same size address block 20–24K - 5 20–24K ❚! Demand paging 16–20K 0 4 16–20K Ø! Unit of mapping/allocation 12–16K - 3 12–16K 8–12K - 2 8–12K ❚! Thrashing and working set 4–8K 4 1 4–8K ❚! Page replacement ❚! A page is mapped to a frame 0–4K 7 0 0–4K Virtual space Physical" Ø! All addresses in the same virtual memory ❚! Kernel memory management page are in the same physical frame ❚! User-space memory management à offset in a page Department of Computer Science @ UTSA 7 Department of Computer Science @ UTSA 8 2 Page Table Translate Virtual to Physical Address ❚! Each process has one page table 15 ❚! Split virtual address (from CPU) into two pieces Ø! Map page number à physical frame number Ø!Page number (p) ❚! Number of PTEs in page table Ø!Page offset (d) Ø! Number of total pages in virtual space Frame 6 Ø! Not just the pages in use Frame 1 ❚! Page number ❚! Page table is checked for Ø!Index into an entry of the page table that holds the every address translation Frame 3 corresponding physical frame number Ø! Where to store page table? ❚! Page offset Frame 0 ❚! Not all pages need to be mapped to frames Ø!Position inside a page at the same time ❚! Page size = 2d bytes: determined by offset size ❚! Not all physical frames need to be used 1 Frame 4 0 Frame 7 Page table Department of Computer Science @ UTSA 9 Department of Computer Science @ UTSA 10 Logic Address An Example of Virtual/Physical Addresses n! Suppose logical address space is 2m and page size is ❚! Example: 2n, so the number of pages is 2m / 2 n , which is 2m-n " Ø! 64 KB virtual memory Ø! 32 KB physical memory ❚! Logical Address (m bits) is divided into:" Ø! 4 KB page/frame size à 12 bits as offset (d) Ø! Page number (p) – used as an index into a page table which contains frame number of physical memory" Page #:4bits Offset: 12 bits Ø! Page offset (d) – combined with base address to define the Virtual address: 16 bits How many virtual pages? physical memory address that is sent to the memory unit" page number" page offset" Frame #:3bits Offset: 12 bits p" d" physical address: 15 bits m - n! n! How many physical frames? Department of Computer Science @ UTSA 12 3 In-Class Exercise In-Class Exercise ❚ For an embedded small computer supporting up ❚ For an embedded small computer supporting up to 1k bytes physical memory, where its virtual to 1k bytes physical memory, where its virtual address is 12 bits. Suppose that the size of address is 12 bits. Suppose that the size of page/frame is 128 bytes. Use a figure to page/frame is 128 bytes. Use a figure to illustrate the physical and virtual address that illustrate the physical and virtual address that shows the number of bits for offset and shows the number of bits for offset and frame/page number for one level page table. frame/page number for one level page table. • What is the number of virtual pages for each process? • How many physical frames in total? • How many entries in page table for each process? Department of Computer Science @ UTSA 13 Department of Computer Science @ UTSA 14 In-Class Exercise Address Translation ❚ # of virtual pages: ❚ Example: Page #:5bits Offset: 7 bits 2^12/128= 2^5 = 32 Ø 64 KB virtual memory Virtual address: 12 bits Ø 32 KB physical memory Ø 4 KB page/frame size à 12 bits as offset (d) ❚ # of physical frames 1K/128=8 Page #:4bits Offset: 12 bits Frame #:3bits Offset: 7 bits How many virtual pages? Virtual address: 16 bits physical address: 10 bits Address " ❚ # of page table entries Translation 32 Frame #:3bits Offset: 12 bits physical address: 15 bits How many physical frames? Department of Computer Science @ UTSA 15 Department of Computer Science @ UTSA 16 4 Address Translation Architecture Computing Physical Address frame number page number page offset 1. Compute the page number 0 2. Check the page table, get physical CPU p d f d 1 frame number ." page table . 0 f-1 1 3. Compute the starting address of Virtual address f ." physical frame . physical address f+1 p-1 f+2 ." p f ." 4. Compute the physical address ." . " physical memory 17 Department of Computer Science @ UTSA 18 Computing Physical Address Computing Physical Address Virtual address 0x44, offset 0x44 Virtual address 0x224, offset 0x24 1. Compute the page number 1. Compute the page number Page number is #0 Page number is #4 2. Check the page table, get physical 2. Check the page table, get physical frame number frame number Frame number is #2 Frame number is #3 3. Compute the starting address of 3. Compute the starting address of physical frame physical frame Start Address = 2 * 0x80 = 0x100 Start Address = 3 * 0x80 = 0x180 4. Compute the physical address 4. Compute the physical address PhysicalAddress = 0x100 + 0x44 = 0x144 PhysicalAddress = 0x180 + 0x24 = 0x1A4 Department of Computer Science @ UTSA 19 Department of Computer Science @ UTSA 20 5 . Limitations of One-level Page Table Page/Frame Size ❚ Page table should contain all pages of virtual space ❚ Determine the number of bits in offset! Ø Otherwise, some addresses can’t be accessed. ❚ Smaller page size " Ø!+ Less internal fragmentation" ❚ All entries should be physically continuous Ø!- Larger page table: require more than one frame, hard to allocate!" Ø Proof by contradiction. If the index is not continuous, we will need another mechanism to tell us where has a hole or ❚! Larger page size " not Ø!+ Smaller page table and less overhead to track them" Ø!+ More efficient to transfer to/from disk " Ø!- More internal fragmentation, wasting memory" Department of Computer Science @ UTSA 21 . Size of Page Table Size of Page Table ❚! If a computer has 22 bits of logical address (4 MB), ❚! Modern Machine and supports the physical memory up to 1 MB. The Ø! 32 bits virtual address page/frame size is 1KB. " Ø! Size of one page/frame is 4KB (12 bits) ❚! Page table size Virtual addr: P#:12 bits Offset: 10 bits Ø! # of virtual pages: 32 – 12 = 20 bits à 220 PTEs Ø! Page table size = PTE size * 220 = 4 MB per process à 210 frames Physical addr: F#:10 bits Offset: 10 bits Ø!Number of pages: 12 bits à 4K pages ❚! If there are 128 processes, and physical memory is 1 GB Ø!Size of page table: Ø! Page tables occupy 128 * 4MB = 512 MB §! Each page entry must have at least 10 bits à 2 bytes Ø! 50% of memory will be used by page tables §! 4K * 2 bytes = 8KB à requires 8 consecutive frames How can we get smaller page table?! Department of Computer Science @ UTSA 24 6 Outline Two-Level Page Tables ." . " ❚ Solution: multi-level page tables 220 ❚ Virtual memory ." ❚ Virtual address: three parts 657 . ❚ Page-based memory management ." Ø Level-one page number (10 bits) . " ." ." . Ø Page table and address translation Ø Level-two page number (10 bits) 401. ." . " ❚ Multi-level page table Ø Offset (12 bits) 125 ." ." . ❚ Translation lookaside buffer (TLB) ." 613 ❚ PTE in 1st level page table . ." ." . " . ❚ Demand paging contains the address of physical ." frame for 2nd level page table 961 .
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