Package Characterization Techniques and Evaluation of a Plastic Package for Mm-Wave Applications

Dissertation

Package Characterization Techniques and Evaluation of a Plastic Package for mm-Wave Applications

Der Technischen Fakultätder Universität Erlangen-Nürnberg zur Erlangung des Grades

DOKTOR-INGENIEUR

vorgelegt von

Dipl.-Ing. (Univ.) Mario Engl

Erlangen - 2006 Dissertation

Methoden der Gehäusecharakterisierung und Evaluierung eines Plastikgehäusesfür Anwendungen im Millimeterwellenbereich

Der Technischen Fakultätder Universität Erlangen-Nürnberg zur Erlangung des Grades

DOKTOR-INGENIEUR

vorgelegt von

Dipl.-Ing. (Univ.) Mario Engl

Erlangen - 2006 Als Dissertation genehmigt von der Technischen Fakultätder Universität Erlangen-Nürnberg

Tag der Einreichung: 23. 1. 2006

Tag der Promotion: 24. 3. 2006

Dekan: Prof. Dr.-Ing. Alfred Leipertz

1. Berichterstatter: Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel

2. Berichterstatter: Prof. Dr.-Ing. Georg B¨ock Abstract

This thesis presents the evaluation of a novel and innovative low-cost leadless package concept (TSLP - Thin Small Leadless Package) for applications in the high frequency and mm-wave region. Packages play a major part in todays semiconductor industry. In order to cope with future technology trends, the need for new package solutions arises. The TSLP contributes to actual industrial demands, which, among others, include ongoing miniaturization, improved heat transfer or extended high frequency capabilities. Another focus of this work lies on the electrical performance of the package concept TSLP. For the performance evaluation of the TSLP, package characterization techniques in time domain and frequency domain are investigated and applied. Especially the versatile use of time domain techniques is demonstrated. A measurement setup with high spatial resolution in the sub-mm region is presented. This allows impedance characterization of packages, failure analysis and fault localization. Frequency characterization is done by means of scattering parameters. A de-embedding technique based on reflection measurements and a port reduction method is introduced to calculate the performance of packages. Further, the package concept TSLP is analyzed by means of electromagnetic field simulation. To demonstrate the high frequency capabilities of the package, RF and mm-wave applications are assembled in TSLP and measured. Actual integrated circuits operating in the upper GHz region, including a fully assembled and fully operational 79 GHz voltage controlled oscillator, are presented for the first time in a low-cost plastic package. The obtained results show an outstanding potential of the package concept TSLP for high frequency applications. Zusammenfassung

Gehäusetechnologien im Umfeld der heutigen Halbleiterindustrie kommt eine zunehmend bedeutende Rolle zu. Die große Herausforderung von neuen Gehäuse- konzepten besteht darin, den rasanten technischen Fortschritt und die rasch zunehmende Leistungkapazität im Bereich integrierter Schaltungen zu beglei- ten und zur Wirkung zu bringen. In diesem Sinne präsentiert diese Arbeit ein innovatives Gehäusekonzept (TSLP - Thin Small Leadless Package), welches aus wirtschaftlicher und technischer Sicht eine attraktive Lösung fur¨ aktuelle und zukunftige¨ Anwendungen im Hochfrequenz- und Millimeterwellenbereich dar- stellt. Das entwickelte Konzept trägt Attributen wie Miniaturisierung, verbesserte Wärmeabfuhr und erweiterte Hochfrequenzeigenschaften Rechnung. Ein wesent- liches Ziel dieser Arbeit ist uber¨ die elektrische Leistungsfähigkeit des Package- konzeptes TSLP definiert. Um die Beweisfuhrung¨ der Leistungsfähigkeit antreten zu können, wurden sowohl numerische als auch experimentelle Untersuchungen durchgefuhrt.¨ Mit dem Ziel, Gehäuse im Hochfrequenzbereich zu charakterisieren, wurden geeignete Messtechniken im Zeit- und Frequenzbereich untersucht und angewandt. Besonders die Vorteile der vielseitig einsetzbaren Zeitbereichs- charakterisierung konnten dargestellt werden. Der vorgestellte Messaufbau, welcher die geforderte Sub-Millimeterauflösung erreicht, eignet sich sowohl fur¨ Im- pedanzcharakterisierung der Gehäuse als auch fur¨ Fehleranalyse und Lokalisie- rung von Defekten. Fur¨ die Charakterisierung der Gehäuse im Frequenzbereich werden Streuparameter verwendet. Im Bestreben mittels Eintormessungen die elektrischen Parameter des Gehäuses zu extrahieren wird die Anwendung einer De-embedding-Methode beschrieben. Um die Leistungsfähigkeit des TSLP demonstrieren zu können, wurden integrierte Hochfrequenzschaltungen eingebaut und gemessen. Die Resultate zeigen, dass sich das Packagekonzept TSLP ganz hervorragend fur¨ Anwendungen im Hochfrequenz- und Millimeterwellenbereich eignet. Dies wird durch einen komplett aufgebauten und voll funktionsfähigen 79 GHz spannungskontrollierten Oszillator (VCO) besonders deutlich. Die erstma- lige aus technischer Sicht erfolgreiche Anwendung von kostengunstigen¨ Plastik- gehäusen fur¨ Hochfrequenzanwendungen stellt somit auch auf Basis wirtschaftlicher Uberlegungen¨ eine attraktive Lösung fur¨ die Industrie dar. Contents

1 Introduction 1 1.1 StateoftheArt...... 2 1.2 ScopeofWork...... 4

2 Simulation Techniques 6 2.1 SimulationFundamentals...... 7 2.2 FiniteElementMethod...... 8 2.3 FiniteIntegrationTechnique ...... 13 2.4 Comparison ...... 17 2.5 Validation ...... 18 2.6 OtherMethods ...... 20

3 Package Fundamentals 22 3.1 PackageTypes ...... 22 3.1.1 Leadframe Packages ...... 22 3.1.2 Laminate Packages ...... 23 3.1.3 Leadless Packages ...... 26 3.1.4 Chip Scale Packages ...... 27 3.2 PackageElements...... 29 3.2.1 First Level Interconnects ...... 29 3.2.2 Second Level Interconnects ...... 41 3.2.3 InterconnectStructures...... 44 3.3 High Frequency Packaging Guidelines ...... 46 3.4 The Leadless Package Concept TSLP ...... 48 3.4.1 AssemblyProcess...... 48 3.4.2 Package Properties ...... 50

4 Characterization Techniques 57 4.1 Material Characterization ...... 57 4.1.1 Capacitance Measurements ...... 58 4.1.2 Filled Transmission Guides ...... 58 4.1.3 Split Post Resonator Technique ...... 60 4.2 Calibration ...... 63 4.2.1 Short-Open-Load-Through(SOLT) ...... 65 4.2.2 Through-Reﬂect-Line and Line-Reﬂect-Line ...... 65

i CONTENTS ii

4.2.3 Time Domain De-embedding ...... 66 4.2.4 Gating...... 67 4.2.5 Application to Package Characterization ...... 69 4.3 MeasurementSetup...... 71 4.4 Frequency Domain Characterization Techniques ...... 73 4.4.1 ScatteringParameters ...... 73 4.4.2 De-embedding...... 74 4.4.3 Frequency Domain Package Characterization ...... 77 4.5 Time Domain Characterization Techniques ...... 81 4.5.1 Realization ...... 84 4.5.2 Time Domain Package Characterization ...... 88

5 Experimental Results 95 5.1 17GHzWLANReceiver ...... 95 5.2 30 GHz Frequency Divider ...... 100 5.2.1 Flip Chip Version ...... 101 5.2.2 Wirebond Version ...... 104 5.3 77GHzSchottkyDiodes ...... 105 5.4 79GHzVCO ...... 107

6 Conclusion and Outlook 112

A Einleitung 114 A.1 StandderTechnik ...... 115 A.2 MotivationundZielederArbeit ...... 117

Bibliography 119

Curriculum Vitae 130

Acknowledgements 131 Inhalt

1 Einleitung 1 1.1 Stand der Technik ...... 2 1.2 Motivation der Arbeit ...... 4

2 Simulationsmethoden 6 2.1 Grundlagen der Simulation ...... 7 2.2 Finite Elemente Methode ...... 8 2.3 Finite Integrationstechnik ...... 13 2.4 Vergleich der Methoden ...... 17 2.5 Validierung ...... 18 2.6 Weitere Methoden ...... 20

3 Gehäusegrundlagen 22 3.1 Gehäusetypen ...... 22 3.1.1 Leadframe-Gehäuse...... 22 3.1.2 Laminat-Gehäuse ...... 23 3.1.3 Leadless-Gehäuse ...... 26 3.1.4 Chip Scale-Gehäuse ...... 27 3.2 Gehäusestrukturen ...... 29 3.2.1 PrimäreVerbindungstechnologien ...... 29 3.2.2 SekundäreVerbindungstechnologien ...... 41 3.2.3 Durchkontaktierungen ...... 44 3.3 Hochfrequenz-Gehäusedesign...... 46 3.4 Das Gehäusekonzept TSLP ...... 48 3.4.1 Herstellprozess ...... 48 3.4.2 Eigenschaften des TSLP ...... 50

4 Methoden der Gehäusecharakterisierung 57 4.1 Materialcharakterisierung ...... 57 4.1.1 Kapazitätsmessung ...... 58 4.1.2 GefüllteWellenleiter ...... 58 4.1.3 Split-Post Resonatoren ...... 60 4.2 Kalibrierverfahren ...... 63 4.2.1 Short-Open-Load-Through (SOLT) ...... 65 4.2.2 Through-Reflect-Line und Line-Reflect-Line ...... 65

iii INHALT iv

4.2.3 De-embedding im Zeitbereich ...... 66 4.2.4 Gating ...... 67 4.2.5 Anwendung auf Gehäusecharakterisierung ...... 69 4.3 Messaufbau ...... 71 4.4 Charakterisierung im Frequenzbereich ...... 73 4.4.1 Streuparameter ...... 73 4.4.2 De-embedding ...... 74 4.4.3 Gehäusecharakterisierung ...... 77 4.5 Charakterisierung im Zeitbereich ...... 81 4.5.1 Realisierung ...... 84 4.5.2 Gehäusecharakterisierung ...... 88

5 Experimentelle Untersuchungsergebnisse 95 5.1 17 GHz WLAN Empf¨anger ...... 95 5.2 30 GHz Frequenzteiler ...... 100 5.2.1 Flip Chip Version ...... 101 5.2.2 Wirebond Version ...... 104 5.3 77 GHz Schottky Dioden ...... 105 5.4 79 GHz spannungsgesteuerter Oszillator ...... 107

6 Ausblick 112

A Einleitung 114 A.1 Stand der Technik ...... 115 A.2 Motivation und Ziele der Arbeit ...... 117

Literaturverzeichnis 119

Lebenslauf 130

Danksagung 131 List of Figures

1.1 Package development drivers ...... 2

2.1 Valid (a) and invalid (b) two-dimensional FEM mesh ...... 9 2.2 Discretization in Finite Integration Technique ...... 14 2.3 Grid G and dual grid G˜ ...... 16 2.4 Photograph and model of via interconnects ...... 18 2.5 Scattering parameter S11 of a via interconnect (Z0 = 50 Ω) . . . . 19 2.6 Scattering parameter S21 of via interconnect (Z0 = 50 Ω) . . . . . 19 2.7 Photographandmodelofwirebond ...... 20 2.8 Scattering parameter S11 of wirebond (Z0 =50Ω)...... 20 2.9 Scattering parameter S21 of wirebond (Z0 =50Ω)...... 21

3.1 Typical leadframe package [1] ...... 23 3.2 Typical laminate package (BGA) [1] ...... 24 3.3 Cross-section of BGA package ...... 24 3.4 TypicalBGAsubstratelayout ...... 25 3.5 Typical leadless package (VQFN) - top view and footprint[1] . . . 26 3.6 Cross-section of a leadless package (TSLP) ...... 27 3.7 Typical Chip Scale Packages [1] ...... 28 3.8 Thin film technology used in CSPs ...... 29 3.9 Photograph of high power transistor ...... 30 3.10 Highdensitywirebonding ...... 30 3.11 Influence of tolerances on S11 of a short wirebond (Z0 = 50 Ω) . . 32 3.12 Influence of tolerances on S21 of a short wirebond (Z0 = 50 Ω) . . 33 3.13 Influence of tolerances on S11 of a long wirebond (Z0 = 50 Ω) . . . 33 3.14 Influence of tolerances on S21 of a long wirebond (Z0 = 50 Ω) . . . 34 3.15 Magneticfieldinsideametaltrace ...... 35 3.16 Equivalent circuit model of two coupled wirebonds with a length of1mm ...... 36 3.17 Comparison model and EM results of two coupled wirebonds with a length of 1 mm (Z0 =50Ω) ...... 37 3.18 Comparison model and EM results of two coupled wirebonds with a length of 1 mm - coupling coefficient (Z0 =50Ω) ...... 37 3.19 Photograph and cross section of flip chip bumps on test wafer . . 38 3.20 Equivalent circuit model of flip chip bumps ...... 40

v LIST OF FIGURES vi

3.21 Comparison model and EM results of flip chip bumps (Z0 = 50 Ω) 40 3.22 Comparison model and EM results of flip chip bumps - coupling coefficient (Z0 =50Ω) ...... 41 3.23 Equivalent circuit model of solder ball ...... 42 3.24 Comparison model and EM results of BGA balls (Z0 = 50 Ω) . . . 43 3.25 Viainterconnectstructures[2] ...... 45 3.26 Equivalent circuit model of a two-layer via interconnect...... 45 3.27 Comparison model and EM results of a via interconnect (Z0 = 50 Ω) 46 3.28 Comparison of package size to sugar grain ...... 48 3.29TSLPcontactpad ...... 49 3.30 TSLP leadframe with flip chip samples ...... 50 3.31 TSLPassemblyprocess...... 51 3.32 AdvancedTSLPleadframe...... 52 3.33 TSLP interconnect performance - S11 (Z0 =50Ω)...... 53 3.34 TSLP interconnect performance - S21 (Z0 =50Ω)...... 53 3.35 Pad width influence on S11 using wirebond interconnects (Z0 = 50 Ω) 55 3.36 Pad width influence on S21 using wirebond interconnects (Z0 = 50 Ω) 55 3.37 Pad width influence on S11 using flip chip interconnects (Z0 = 50 Ω) 56 3.38 Pad width influence on S21 using flip chip interconnects (Z0 = 50 Ω) 56

4.1 Filledtransmissionguides ...... 59 4.2 Split-post resonator and sample materials ...... 61 4.3 Resonance shift due to material in resonator (Z0 = 50 Ω) . . . . . 62 4.4 Coaxial to microstrip technology in universal test ﬁxture . . . . . 63 4.5 Stepbeforeandaftertransition ...... 64 4.6 TRL and Time Domain De-embedding planar standards . . . . . 67 4.7 Step before and after time domain de-embedding ...... 68 4.8 Stepbeforegating...... 68 4.9 Stepaftergating ...... 69 4.10 Comparison microstrip TRL and Time Domain De-embedding method (Z0 =50Ω)...... 70 4.11 Comparison microstrip TRL and coaxial TRL with applied gate (Z0 =50Ω)...... 71 4.12 Measurementsetup ...... 72 4.13 Two-port network and traveling waves ...... 73 4.14 Theoryofde-embeddingprocedure ...... 76 4.15 De-embedded transmission line (Z0 =50Ω) ...... 77 4.16Layoutoftestchip ...... 78 4.17 Scattering parameter S11 of TSLP-24 (Z0 =50Ω)...... 79 4.18 Scattering parameter S21 of TSLP-24 (Z0 =50Ω)...... 79 4.19 Scattering parameter S11 of BGA (Z0 =50Ω) ...... 80 4.20 Scattering parameter S21 of BGA (Z0 =50Ω) ...... 80 4.21 TDRoperationprinciple ...... 81 4.22 Common discontinuities ...... 82 LIST OF FIGURES vii

4.23 Impact of risetime on spatial resolution ...... 84 4.24 TDR with source enhancement module [3] ...... 85 4.25 TDR measurement setup block diagram ...... 86 4.26 TDR and TDR with SEM Comparison ...... 87 4.27 Bandwidth influence on voltage step risetime ...... 88 4.28 Output step using different window functions...... 89 4.29 Photograph of TSLP and BGA packages on test modules . . . . . 89 4.30 Voltage profile of a BGA package ...... 90 4.31 Bandwidth influence on package characterization ...... 91 4.32 Voltage profile of a BGA package - TDR and VNA comparison . . 92 4.33 Different signal pathways leading to on-chip short standard.... 93 4.34 Broken bondwire voltage profile ...... 93 4.35 X-ray photograph of a BGA package ...... 94 4.36 TSLPvoltageprofile ...... 94

5.1 Polishedcutimage ...... 96 5.2 Receiver block diagram ...... 97 5.3 Receivermodule...... 97 5.4 Receivergain ...... 98 5.5 Receiver two tone measurement ...... 99 5.6 Frequency divider block diagram ...... 100 5.7 Flip-ﬂopschematic ...... 101 5.8 Frequency divider chip photograph ...... 101 5.9 Frequency divider soldered on Rogers RO4003 substrate ...... 102 5.10 Frequency divider polished cut image ...... 103 5.11 Frequency divider input sensitivity - ﬂip chip version ...... 103 5.12 Frequency divider input sensitivity - wirebond version ...... 104 5.13 77 GHz Schottky diodes on Rogers RO3003 substrate ...... 105 5.14 Scattering parameter S11 - VBIAS =0V(Z0 = 50 Ω) ...... 106 5.15 Scattering parameter S11 - VBIAS = 0.7 V (Z0 = 50 Ω) ...... 107 5.16 Photograph of VCO die on TSLP leadframe ...... 108 5.17 79 GHz VCO in TSLP-24 on evaluation board ...... 109 5.18 79GHzVCOmeasurementsetup ...... 110

A.1 Trends in der Geh¨auseentwicklung ...... 115 List of Tables

2.1 Maxwell’s equations and their discretized equivalents ...... 16

3.1 Manufacturing tolerances (exemplary values) ...... 31 3.2 Minimum, nominal and maximum projected wirebond lengths . . 32

4.1 Measurement results of various mold compounds ...... 62

5.1 Receiver performance summary ...... 99 5.2 VCO output power (VSS = 5.7 V, I =387mA) ...... 110 5.3 VCO output power (VSS = 6 V, I =413mA) ...... 111

viii Chapter 1

Introduction

The fast-paced semiconductor industry might be considered to be one of the biggest growing and fastest developing industry branches. According to Moore’s law, the transistor density on an integrated circuit doubles every 18 months. Thus, integration density dramatically increases continuously. This leads to ex- treme shrinkage of chip dimensions, pad sizes and pitches toward nano-technology. However, size and interfaces in human world keeps constant. Therefore, the chal- lenges for assembly and interconnect technology, which are the interface between the semiconductor chip and human world, steadily increase. Hence, the need for innovative package solutions arises in order to cope with the advances of the semiconductor industry and future high performance applications. The necessity of innovative advancements and technological improvements might be characterized by summarizing industrial demands on semiconductor packages as illustrated in Fig. 1.1. These demands are identified by numerous package roadmaps, e.g. the ITRS [4] or JISSO [5]. Every individual development topic presented in Fig. 1.1, such as improved thermal performance, reduced size or improved high frequency performance, leads to a higher functionality of the package solution. However, based on commercial considerations, the most important issue concerning packaging and package development seems to be time-to-market in combination with cost. From the technical point of view, packages are considered to be indispensable complement technology in combination with semiconductor applications. Packages provide protection of the integrated circuit from external hazards, e.g. mechanical stress, humidity and similar environmental influences. Further, packages improve the thermal performance of the chip. The heat produced by the circuit is transferred through the package to external heat sinks. This is especially important for power applications. Further, complex integrated circuits, e.g. receiver implementations for mobile communications, require a flexible redistribution concept and common supply- and return current paths. These demands are provided by proper package solutions. Lastly, packages enable easy handling of the integrated applications and board level assembly.

1 CHAPTER 1. INTRODUCTION 2

Functionality (System Integration)

Speed Size

CostCost & TimeTime to MarketMarket

Thermal Low/High Performance Power

Reliability & Failure Analysis

Figure 1.1: Package development drivers

1.1 State of the Art

A wide array of diﬀerent semiconductor package technologies exist nowadays. Most of today’s semiconductor packages can be grouped into the following package families, depending on size, assembly process and structural composition of the package:

Leadframe Packages (DIP, SOP, ...) • Laminate Packages (BGA, LFBGA, LGA, ...) • Leadless Packages (VQFN, TSLP, ...) • Chip Scale Packages (CSPs) • Wafer Level Packages (WLP, UWLP, ...) • Leadframe packages represent a cost-effective plastic packaging solution, however, forfeits regarding electrical performance are high in most cases [6]. Laminate packages (e.g. BGA) allow a high contact density and improved electrical performance [7]. Package design of BGAs is very flexible due to the assembled substrate, which is used for redistribution purposes and common power- and ground nets. Assembly cost are higher compared to leadframe packages, though. Originally, most plastic packages are not intended for applications in the upper GHz- and mm-wave region[8]. The quite recently emerged Chip Scale Packages [9][10] and CHAPTER 1. INTRODUCTION 3 leadless packages (e.g. [11]) aim at high frequency applications. Package dimensions are small and signal pathways very short. In addition, manufacturing cost are low. For RFICs (radio frequency integrated circuits), ceramic packages are typically utilized up to now [12][13][14]. Nonetheless, the manufacturing and assembly of these packages is cost-intensive, which is a major disadvantage of ceramic chip carriers. Further, ceramic packages are subject to manufacturing tolerances and shrinkage during assembly to a great extend. As already mentioned, many of today’s low-cost package types are not suited for high frequency applications since parasitic elements of the package seriously deteriorates the overall performance of the application. For instance, leads of leadframe packages act as large inductive elements which cause power loss, impedance mismatch and detuning. Thus, the need for novel semiconductor package technologies arises in order to cope with future high performance integrated circuits. Potential solutions have been proposed, e.g. [15][16][17], however, none actual high frequency applications demonstrating the performance are presented. This thesis presents the low-cost leadless package concept TSLP. Leadless packages are considered excellent candidates for RF applications [18]. The package makes an economical attractive contribution to the actual industrial demands shown in Fig. 1.1. So far, package characterization mainly focused on thermal and mechanical issues as exemplary presented in [16]. Electrical characterization of packages and package structures played a minor role and has been often neglected. The electrical modeling of packages has been carried out mostly in the lower frequency region up to a few GHz [19][20]. However, with increasing operating frequencies and increasing data rates, the electrical performance, especially the high frequency performance, of packages has a determining impact on the overall behavior of applications. At higher frequencies, effects such as crosstalk occur. Further, package elements may not be considered as lumped elements any longer. Instead, package components need to be treated as distributed elements since the wavelength of the operating frequencies move into the range of package dimensions. From an electrical point of view, the impact of the package on the application cannot be neglected anymore. As a consequence, electrical package characterization in the high frequency region to determine the performance of the package and package structures is a major topic nowadays [4]. Especially time domain techniques can be used in a very versatile manner. Time domain reflectometry allow impedance characterization of interconnects and package structures [21][22], failure analysis and fault localization [23][24][24]. These techniques have been applied to rather large devices up to now, for instance, impedance analysis on transmission lines, printed circuit boards or large leadframe packages [25][26][27]. As dimensions of packages decrease, the application of time domain measurement techniques becomes more difficult. The risetime is the limiting factor, since it determines the spatial resolution. Actual time domain reflectometers available on the market are CHAPTER 1. INTRODUCTION 4 capable to generate voltage steps with a risetime down to 35 ps [28], which yields a spatial resolution of about 2.6 mm. To characterize actual packages with dimensions in the millimeter region a sub-millimeter spatial resolution is absolutely mandatory, though. Up to now, accurate and high resolution time domain characterization of modern package types was not achieved due to these risetime limitations.

1.2 Scope of Work

A novel and innovative leadless package concept (TSLP - Thin Small Leadless Package) is presented in this thesis. This package concept attempts to enable applications operating in the high frequency and mm-wave region. The motivation of this work is the electrical performance evaluation of the leadless package concept TSLP, especially with respect to high frequency performance. The package was simulated using 3D electromagnetic ﬁeld solver software packages. In this analysis step the package geometry was varied to determine its impact on the electrical performance. The performed simulations show promising results regarding the high frequency performance of the package. A major part of this work deals with package characterization techniques. To perform measurements on the package, time as well as frequency domain package characterization techniques have been considered and developed. So far, time domain techniques have not been employed for characterization of actual package technologies due to the small dimensions of today’s semiconductor packages. A major goal of this work was the evaluation of time domain techniques for package characterization. This further includes an appraisal and examination regarding construction possibilities and their realization, their properties and sub- sequently the applicability to package characterization. A time domain measurement methodology with an achieved high spatial sub-millimeter resolution is presented. Regarding frequency domain measurements, packages are characterized up to 65 GHz. A de-embedding technique based solely on one-port measurements to obtain the scattering parameter of the package itself is described. Finally, actual high frequency components were assembled in TSLP to show its capabilities and suitability for applications in the mm-wave region. The perfor- mances of the fully assembled integrated circuits were measured and give insight into the suitability of the package for high frequency applications. The considered circuits range from discrete components to complex parts of communication systems to cover a wide array of applications. The superior mm-wave performance of the package is demonstrated by a fully packaged and fully operational 79 GHz voltage controlled oscillator. Chapter 2 gives an overview of simulation techniques, which were employed in the course of this thesis. Two of the most common simulation approaches are highlighted, the Finite Element Method and the Finite Integration Technique. CHAPTER 1. INTRODUCTION 5

Their advantages and disadvantages are pointed out. Further, simulation results and their accuracy are validated by measurements. Chapter 3 deals with fundamental items of packaging and actual package technologies. Common packages and package elements are described and their performance is analyzed. In addition, electrical compact models describing the performance of these package elements are developed. This is especially important for quick analysis of package designs. Further, the leadless package concept TSLP and its advantages compared to actual packages are introduced in this chapter. In Chapter 4 package characterization techniques are explained. Time and frequency domain techniques as well as package material characterization techniques have been observed in the course of this thesis. Time domain measurements yield impedance profiles of the device under test. Further, time domain techniques are very well suited for failure analysis and fault localization. In addition, scattering parameters describing the high frequency performance up to 65 GHz of the measured packages are obtained from frequency domain measurements. The assembled high frequency applications is the central theme of Chapter 5. Ac- tual RF components are fully assembled in a low-cost plastic package and characterized for the first time. The performance of these fully assembled applications is presented in this chapter. The applications range from discrete components like 80 GHz Schottky diodes using wirebond and flip chip interconnect technology to complex parts of communication systems, for instance a 17 GHz wireless local area network receiver. The measured results demonstrate the suitability of the package concept TSLP for actual and future high performance applications operating in the upper frequency and mm-wave region. This is underlined by a fully packaged and operational 79 GHz voltage controlled oscillator. Chapter 6 gives concluding remarks and additionally highlights future development topics. For the first time plastic packages for high frequency applications can be presented which might be considered as economic attractive contribution to industry demands. Chapter 2

Simulation Techniques

In past times, the manufacturing of package prototypes to determine the performance of packages and package structures was inevitable. Especially the optimization of these structures was a time- and most of all cost-consuming task. Optimization required several manufacturing and analysis cycles while gradually improving the performance in each cycle. Thus, the entire package design and production cycle from first scratch to the final design demanded an extensive amount of time, money and manufacturing resources. A possibility to reduce production cycles and thus increase Time-to-Market, one major keyword in today’s indus- tries, simulation software can be utilized. In past times, computer were not able to handle complex problems by simulation. Simulation time added up to several days with ease. Computer performance increased dramatically in the past years, though. This lead to an increasing appliance of simulation software. Today, electromagnetic field simulators are capable to handle more complex problems while providing higher accuracy. Simulations are performed within a few hours. Hence, the electrical performance of a design can be predicted using electromagnetic field simulation tools before manufacturing a first prototype. Further, it is possible to quickly analyze several designs and optimize them afterwards. Thus, time-to- market is reduced, which is an important advantage when the rapid advances in semiconductor technology are considered. Several package structures were simulated using common electromagnetic field simulators available on the market. This chapter gives a brief overview about the simulation techniques employed by common software tools. It starts with the introduction of Maxwell’s equations, the fundamental equations of electrodynamics, and simulation basics. Next, the Finite Element Method and Finite Integration Technique are briefly explained. These are the calculation methods which are implemented by the utilized simulation software. Further, advantages and disadvantages are discussed and outstanding properties are highlighted. Fi- nally, a validation of simulation results by a comparison to measurement results of manufactured structures is presented.

6 CHAPTER 2. SIMULATION TECHNIQUES 7

2.1 Simulation Fundamentals

Electromagnetic ﬁeld theory is based on Maxwell’s equations, which are the fundamental equations of electrodynamics. The Maxwell’s equations in diﬀerential form are

~ B~ = 0 (2.1) ∇ · ~ D~ = ρ (2.2) ∇ · ~ H~ = J~ + ∂tD~ (2.3) ∇ × ~ E~ = ∂tB~ (2.4) ∇ × − where the following quantities are used:

B~ : magnetic flux density [T] • D~ : electric flux density [C/m2] • ρ: electric charge density [C/m3] • H~ : magnetic field strength [A/m] • J~: current density [A/m2] • E~ : magnetic field strength [V/m]. •

Further, the magnetic field strength H~ and electric field strength E~ are linked to the magnetic flux density B~ and the electric flux density D~ by the expressions

B~ = µ0µrH~ (2.5)

D~ = ε0εrE~ (2.6)

−7 where µ0 is the magnetic field constant (µ0 = 4π 10 Vs/Am), µr the perme- · −12 ability of the material in use, ε0 the electric field constant (ε0 = 8.854 10 · F/m), and εr the permittivity of the material. The Maxwell’s equations allow a complete characterization of the electromagnetic field within any arbitrary 3D structure. All common electromagnetic field computation methods reduce the Maxwell’s equations in their own specific way to a linear system of equations. The resulting equations are solved afterwards. Moreover, all computational methods require a discretization of the volume. Thus, electromagnetic fields are considered only at discrete points within the volume. This reduces the amount of data to a quantity which computer systems are capable CHAPTER 2. SIMULATION TECHNIQUES 8 to handle. The field is interpolated in-between these discrete points using various interpolation techniques. This discretization is a necessary procedure in order to numerically analyze and compute complex problems and their solution by simulation software. The discretization finally allows the transfer from the common form of the Maxwell’s equations to a linear set equations. The individual computation methods yield different linear systems of equations, thus each method has its own advantages and disadvantages. Two of the most common approaches to numerically analyze electromagnetic field problems are briefly explained in this chapter. These are the Finite Element Method (FEM) and the Finite Integration Technique (FIT) [29][30][31]. The software tool Ansoft HFSS [32] uses FEM as solving algorithm while FIT is the method applied by the software package CST Microwave Studio [33]. These two electromagnetic field simulation tools are the most widespread programs available on the market to-date. For the sake of simplicity, the computation methods are not covered in full detail here. The focus rather lies on pointing out the main properties and limits, as well as advantages and disadvantages of the simulation software tools and the employed methods, respectively. This allows the user of such software packages to select the proper simulation environment for a given electromagnetic field problem. A detailed explanations of computation methods can be found in [29] and [30].

2.2 Finite Element Method

The Finite Element Method has been originally developed for mechanical and structural analysis and is very successfully utilized for mechanical and thermal problems. Later, the method was adapted for electrodynamic modeling. It was continuously enhanced for more than fifty years by now. Thus, the Finite Element Method is very advanced and well developed by now. The derivation of the Finite Element Method is mostly done by calculus of variations [29][30][31]. The variational calculus assumes a functional J(φ) of a given function φ. The solution of many physical problems can be traced back to find a function ψ, whose applicable functional J(ψ) reaches its extremum value. Thus, the functional J(ψ) has its local maximum or minimum. Applied to the determination of electromagnetic fields, the functional is generally the total energy of the system. The differential equations are replaced by an appropriate formulation of a variational problem, which requires an increased expenditure of computation time. Besides the possibility to deduce proper functionals directly from the con- ceptual formulation of the problem, it is further possible to derive functionals directly from differential equations to be solved. A more detailed description of this practice can be found in [34]. For the sake of simplicity, the following explanations assume a two-dimensional electrostatic problem. Hence, the aim is to find a solution of the electrostatic potential ϕ(~r) at a location ~r. Despite this CHAPTER 2. SIMULATION TECHNIQUES 9 simplification, the fundamental principled of the method are retained. The first step in finding a solution to a problem using FEM is the discretization of the space into small elements, so-called finite elements. The shape of these elements are either triangles or rectangles for a two-dimensional space and tetrahedrons or cuboids for a three-dimensional space, respectively. Most software tools utilize tetrahedrons. The appliance of tetrahedrons allows a great flexibility during the discretization process. The finite elements must not overlap each other and the corners of the elements must not contact the edges of other elements. Thus, only the corners of individual elements contact each other, which is a mandatory condition for the solution process. Fig. 2.1 gives an exemplary illustration of one valid and one invalid finite element mesh of a two-dimensional space, respectively.

(a) (b)

Figure 2.1: Valid (a) and invalid (b) two-dimensional FEM mesh

The next step is the determination of an interpolating functionϕ ˜(x, y). Inter- polating functions are also termed form functions. These form functionsϕ ˜(x, y) approximate the potential ϕ(x, y) within the ﬁnite element. Typically polynomials of ﬁrst or second order are used. These polynomials are

ϕ˜(x, y) = c1 + c2x + c3y (2.7) 2 2 ϕ˜(x, y) = c1 + c2x + c3y + c4x + c5xy + c6y (2.8) for triangular elements (ﬁrst and second order) and

ϕ˜(x, y) = c1 + c2x + c3y + c4xy (2.9) for rectangular elements (ﬁrst order), respectively.

The set of coefficients ci are only valid within the considered element. 3D field simulation software usually provide linear and quadratic form functions when CHAPTER 2. SIMULATION TECHNIQUES 10 tetrahedrons are used as discretization elements. While quadratic form functions provide higher accuracy, the use of linear form functions results in a reduced calculation time. All further explanations assume the utilization of triangular finite elements and linear form functions. These functions now allow the interpolation of the electrostatic potential ϕ(x, y) which is to be determined. First it is mandatory to determine the coefficients cv according to Equation 2.7, where v = 1, 2, 3. The three corners i,j,k of the element and the unknown values ϕ(xµ, yµ), (µ = i,j,k) of the potential ϕ(x, y) are considered now by

ϕµ := ϕ(xµ, yµ) = c1 + c2xµ + c3yµ. (2.10)

Equation 2.10 represents a linear system consisting of three equations and three unknowns. The coeﬃcients cv can be determined from this set of equations. These coeﬃcients are a function of the coordinates (xµ, yµ) and the potential ϕµ, hence

cv = f(ϕi, ϕj, ϕk, xi, xj, xk, yi, yj, yk). (2.11)

Inserting Equation 2.11 back into Equation 2.7 yields the expression

ϕ˜(x, y) = Nµ(x, y) ϕµ (2.12) = µ Xi,j,k for the interpolated potential within the element, where

1 Ni(x, y) = [(xjyk xkyj)+(yj yk)x +(xk xj)y] (2.13) 2Ae − − − 1 Nj(x, y) = [(xkyi xiyk)+(yk yi)x +(xi xk)y] (2.14) 2Ae − − − 1 Nk(x, y) = [(xiyj xjyi)+(yi yj)x +(xj xi)y] (2.15) 2Ae − − − and Ae denotes the area of the element. Next, the functional J(ϕ) of the potential ϕ is derived. Basis for this calculation is the stored energy in an electric ﬁeld within a volume V . The stored energy WV is deﬁned as

2 ε0εr 2 ε0εr WV = E~ dV = ~ ϕ dV. (2.16) 2 V 2 V ∇ ZZZ ZZZ Assuming a two-dimensional problem and the expression

dV = ∆z dA (2.17) · Equation 2.16 can be written as CHAPTER 2. SIMULATION TECHNIQUES 11

2 2 ε0ε ∂ ∂ W = r ∆z ϕ + ϕ dA. (2.18) V   2 ZZA ∂x ! ∂y !   If the space A with its surrounding surface area Ae is small enough, the electric ﬁeld in this area can be approximated as nearly constant and Equation 2.16 further simpliﬁes to

2 2 ε0εr ∂ ∂ WV ∆z Ae ϕ + ϕ . (2.19) ≈ 2  ∂x ! ∂y !    A functional JA(ϕ) of a single ﬁnite element can then be deﬁned as the stored energy WV related to ∆z according to

2 2 WV ε0εr ∂ ∂ JA(ϕ) = Ae ϕ + ϕ . (2.20) ∆z ≈ 2  ∂x ! ∂y !    Finally, the energy of the electrostatic ﬁeld in all elements is obtained by summation of the functionals JA(ϕ), hence

J(ϕ) = JA(ϕ). (2.21) all elementsX According to Equation 2.19 the partial derivatives of the potential ϕ(x, y) need to be calculated. In order to do this, Equation 2.12 is transformed into the expressions

∂ ∂Nµ(x, y) φ˜(x, y) = ϕµ (2.22) ∂x = ∂x µ Xi,j,k ∂ ∂Nµ(x, y) φ˜(x, y) = ϕµ. (2.23) ∂y = ∂y µ Xi,j,k

Inserting Equations 2.22 and 2.23 into Equation 2.19 and considering the omission of the variables x and y due to the partial derivate yields

ε0εr 2 JA(ϕ) [(yj yk)ϕi +(yk yi)ϕj +(yi yj)ϕk] + (2.24) ≈ 4Ae − − − n 2 + [(xk xi)ϕi +(xi xk)ϕj +(xj xi)ϕk] . − − − o

To ﬁnd the minimum of the functional JA(ϕ) it is required to set the partial derivatives equal zero, hence CHAPTER 2. SIMULATION TECHNIQUES 12

∂ ! JA(ϕ) = 0 µ = i,j,k. (2.25) ∂ϕµ ∀ The resulting equations for the individual corners of the triangles can be arranged in an elemental matrix p according to

pii pij pik φi  pji pjj pjk   φj  = 0. (2.26) p p p φ  ki kj kk   k      The matrix p exists for every ﬁnite element. For the solution of the problem it is mandatory to build the matrix P for the entire structure. This is done by summation of the functionals of the individual ﬁnite elements. The matrix P is obtained by adding the individual contributions of all neighboring elements to a joint corner. This yields

P nm = pnm. (2.27) elementsX As mentioned previously, the corners of adjacent discretization elements must overlap. Otherwise the calculation of the matrix P is not possible. Before the solution for the potential ~ϕ is obtained, the boundaries of the structure need to be considered. The ﬁnal solution results in

−1 ~ϕ = P P boundary ~ϕboundary. (2.28)

A detailed description of boundary conditions and their consideration during the solution process would go beyond the scope of this work. More information on this topic is found in [31]. The Finite Element Method is a very flexible and all-purpose calculation method. Nearly arbitrary 3D structures can be discretized and analyzed using FEM, which is a significant advantage of this computation method. In addition, the properties of anomalous materials can be included. As an example, non-linear and magnetic materials can be taken into account, as well as ohmic losses and dielectric losses [35][36][37]. Besides, FEM has the potential to integrate numerous different boundary conditions, e.g. periodic boundary conditions [38]. Moreover, elements of miscellaneous dimensions within the model are possible [39]. For instance, wirebonds can be represented as a one-dimensional line, whereas ground planes are characterized by a two-dimensional area. This results in a considerable saving of calculation time. As a disadvantage, FEM requires a formidable amount of calculation time. On average, the simulation time for the solution of a problem increases quadratically with the number of elements. For comparison, the Finite Integration Technique (see next chapter) features a linear growth of calculation time with number of CHAPTER 2. SIMULATION TECHNIQUES 13 elements. As a consequence, very large models containing many very small structures are likely to reach the limits of the Finite Element Method, since computing resources may not be sufficient to solve a given problem. Another issue are heavily deviating electromagnetic field gradients. Linear form functions are not capable to accurately describe these diverging gradients. To overcome this problem, a finer discretization and quadratic form functions can be used in the affected region. However, this further increases calculation time. Another solution is the use of form functions which can emulate singularities of the electromagnetic field [40]. Furthermore, elements utilizing directly the electromagnetic field values instead of the potential [41] can be employed to handle the problem of heavily diverging field gradients. Solving electromagnetic fields according to [41] further avoids numerically problematic calculation steps. It should be noted that most FEM techniques used for electromagnetic field simulation yield results only at one frequency. Thus, for problems where a broadband frequency characterization is desired, many frequency points need to be simulated. This dramatically increases calculation times for the solution of the problem. To overcome this issue, interpolation techniques have been developed [32]. This interpolation methods calculates the electromagnetic field at two frequency points. After this step, the solution between these two frequency points is interpolated and an error function is computed. If the error is above a predefined limit, additional frequency points are inserted and the electromagnetic field equations are solved again. This loop is repeated until the error value is within the maximum allowed limit.

2.3 Finite Integration Technique

The Finite Integration Technique (FIT) is another common method to calculate the electromagnetic ﬁeld within a 3D structure. It is utilized by CST Microwave Studio, a well known 3D full-wave solver. Similar to FEM, FIT is a well developed and established computation method. Basis for the technique are the Maxwell’s equations in their integral form which are derived from the diﬀerential form. The Maxwell’s equations in integral form are

1 Q E~ d~a = ρdV = (2.29) ZA · ε0 ZV ε0 E~ d~a = 0 (2.30) ZA · ∂ E~ d~s = B~ d~a (2.31) IC · −∂t ZA · CHAPTER 2. SIMULATION TECHNIQUES 14

~  ∂E  B~ d~s = µ0 ~j + ε0 d~a (2.32) IC · ZA  ∂t  ·    :=I~   s   | {z } where the following additional symbols are used:

V : The considered volume • Q: Electric charge in volume V • C: Curve in space • A: Surface area of volume V and area whose boundary is curve C, respec- • tively.

A detailed description of the Maxwell’s equations in integral form and additional illustrations are found in [42]. The Finite Integration Technique employs cuboids as discretization elements. Hence, the entire space is discretized into NV cubical volumes Vi. It is mandatory for the wall areas Aj of two adjacent cubes to completely overlap. Each volume can be ﬁlled by only one material. After discretization, Lk borderlines of adjacent volumes as well as Pk intersection points are introduced. This deﬁnes a grid G. Fig. 2.2 further illustrates this discretization process.

Lk Vi

Figure 2.2: Discretization in Finite Integration Technique

Next, a grid voltage ek along the borderlines Lk and a magnetic ﬂux bj through wall areas Aj are deﬁned as CHAPTER 2. SIMULATION TECHNIQUES 15

ek = E~ d~s (2.33) ZLk ·

bj = B~ d~a. (2.34) ZAj · Using Equations 2.33 and 2.34 transforms the third Maxwell’s equation in integral form 2.31 into

∂bj cjkek = . (2.35) − ∂t Xk The remaining Maxwell’s equations can be transformed in a similar way using the expressions

~ hk = ˜ H d~s (2.36) ZLk · ~ ~ dj = ˜ D dA (2.37) ZAj · ~ ~ ij = ˜ j dA (2.38) ZAj ·

qi = ρ ~s. (2.39) ZVi For Maxwell’s equations 2.29 and 2.32 the integration is not performed along the predefined grid G, but along a so-called dual grid G˜. The intersection points P˜l of the dual grid G˜ lie in the center of the volumes Vi. The parallel components of the electric field are assigned to the borderlines of grid G, whereas the normal components of the magnetic flux are assigned to the borderlines of the dual grid G˜. This is illustrated in Fig. 2.3. The resulting equations can be transformed into matrix form which allows a numerical calculation of the problem. FIT requires approximations for the relations between the fields E~ and D~ , as well as approximations for the relations between H~ and B~ , respectively. Table 2.1 gives an overview of the Maxwell’s equations and their discretized forms used in the Finite Integration Technique. The permeability µ, the permittivity ε and the conductivity σ (see Table 2.1 are approximated using

˜ ~ ~ ˜ ~ Ak D dA Ak εdA · := (Dε)k (2.40) R E~ d~s ≈ R L d~s Lk · k R ~ ~ R ~ Ak B dA Ak dA · 1 := (Dµ)k (2.41) R ˜ H~ d~s ≈ RL˜ d~s Lk · k µ R R CHAPTER 2. SIMULATION TECHNIQUES 16

G B

Figure 2.3: Grid G and dual grid G˜

˜ ~ ~ ˜ ~ Ak j dA Ak σdA · := (Dσ)k. (2.42) R E~ d~s ≈ R L d~s Lk · k R R

Table 2.1: Maxwell’s equations and their discretized equivalents

Maxwell’s equations Discretized form

D~ d~a = ρf dV S˜d~ = ~ρ A · V H B~ d~a R= 0 S~b = 0 A · ~ ~ E~ Hd~s = ∂B d~a C~e = ∂b C · − A ∂t · − ∂t H R ∂D~ ∂d~ H~ d~s = ~jf + d~a C˜~h = ~i + C · A ∂t · ∂t H ~ R ~ ~ D = εE d = Dε~e ~ ~ ~ ~ B = µH b = Dµh ~ ~j = σE ~i = Dσ~e

The Finite Integration Technique replaces the divergence and rotation operators of the Maxwell’s equations by the matrices S, S˜ and C, C˜ , respectively. Com- putation of the equations presented in Table 2.1 yields the solution of the given CHAPTER 2. SIMULATION TECHNIQUES 17 problem. The discretization into cuboids results in lower complexity and rather simple matrices if the grid is not too dense. Due to this, the algorithm of the Finite Integration Technique works very efficiently. However, for small structures within a larger volume a very dense mesh is necessary along the entire axes of the coordinate system. This can dramatically increase the number of elements and the computation time as a direct result. Although it is possible to completely integrate denser meshes into a relatively coarse mesh [43], this method may result in additional electrical reflections along the borders of the grid. These reflections falsify the results. As a major advantage, the Finite Integration Technique works in frequency domain as well as time domain. This is especially beneficial for broadband frequency characterization. Very few calculation cycles are necessary if calculations are performed in time domain [44].

2.4 Comparison

The simulation results presented in this work were calculated utilizing the Finite Element Method and the Finite Integration Technique, respectively. As a FEM tool, Ansoft HFSS [32] was employed, whereas CST Microwave Studio [33] was used for the FIT calculations. Below is a list of the main advantages and disadvantages of both techniques with respect to eﬃciency and computer performance, respectively.

Finite Element Method:

+ Tetrahedrons as discretization elements

+ Arbitrary structures can be calculated

+ Mutable mesh density within entire volume

- Requires high amount of Random Access Memory (RAM) due to extensive matrix calculations

- Broadband frequency characterization requires additional calculation cycles

Finite Integration Technique:

+ Moderate system requirements for common problems

+ Eﬃcient frequency characterization due to time domain calculations

- No tetrahedrons as discretization elements

- Arbitrary structures require extremely dense mesh due to discretization CHAPTER 2. SIMULATION TECHNIQUES 18

2.5 Validation

One important aspect when using simulation tools is the veriﬁcation of the provided simulation results and their accuracy by measurement of the simulated components. For this, various package structures were manufactured and measured. Two diﬀerent structures are presented in this chapter. These structures were analyzed using Ansoft HFSS. First, two via interconnects were considered. The vias are connected by a microstrip line. Fig. 2.4(a) shows a photograph of the substrate containing the interconnects and transmission lines. The 3D model is depicted in Fig 2.4(b).

(a) (b)

Figure 2.4: Photograph and model of via interconnects

The scattering parameters obtained from measurement and simulation are presented in Fig. 2.5 and Fig. 2.6. Fig. 2.5 shows the simulated and measured reflection coefficient S11. The transmission coefficient S21 is depicted in Fig. 2.6. A very good agreement between simulation and measurement results is achieved. The resonant frequency of about 5 GHz is perfectly captured by the simulation software. As another example, wirebonds of different lengths were regarded. A photograph of one exemplary wirebond is presented in Fig. 2.7(a). The model is shown in Fig. 2.7(b). The wirebond is made from gold and has a diameter of 25 µm. The length of the wirebond is approximately 1.2 mm. A comparison of simulation and measurement results is depicted in Fig. 2.8 and Fig. 2.9 which show the reflection coefficient S11 and transmission coefficient S21, respectively. Again a good agreement of simulation and measurement is given. Thus, actual 3D electromagnetic field simulation tools are capable to quickly provide results which describe the electrical behavior of the simulated structure accurately. Further simulation results presented in this work were validated using measurements, where applicable. CHAPTER 2. SIMULATION TECHNIQUES 19

Measurement

-10

Simulation

-20 [dB] -30 11 S

-40

-50

-60

0 2 4 6 8 10

Frequency [GHz]

Figure 2.5: Scattering parameter S11 of a via interconnect (Z0 = 50 Ω)

0,0

-0,5

-1,0 [dB] -1,5 21 S

-2,0

Measurement

-2,5

Simulation

-3,0

0 2 4 6 8 10

Frequency [GHz]

Figure 2.6: Scattering parameter S21 of via interconnect (Z0 = 50 Ω) CHAPTER 2. SIMULATION TECHNIQUES 20

(a) (b)

Figure 2.7: Photograph and model of wirebond

-5

-10

-15

-20 [dB] -25 11 S

-30

-35

Measurement

-40

Simulation

-45

-50

0 2 4 6 8 10

Frequency [GHz]

Figure 2.8: Scattering parameter S11 of wirebond (Z0 = 50 Ω)

2.6 Other Methods

Besides the presented FEM and FIT computation methods, many other numerical analysis techniques exist. Another commonly used method is the Method of Moments, which is an alternative mathematical technique to transform the Maxwell’s equations into matrices. Fundamentals of this technique are described in [45]. Other implementations of the Method of Moments can be found in [46], [47] and [48], respectively. The Boundary Element Method is an emerging analysis CHAPTER 2. SIMULATION TECHNIQUES 21

0,0

-0,5

-1,0

-1,5

-2,0 [dB]

-2,5 21 S

-3,0

-3,5

-4,0

Measurement

Simulation

-4,5

-5,0

0 2 4 6 8 10

Frequency [GHz]

Figure 2.9: Scattering parameter S21 of wirebond (Z0 = 50 Ω)

technique. In contrast to the Finite Element Method or Finite Integration Tech- nique, only surfaces are discretized instead of the entire volume. This reduces calculation times to a great extend. Special boundary conditions are assumed at the edges of the surfaces. A detailed derivation of the Boundary Element Method is found in [34]. One of the eldest calculation techniques is the Finite Difference Method. Similar to FIT, the volume is discretized using cuboids. The Finite Dif- ference Method is simple and straightforward to implement, but tends to be not as efficient as FEM of FIT. Although FEM requires a higher computation effort per element, the use of tetrahedrons allow a higher flexibility. A dense mesh can easily be integrated into a coarse mesh to analyze small geometries within a large volume. This is not possible when the Finite Difference Method is employed, hence the number of elements quickly increase for a complex structure. More information and detailed derivations are found in [34], [29] and [46]. Intented for the analysis of stacked materials is the Spectral Domain Method. It is further referred to as a 2.5D method since only planar structures between two isolating dielectric media can be calculated. The only allowed exception are perpendicular interconnect structures. The Spectral Domain Method is very efficient and gives accurate results for planar structures [30]. An in-depth description of this method is given in [29], [49], [50] and [51], respectively. Chapter 3

Package Fundamentals

An overview of actual packages and package basics is given in this chapter. Pack- ages can be classiﬁed into several types. The most common types and their typical characteristics and properties are described below. Next, components found in actual packages are explained. The electrical characteristics of these package elements are described using scattering parameters (see Chapter 4.4.1) as well as lumped elements of equivalent circuit models. Finally, the leadless package concept TSLP is explained in detail. Its electrical performance is pointed out, especially in comparison to other actual packages.

3.1 Package Types

This chapter focuses on the basic description of common actual packages. Spe- ciﬁc features and characteristics are highlighted, as well as their advantages and disadvantages, respectively.

3.1.1 Leadframe Packages

Leadframe packages are one of the earliest package types. As second level interconnects, the printed circuit board/package interface, long leads are used. The chip mounted inside the package is directly connected to these leads utilizing wirebond interconnect technology. A photograph of a typical leadframe package is shown in Fig. 3.1(a). In Fig. 3.1(b) a photograph of an open leadframe package showing the wirebond ﬁrst level interconnects, the chip/package interface, is presented. Leadframe packages are increasingly replaced by laminate packages and leadless packages. This is due to the performance and pin count limitations of leadframe packages. The utilized leads induce a high parasitic inductance and additional power losses. In addition, the dimensions of leadframe packages are very large

22 CHAPTER 3. PACKAGE FUNDAMENTALS 23

(a) (b)

Figure 3.1: Typical leadframe package [1] compared to laminate packages and especially leadless packages. As a consequence, the leads of the package cannot be considered as lumped elements since the wavelengths of higher operating frequencies easily lie in the region of package dimensions. Therefore, leads need to be considered as distributed elements and additional high frequency eﬀects such as remarkable impedance mismatch occur. Thus, the package is not suited for high frequency applications. Furthermore, laminate package types (see next chapter), such as the BGA package, provide a much higher pin count which is mandatory for today’s complex applications. Electrical modeling methodologies of leadframe packages are found in [52] and [53].

3.1.2 Laminate Packages

Laminate packages employ some kind of assembled substrate in the package. A common example of this package type is the Ball Grid Array package (BGA). BGA packages are well suited for high pin count applications, mainly due to the assembled substrate and thus the very ﬂexible redistribution capabilities within the package. To date, the typical pin count of actual BGA packages reaches a few hundreds with ease as seen for instance in Fig. 3.2. Fig. 3.2 shows a photograph of an exemplary BGA package (top and bottom view). Solder balls are used to establish an electrical and mechanical connection to the printed circuit board where the package is used. These solder balls are typically made from tin and lead. However, the demand for green packages increased in the last years [4]. So-called green packages renounce the use of harmful and hazardous materials, such as lead in solder balls or halogens in the mold compound [54]. Common alternative materials to lead are gold and silver. A cross-section of this package type is given in Fig 3.3. The substrate inside the package is used for redistribution purposes. In addition, large power and CHAPTER 3. PACKAGE FUNDAMENTALS 24

Figure 3.2: Typical laminate package (BGA) [1]

First Level Interconnects

Mold Compound

Die

Substrate

Vias Redistribution Soldermask Second Level Interconnects

Figure 3.3: Cross-section of BGA package ground planes can be realized on the substrate. This is of importance for high pin count applications to commonly distribute supply voltages and current return paths to the die inside the package. Regarding high frequency performance, impedance matched microstrip transmission lines and coplanar waveguides, as well as stripline structures can be manufactured. However, dimensions of impedance matched structures are usually large. As a consequence, they are rarely realized. For example, the width of a 50 Ω microstrip line is approximately 300 µm if a CHAPTER 3. PACKAGE FUNDAMENTALS 25

substrate with a typical height of 200 µm and a dielectric constant εr of 4, a common value, is used. Typical dimensions for line width and line spacing of metalization traces on the substrate are 50 µm to 100 µm. Manufacturing and assembly costs increase with decreasing dimensions of the metalization structure, though. In Fig. 3.3 a substrate with two metalization layers is shown. More layers can be implemented, however, costs of packages dramatically increase with additional substrate layers. In general, laminate packages are cost-intensive package types, especially compared to other plastic package solutions, e.g. leadless packages and leadframe packages. In a BGA package, the substrate alone takes up about 70 percent of all assembly costs. Hence, it is desired to keep the amount of layers as low as possible, since package development and assembly is mainly cost-driven.

Figure 3.4: Typical BGA substrate layout

To connect different substrate metalization layers, vias are used. Vias are drills in the substrate with a thin copper wall. The drill diameter is typically 100 µm. The via holes are usually filled with air or solder resist, if a solder resist is utilized in the package. For more detailed information about via interconnect structures, CHAPTER 3. PACKAGE FUNDAMENTALS 26 see Chapter 3.2.3. A typical substrate layout design of a BGA package is shown in Fig. 3.4. Fig. 3.4 additionally illustrates the very high flexibility of laminate package design, particularly its redistribution and power/ground net capabilities. Without proper design and modification of the substrate layout, BGA packages are not suited for high frequencies. Conductors on the substrate layers show a strong inductive behavior. This is due to a missing ground plane, which is often omitted due to cost and space reasons. An analysis of individual package elements is given later in this chapter. Other important features of laminate-type packages include the possibility to integrate passive components like inductors, capacitors or resistors on the substrate. This is a major advantage for communication applications and a significant contribution to the ongoing System-in-Package (SiP) [55][56] trend. External components like filters or matching networks can be realized on the substrate of the package. Moreover, more than one chip die can be integrated into one single package. The die can be mounted and connected using either wirebonds or flip chip bumps as first level interconnect technology. More information about first level interconnect technologies is given in Chapter 3.2.1 found later in this chapter.

3.1.3 Leadless Packages

Leadless packages are excellent candidates for high frequency applications [18]. They are small and signal pathways are very short. Typical leadless packages are the VQFN (Very thin Quad Flat Non-leaded), LGA (Land Grid Array) and TSLP (Thin Small Leadless Package - see Chapter 3.4). A photograph of a VQFN is shown in Fig. 3.5 as an example.

Figure 3.5: Typical leadless package (VQFN) - top view and footprint[1] CHAPTER 3. PACKAGE FUNDAMENTALS 27

In contrast to solder balls used for BGA packages, leadless packages use very small and thin contact areas as second level interconnects. These contact pads are directly integrated into the package, hence the name leadless package. The bottom side of the package showing the pad configuration, the contact pad locations and contact pad sizes represents the so-called footprint of package. The chip is directly connected to the contact pads using wirebonds or flip chip bumps. A substrate is not assembled in leadless packages. Realizing redistribution capabilities in a leadless package is possible, but requires formidable additional effort. Package costs dramatically increase, since several supplementary manufacturing processes are mandatory for additional metalization layers. For all further explanations, no redistribution capability is assumed. A cross-section of a leadless package is depicted in Fig. 3.6.

First Level Interconnects

Mold Compound

Die

Second Level Interconnects Plating

Figure 3.6: Cross-section of a leadless package (TSLP)

A major advantage of leadless packages is the very good high frequency performance, which allows applications in the GHz range. Signal pathways are very short and mostly determined by the ﬁrst level interconnects. An additional advantage are the low manufacturing costs of leadless packages. As a disadvantage, leadless packages to-date are only suited for low and medium pin count applications. This is primarily due to the lack of some kind of carrier for redistribution purposes. The average pin count of leadless packages to-date is about 40. The maximum number of contact pads for leadless packages in mass-volume production is 80.

3.1.4 Chip Scale Packages

In the last few years, so-called Chip Scale Packages (CSP) [9][10] and Waver Level Packages (WLP) [57][58] have emerged. The dimensions of CSPs and WLPs are comparable to the assembled chip itself. Per deﬁnition [9], sizes of CSPs are only CHAPTER 3. PACKAGE FUNDAMENTALS 28 up to 20 percent larger compared to the die itself. The assembly of these package types start directly at the waver level. For example, solder balls can directly be applied to the pads of the integrated circuit on the wafer. The wafer is sawed after the ball apply process to obtain the individual CSPs. Fig. 3.7 shows typical Chip Scale Packages.

Figure 3.7: Typical Chip Scale Packages [1]

Thin ﬁlm technology can be used on the wafer level to add dielectric layers as well as metalization layers on top of the integrated circuit. This allows the realization of signal redistribution layers similar to laminate packages. Impedance matched transmission lines for high frequency applications can be realized. The advantages of this technology are very short signal traces and very small package dimensions. However, the main drawbacks to-date are costs and manufacturing tolerances. Costs dramatically increase with increasing number of layers as well as layer thickness. Fig. 3.8 further illustrates this technology. Hence, thin layers are used to reduce manufacturing costs. Typical values for the thickness of dielectric layers are 5 µm to 10 µm. For these values, manufacturing tolerances are within 30 percent. This rather large value should be taken into account during package layout design, especially when impedance matched transmission lines are used. The characteristic impedance of microstrip lines varies up to 40 percent due to the tolerances. Thus, the use of coplanar waveguides is advantageous since only one metalization layer is used. Wafer level packages have a great potential for future high performance applications. CHAPTER 3. PACKAGE FUNDAMENTALS 29

Die Die

MS lines Dielectric

Figure 3.8: Thin ﬁlm technology used in CSPs

3.2 Package Elements

Various components found in actual package technologies are discussed in this chapter. The performance of these package elements was analyzed using 3D electromagnetic ﬁeld simulations. Further, test structures were assembled and measured to validate the simulation results where applicable. In addition, models of package elements are presented in this chapter. These models describe the electrical performance of the package elements using lumped circuit elements. Very good agreement with electromagnetic ﬁeld simulation results is achieved.

3.2.1 First Level Interconnects

First level interconnects establish a direct connection from the chip assembled inside the package to the chip carrier, for instance the substrate inside laminate packages or the contact pads of a leadless package. Most common interconnect types are wirebonds and ﬂip chip bumps.

Wirebond Interconnects

Wirebonds are very thin wires with a typical diameter of 15 µm to 25 µm. This small dimensions allow high interconnect density and enable high pin count applications. Nevertheless, wirebonds with a diameter up to 1 mm can be used for certain applications. Especially high power applications like power transistors require thick wirebonds to allow great current ﬂows and to ensure high power transmission capabilities. Gold or aluminum as materials are mostly used for wirebonds. Fig. 3.9 shows a power transistor using wirebond technology. Three parallel aluminum wirebonds with a diameter of approximately 500 µm are utilized. This ensures the capability to deliver high power and high currents. CHAPTER 3. PACKAGE FUNDAMENTALS 30

Figure 3.9: Photograph of high power transistor

Using a smaller wirebond diameter results in a higher wirebond density. This is especially important since more and more functions are integrated into one single chip which consequently results in an increased amount of chip pads of the integrated circuit. Up to a few hundred chip pads can be connected to the package using wirebond technology. Fig. 3.10 shows two stacked dies inside a BGA package which are connected using wirebonds with a diameter of about 25 µm. However, electromagnetic coupling between individual wirebond dramatically increases with higher bonding density.

Figure 3.10: High density wirebonding CHAPTER 3. PACKAGE FUNDAMENTALS 31

Thus, wirebond technology is very flexible. Further, wirebonding is well developed, reliable and cheap since wirebond technology is in use for several decades by now. From an electrical point of view, wirebonds act like inductors since the diameter of the wirebonds can be neglected compared to the length of wirebonds. As a coarse approximation and common rule of thumb, the parasitic inductance L of wirebonds is 1 nH per 1 mm wirelength. A detailed derivation of inductance formulas for wirebond interconnects is found in [59]. Wirebond technology is used in a wide range of packages. For leadframe packages, wirebonding is the interconnect technology of choice. Further, it is mostly used in laminate and leadless packages due to cost reasons. Especially for leadless packages the employment of flip chip technology is a difficult task in many cases. For printed circuit board assembly purposes, a minimum pitch of the contact pads is required. This minimum pitch is typically about 500 µm. If flip chip interconnects are used, a large chip pad pitch is also mandatory to maintain the contact pad pitch of the package itself. As a consequence, a larger die area is necessary which significantly raises wafer costs and reduces the chip pad density.

Tolerances of Wirebond Interconnects

Manufacturing tolerances represent an important issue in package assembly and particularly the wirebonding process. The parasitic behavior of wirebond interconnects mainly depend on their overall length. Thus, to minimize parasitic elements, the length of the wirebond should be minimized. Manufacturing tolerances during the package assembly process alters the length of the wirebond, though. For example, the wirebond loop height is subject to a certain amount of length variation. A summary of typical manufacturing tolerances which inﬂuence the total wirebond length to a certain extend is given in Table 3.1.

Table 3.1: Manufacturing tolerances (exemplary values)

Property Tolerance / Accuracy

Wirebond Loop Height 25 µm ± Wirebond Placement 25 µm ± Solder Resist Height 5 µm ± Die Tape Height 2 µm ± Die Attach Glue Height 2 µm ± Die Placement 25 µm ± In the course of this thesis the impact of manufacturing tolerances on the electrical performance of the interconnect structure was analyzed. The worst and best cases CHAPTER 3. PACKAGE FUNDAMENTALS 32 were assumed. For worst case analysis, the wirebond length is maximum and minimum for best case, respectively. In addition, two diﬀerent nominal wirebond lengths representing short and longer wirebonds were chosen. The nominal length of the short wirebond is about 550 µm, the nominal length of the longer one is about 900 µm, respectively. The maximum, nominal and minimum wirebond lengths due to manufacturing tolerances are summarized in Table 3.2.1.

Table 3.2: Minimum, nominal and maximum projected wirebond lengths

Minimum length Nominal length Maximum length

Short wirebond 500 µm 550 µm 600 µm Long wirebond 850 µm 900 µm 950 µm

The results for the short wirebond with a nominal length of 550 µm are depicted in Fig. 3.11 and Fig. 3.12, respectively. Fig. 3.11 shows the magnitude of the scattering parameter S11. The reflection coefficient S11 can vary by about 2 dB due to manufacturing tolerances, if worst (maximum length) and best (minimum length) case are compared. The transmission coefficient S21 is presented in Fig. 3.12. At a frequency of 10 GHz the difference in transmission performance of the interconnect is about 0.2 dB.

-5

-10

-15

-20 [dB] -25 11 S

-30

-35 Max.

Nom.

-40

Min.

-45

0 2 4 6 8 10

Frequency [GHz]

Figure 3.11: Inﬂuence of tolerances on S11 of a short wirebond (Z0 = 50 Ω) CHAPTER 3. PACKAGE FUNDAMENTALS 33

0,0

-0,2

-0,4 [dB] 21 S

-0,6

Max.

-0,8

Nom.

Min.

-1,0

0 2 4 6 8 10

Frequency [GHz]

Figure 3.12: Inﬂuence of tolerances on S21 of a short wirebond (Z0 = 50 Ω)

-5

-10

-15 [dB] -20 11 S

-25

-30

Max.

Nom.

-35

Min.

-40

0 2 4 6 8 10

Frequency [GHz]

Figure 3.13: Inﬂuence of tolerances on S11 of a long wirebond (Z0 = 50 Ω) CHAPTER 3. PACKAGE FUNDAMENTALS 34

0,0

-0,5 [dB] -1,0 21 S

Max.

-1,5

Nom.

Min.

-2,0

0 2 4 6 8 10

Frequency [GHz]

Figure 3.14: Inﬂuence of tolerances on S21 of a long wirebond (Z0 = 50 Ω)

Fig. 3.13 and Fig. 3.14 demonstrate the impact of tolerances on the performance of wirebonds with a nominal length of 900 µm. Due to the increased overall length of the interconnect the influence is negligible. In Fig. 3.13 the scattering parameter S11 is shown. The difference is less than 1 dB for frequencies above 1 GHz. In Fig. 3.14 the scattering parameter S21 is depicted. The difference in transmission is approximately 0.1 dB.

Electrical Modeling of Wirebond Interconnects

During product development, the package design may chance a number of times before a decision on the final design is made. In addition, more than one package design may be considered. Therefore, it is desired to quickly analyze a given package design in order to evaluate its influence on the assembled integrated circuit or to optimize a package design. Performing complex 3D electromagnetic field simulations of different package designs requires a rather large amount of time, especially if a number of design variations are to be analyzed or optimized. Moreover, most software package yield scattering parameters as a result, which may be difficult to integrate in circuit simulators due to convergence reasons. A proposed solution is the use of electrical compact models. These models describe the electrical performance of wirebond interconnects using lumped elements. The models are based on electromagnetic field simulations which were performed once. CHAPTER 3. PACKAGE FUNDAMENTALS 35

Agilent Advanced Design System 2003 [60] was used to fit the equivalent circuit model to the 3D field simulation results afterwards. Wirebonds made from gold were assumed since gold is mostly used as material for wirebonds. The diameter of the modeled wirebonds is 25 µm, the length is about 1 mm. Since a minimum number of lumped elements is used to describe the electrical performance of the wirebond, the model is not accurate for very high frequencies. Nonetheless, excellent agreement is achieved for frequencies up to 15 GHz. Skin and proximity effects occur at higher frequencies. The time-varying alter- nating currents flowing through the conducting metal traces produce an electric field on their own within the conductor. This electric field counteracts the overall magnetic field of the device, as illustrated in Fig. 3.15.

Counteracting field

Figure 3.15: Magnetic ﬁeld inside a metal trace

Due to this induced field within the volume of the conductor the current flowing through the conductor is forced to the edge of the metal traces and accumulates near the surface of the conducting element. Hence the overall magnetic field of the structure can penetrate the metal traces only to a certain depth. These effects are known as skin effect and current crowding. The skin depth describes the depth of penetration

2ρ δ = . (3.1) sµω where ρ is the resistivity [Ωm] of the material, µ [Vs/Am] is the permittivity and ω [Hz] the circle frequency. The circle frequency ω is deﬁned as

ω = 2πf. (3.2) CHAPTER 3. PACKAGE FUNDAMENTALS 36

Thus, the resistance changes with frequency since the current distribution and eﬀective conducting area withing the structure changes according to Equation 3.1. As a direct consequence, the resistance is only valid for a narrow frequency band. The resistance values found in the equivalent circuit were extracted at a frequency of 5 GHz.

L=0.4652 nH L=0.4652 nH R=190.42 mOhm R=190.42 mOhm Port 3 Port 4 CGND=26.207 fF CCOUP=61.09 fF

M=0.319 nH M=0.319 nH

R=190.42 mOhm R=190.42 mOhm

Port 1 L=0.4652 nH L=0.4652 nH Port 2 CGND=26.207 fF

Figure 3.16: Equivalent circuit model of two coupled wirebonds with a length of 1 mm

The equivalent circuit of two coupled wirebond with a projected length of 1 mm is illustrated in Fig. 3.16. The pitch on the chip side is 80 µm and 130 µm on substrate side. These values represent typical values for wirebond pitches. The loop height is about 100 µm, thus the overall wirebond length is approximately 1.2 mm. The main parasitic elements of the wirebond are the resistance R and inductance L. The capacitances CGND are defined by the bonding pad on the substrate and the pad on the chip, respectively. In Fig. 3.17 a comparison of the compact model and field simulation results is given. Fig. 3.17(a) and Fig. 3.17(b) show the real and imaginary part of the scattering parameter S11. The real and imaginary part of the scattering parameter S21 are displayed in Fig. 3.17(c) and Fig. 3.17(d), respectively. A comparison of the coupling coefficient is given in Fig. 3.18. For the sake of simplicity, only the direct coupling from input to the output of the adjacent wirebond is presented here. The real part of the scattering parameter S41 is shown in Fig. 3.18(a), Fig. 3.18(b) displays the imaginary part of the scattering parameter S41, respectively.

Flip Chip Interconnects

Besides wirebond technology, another major interconnect technology are flip chip first level interconnects. Flip chip interconnects are small solder bumps which are directly applied to the pads of the integrated circuits. A photograph of flip chip bumps on a test circuit is shown in Fig. 3.19. Typical diameters of flip chip CHAPTER 3. PACKAGE FUNDAMENTALS 37

Real (S ) Imag (S )

11 11

1,0 1,0

0,8 0,8

0,6 0,6

0,4 0,4

0,2 0,2

0,0 0,0

-0,2 -0,2

-0,4 -0,4

-0,6 -0,6

Model Model

-0,8 -0,8

EM Simulation EM Simulation

-1,0 -1,0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (a) (b)

Real (S ) Imag (S )

21 21

1,0 1,0

0,8 0,8

0,6 0,6

0,4 0,4

0,2 0,2

0,0 0,0

-0,2 -0,2

-0,4 -0,4

-0,6 -0,6

Model Model

-0,8 -0,8

EM Simulation EM Simulation

-1,0 -1,0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (c) (d)

Figure 3.17: Comparison model and EM results of two coupled wirebonds with a length of 1 mm (Z0 = 50 Ω)

S [dB]

41 S [deg]

-10

200

-15

Model

150

-20

EM Sim ulation

-25

100

-30

-35

-40

-45

-50

-55 -100

Model

-60

EM Sim ulation -150

-65

-70 -200

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (a) (b)

Figure 3.18: Comparison model and EM results of two coupled wirebonds with a length of 1 mm - coupling coefficient (Z0 = 50 Ω) CHAPTER 3. PACKAGE FUNDAMENTALS 38 bumps range from 30 µm to 80 µm. Common materials for bumps are AuSn [61] or SnAg. After the ball apply process, the chip is simply placed upside down on the carrier, for instance a package leadframe or package substrate, if the die is assembled in a laminate package. During a reflow process, the bumps are soldered on the carrier, thus forming the interconnect structure between the chip die and the package carrier. One very important advantage of flip chip technology is the electrical performance of the first level interconnect. The dimensions of the bumps are very small, thus signal pathways are very short. As a direct consequence, parasitic elements induced by the interconnect structure are very small, especially in comparison to wirebond technology. Hence, flip chip technology is the interconnect technology of choice for the realization of mm-wave applications, where low input reflections and very low insertion losses play a major role. Bare die applications using flip chip interconnects are presented in [62] and [63]. Flip chip technology can be used up to an operating frequency of 100 GHz [64].

35 µm

Figure 3.19: Photograph and cross section of ﬂip chip bumps on test wafer

Another major advantage of flip chip technology are the low space requirements on the package carrier. This especially applies to laminate packages. Since the chip is placed upside down on the carrier, the necessary bond pad pitches on the carrier are identical to the pitch of the chip pads. Moreover, the die itself does not consume any space on the carrier. As a result, package design and substrate layout is considerably more flexible if flip chip technology is employed. However, the reduced pitch may yield additional problems, if flip chip is used in leadless packages. For leadframe packages, the pitch of the contact pads of the package (package footprint, see Chapter 3.1.3) is also identical to the chip pads (also see CHAPTER 3. PACKAGE FUNDAMENTALS 39

Fig. 3.30). However, a minimum pitch of the contact pads is required for board assembly purposes. This minimum pitch lies in the region of a few hundred µm. In contrast, common pitches of chip pads range from 70 µm to 100 µm. Hence, in order to reach the minimum pitch, the pitch of the pads on the chip needs to be increased. This, however, leads to a larger die area and additional cost. This does not apply to laminate packages, though, since the mandatory small pad dimensions and pitches on the assembles substrate can be achieved. Another issue of flip chip technology is the additional mechanical stress when high pin count applications are assembled using flip chip technology. Due to small dimensions and close spaces mechanical stress can lead to cracks in the solder balls, the ball to chip interfaces or the ball to carrier interfaces, respectively. To reduce mechanical stress, an underfill material is used [65]. Besides the mentioned mechanical issues, the thermal performance may decrease. In many cases, the installation of an additional heat sink is difficult or even impossible when flip chip is used. Besides, the flipped die permits the use of thermal vias, which are often used in laminate packages to improve the heat transfer. The thermal conductivity properties of the flip chip interconnects themselves is rather poor, thus additional methods for heat transfer are necessary.

Electrical Modeling of Flip Chip Interconnects

Similar to the wirebond interconnects, equivalent compact models describing the electrical performance of flip chip interconnects were developed. These models can directly be implemented into circuit simulators for quick analysis and estimation of the parasitic elements induced by the package and interconnects during product development. The equivalent circuit of two coupled flip chip bumps is illustrated in Fig. 3.20. The parasitic inductance L as well as the parasitic resistance R show very small values which further demonstrate the superior electrical performance of the flip chip technology. The series resistance R was extracted at 5 GHz. A comparison of the compact model results and the 3D electromagnetic field simulation results is given in Fig. 3.21. Fig. 3.21(a) shows the real part of the scattering parameter S11, Fig. 3.21(b) the imaginary part of the scattering parameter S11, respectively. The real and imaginary parts of the scattering parameter S21 yielded by field simulation and the equivalent electrical model are displayed in Fig. 3.21(c) and Fig. 3.21(d). Very good agreement is achieved for frequencies up to 15 GHz. Again, one can see from the amplitude on the y-axis of the graphs depicted in Fig. 3.21 that the parasitic elements of the flip chip interconnects are very small. The coupling coefficient is shown in Fig. 3.22. Fig. 3.22(a) displays the real part of scattering parameter S41, the imaginary part of the scattering parameter S41 is shown in Fig. 3.22(b). Similar to other parasitic values, the coupling coefficient is very small. The pitch of the flip chip bumps is about 200 µm, the height and diameter of the bumps are approximately 80 µm. These small dimensions contribute to the low coupling effects to a major extend. CHAPTER 3. PACKAGE FUNDAMENTALS 40

R=26.4 mOhm L=93.8 pH Port 3 Port 4 M=89.8 pH

C1=2.76 fF

C2=3.37 fF CGND1=3.24 fF CGND2=9.16 fF

R=26.4 mOhm

Port 1 L=93.8 pH Port 2

CGND1=3.24 fF CGND2=9.16 fF

Figure 3.20: Equivalent circuit model of ﬂip chip bumps

Real (S ) Imag (S )

11 11

0,6 0,6

0,5 0,5

0,4 0,4

0,3 0,3

0,2 0,2

0,1 0,1

0,0 0,0

-0,1 -0,1

-0,2 -0,2

-0,3 -0,3

-0,4 -0,4

Model Model

-0,5 -0,5 EM Simulation EM Simulation

-0,6 -0,6

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (a) (b)

Imag (S ) Real (S )

0,0 1,00

-0,1 0,95

-0,2 0,90

-0,3 0,85

-0,4 0,80

-0,5 0,75

-0,6 0,70

-0,7 0,65

-0,8 0,60

Model Model

0,55 -0,9

EM Simulation EM Simulation

0,50 -1,0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (c) (d)

Figure 3.21: Comparison model and EM results of ﬂip chip bumps (Z0 = 50 Ω) CHAPTER 3. PACKAGE FUNDAMENTALS 41

S [dB]

41 S [deg]

-20

-90

-25

-100

-30

-110 -35

-40

-120

-45

-130

-50

-140

-55

-60 -150

-65

Model

-160

Model

-70 EM Sim ulation

EM Sim ulation

-170

-75

-80 -180

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (a) (b)

Figure 3.22: Comparison model and EM results of ﬂip chip bumps - coupling coeﬃcient (Z0 = 50 Ω)

3.2.2 Second Level Interconnects

Second level interconnects are the interface technology between the package and the printed circuit board (PCB) where the package is utilized. Common interfaces are package leads, solder balls and lands of leadless packages.

Leads

Leadframe packages utilize relatively large metal elements as second level interconnects. The length of package leads is typically a few millimeter. Due to the size, these leads cause additional reﬂections by impedance mismatch and considerable power losses at higher frequencies. Hence, leadframe packages are not suited for high frequency applications. Due to the high variety of package leads, size and shape are practically arbitrary, the development of equivalent electrical models was omitted. Exemplary electrical modeling of leads is given in [52].

Balls

Balls are found in laminate packages (see Chapter 3.1.2), e.g. the Ball Grid Ar- ray (BGA) package, as second level interconnect technology. The interconnect structure is formed by a solder ball. The solder balls are applied to the substrate mounted inside the package during the ﬁrst assembly step. These balls are mostly made from tin and lead. With the ongoing trend to green packaging [54], it is desired to replace lead in solder balls by materials conform to the green packaging guidelines, for instance gold or silver. The typical diameter of these balls used in today’s BGA packages is 300 µm. After reﬂow and board assembly, the typical ball height is about 200 µm. The ball pitch depends on the ball diameter. The CHAPTER 3. PACKAGE FUNDAMENTALS 42 ball pitch is typically 500 µm for solder balls with a diameter of 300 µm. Besides Ball Grid Array packages, balls are also utilized in some Chip Scale Packages [57] as well as Wafer Level Packages [58] as second level interconnect technology. As an illustrative example, Fig. 3.7 shows Wafer Level Packages using solder balls for board level assembly.

Electrical Modeling of BGA Balls

Similar to ﬁrst level interconnects, equivalent electrical models for solder balls as second level interconnects were developed in the course of this thesis. The compact model representing the electrical performance of the solder ball is presented in Fig. 3.23. The modeled solder balls have a diameter of 300 µm and a ball height of 200 µm. The main parasitic elements are the inductance L and resistance R. The series resistance R was extracted at 5 GHz and is strictly speaking only valid at this frequency due to the skin eﬀect. The resistance decreases at lower frequencies. The capacitances CGND1 and CGND1 originate from the bondpads on the printed circuit board and the BGA substrate where the solder balls are attached. Bondpads with a common diameter of 300 µm were assumed. The electrical model is further valid for solder balls used in Chip Scale Packages and Wafer Level Packages.

R=127 mOhm L=254 pH

Port 1 Port 2

CGND1=24.2 fF CGND2=49.5 fF

Figure 3.23: Equivalent circuit model of solder ball

In Fig. 3.24 a comparison of 3D electromagnetic ﬁeld results and results yielded by the compact model is presented. Fig. 3.24(a) and 3.24(b) show the real and imaginary part of the scattering parameter S11, respectively. The scattering parameter S21 is depicted in Fig. 3.24(c) and Fig. 3.24(d). Fig. 3.24(c) shows the real part of transmission coeﬃcient S21, the imaginary part is displayed in Fig. 3.24(d). Very good agreement is achieved up to 15 GHz.

Lands

The contact pads of leadless packages are further referred to as lands. Another representative example of a package type using lands as second level interconnect CHAPTER 3. PACKAGE FUNDAMENTALS 43

Imag (S )

Real (S ) 11

1,0

0,6

0,5 0,9

0,4

0,8

0,3

0,7

0,2

0,6

0,1

0,5 0,0

-0,1 0,4

-0,2

0,3

-0,3

0,2

-0,4

Model Model

0,1

-0,5 EM Simulation EM Simulation

0,0 -0,6

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (a) (b)

Real (S )

Imag (S ) 21

1,0

0,9

0,8

0,6

0,7

0,4

0,6 0,2

0,5 0,0

0,4 -0,2

0,3 -0,4

0,2 -0,6

Model Model

0,1 -0,8

EM Simulation EM Simulation

0,0 -1,0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (c) (d)

Figure 3.24: Comparison model and EM results of BGA balls (Z0 = 50 Ω) technology is the Land Grid Array (LGA) package. Lands are not limited to leadless packages, though. Some Wafer Level Packages and Chip Scale Packages additionally support the use of lands as second level interconnects as well. Contact pads of leadless packages are usually square or rectangular shaped. Further, there are no standard values for the dimensions of the lands. In general, rectangular shaped pads with dimensions ranging from 200 µm 200 µm up to 300 µm 450 µm are used. The TSLP further supports circular× shaped pads due to the× flexible leadframe concept. More details about TSLP assembly is given in Chapter 3.4. In general, arbitrary pad shapes can be realized, but require increased effort, especially during the photolithographic processes used for the leadframe. Due to cost reasons, this option is not used in practice. Values for the contact pad height typically range from 50 µm to 200 µm. Because of their reduced size, parasitic elements are very small. Since there exist several variations of lands, the derivation of equivalent electrical models was omitted. Each individual land geometry would require a different electrical model. Besides, the electrical performance further has a strong dependency on the used printed circuit board design. Due to the planar shape, lands may induce an additional capacitive effect if a board with CHAPTER 3. PACKAGE FUNDAMENTALS 44 low thicknesses and underlying ground plane is used. This capacitance is in the order of the parasitic elements of the land itself. On the other hand, this additional capacitive effect slightly improves transmission performance if wirebonds are used as first level interconnects. The capacitance counteracts the parasitic inductance of the wirebond to a certain extend.

3.2.3 Interconnect Structures

Interconnect structures, or so-called vias, are used to connect substrate layers on a package laminate or a printed circuit board. The substrate is drilled and the walls of the via are plated using the metalization material of the substrate. Copper as metalization is used in most cases. If solder resist is applied to the substrate, the drill holes are ﬁlled by the solder resist material, otherwise air. A wide range of drill diameters are utilized, depending on substrate technology and application. Typical dimensions for the drill diameter are 50 µm to 500 µm. For multilayer substrate stack-ups, three diﬀerent types of vias exist. These are buried vias, blind vias and through vias:

Buried vias: Buried vias are vias placed inside the substrate. They connect two or more inner substrate layers to each other and are mainly used for redistribution purposes.

Blind vias: In contrast to buried vias, blind vias are used to connect the outer top and bottom substrate layers to the inner layers of the stack-up. Blind vias are mostly used for redistribution.

Through via: Through vias, or through-hole-vias, are drilled through the entire substrate stack-up. They are often used to connect power and ground planes.

A detailed illustration of the via structures is presented in Fig. 3.25. In Fig. 3.25 a substrate stack-up of ﬁve layers is shown. Thus, the total number of metalization layers adds up to six layers.

Electrical Modeling of Via Interconnects

Vias are very common package elements. More and more integrated circuits are assembled in BGA packages. The high frequency applications operating in the GHz region increase steadily. Therefore, electrical characterization of via interconnects is of importance for today’s and future applications. Detailed analysis of via interconnects is found in [66], [67] and [68]. Equivalent electrical models for via interconnects found in BGA substrates were developed in the course of this work. Fig. 3.26 presents the equivalent circuit model for a via connecting two substrate layers. FR4 with a dielectric constant of 4.5 was chosen as substrate CHAPTER 3. PACKAGE FUNDAMENTALS 45

Buried via TOP L2

L3 L4

L5 BOTTOM Through via

Blind via

Figure 3.25: Via interconnect structures [2] material. The considered height of the substrate is 200 µm. A common drill diameter of 100 µm was assumed. Further, feeding metal traces with a length of 150 µm are included in the model. The feeding lines contribute about 150 pH to the total inductance LTOT = L1 + L2. Thus, the parasitic inductance LVIA of the via itself is approximately 290 pH. The resistances R1 and R2 were extracted at 5 GHz. The parasitic resistances of the feeding lines are roughly 25 mΩ. The parasitic capacitance of a via interconnect is about 38 fF.

R1=67.5 mOhm R2=67.5 mOhm

Port 1 L1 =287.6 pH L2=287.6 pH Port 2

C=38.25 fF

Figure 3.26: Equivalent circuit model of a two-layer via interconnect

The resulting scattering parameters of the model as well as the scattering parameter calculated by 3D electromagnetic field simulation are presented in Fig. 3.27. Fig. 3.27(a) compares the real part of reflection coefficient S11. The imaginary part of the scattering parameter S11 is shown in Fig. 3.27(b). Fig. 3.27(c) and Fig. 3.27(d) give a comparison of the real part and the imaginary part of the transmission coefficient S21, respectively. CHAPTER 3. PACKAGE FUNDAMENTALS 46

Real (S ) Imag (S )

11 11

1,0 1,0

0,8 0,8

0,6 0,6

0,4 0,4

0,2 0,2

0,0 0,0

-0,2 -0,2

-0,4 -0,4

-0,6 -0,6

Model Model

-0,8 -0,8

EM Simulation EM Simulation

-1,0 -1,0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (a) (b)

Real (S )

Imag (S ) 21

1,0

0,0

0,9

-0,1

0,8

-0,2

0,7

-0,3

0,6 -0,4

0,5 -0,5

0,4 -0,6

0,3 -0,7

0,2 -0,8

Model Model

0,1 -0,9

EM Simulation EM Simulation

0,0 -1,0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Frequency [GHz] Frequency [GHz] (c) (d)

Figure 3.27: Comparison model and EM results of a via interconnect (Z0 = 50 Ω)

Good agreement is achieved up to 15 GHz. The equivalent model presented in Fig. 3.26 can be directly integrated into circuit or system simulation and provides an eﬃcient possibility to model via structures. Several package designs and substrate layout variations can be analyzed within a short amount of time. This is of particular importance for BGA package designs where it is not feasible to perform several complex and time-consuming 3D electromagnetic ﬁeld simulations within a reasonable amount of time.

3.3 High Frequency Packaging Guidelines

This section is intended to give guidelines for high frequency package designs. In general, each package structure causes additional reﬂections and losses at higher frequencies. Thus, it is desired to minimize the number of necessary package structures along the high frequency signal pathways to obtain satisfactory electrical performance in the GHz region. Further, signal pathways should be as short as possible to avoid attenuation and additional losses due to impedance mismatch. CHAPTER 3. PACKAGE FUNDAMENTALS 47

These two issues are properly addressed by leadless packages. Since there are no additional redistribution measures in leadless packages, the use of leadless packages results in a minimum number of discontinuities. In addition, signal pathways are short in general. If wirebond technology is utilized, the length of signal pathways is mainly determined by the length of the wirebonds. The second level interconnect can be neglected due to the difference in size compared to wirebonds. Regarding first level interconnects, flip chip technology is the interconnect technology of choice for high frequency applications. Up to 100 GHz, excellent electrical performance is achieved [64][69]. Bare die applications using flip chip mounting schemes have been demonstrated in [62] and [63]. Laminate packages offer very flexible possibilities for package design which makes them suitable candidates for high frequency applications. These package types provide the potential for the realization of impedance matched structures within the package. Impedance matched transmission lines can be manufactured on the substrate inside laminate packages. Unfortunately, this option is disregarded in most cases, primarily because of space and cost reasons. For microstrip lines, an additional metal layer for realizing a common ground layer is necessary. This additional layer increases substrate cost dramatically. Coplanar waveguides, on the other hand, require additional space on the metalization layer, which drastically reduces rerouting capabilities of the package. Thus, to-date only single conducting traces on the substrate instead of transmission lines are manufactured in most cases. These traces show inductive characteristics since their length is generally by far longer compared to the height and width of the conductor. If impedance matched transmission lines are considered, coplanar waveguides are advantageous compared to microstrip lines. Coplanar waveguides require the use of only one metal layer on the substrate. Furthermore, the transition between two substrate layers is very short. For microstrip line transitions, a secondary ground layer and additional vias are necessary. Furthermore, the coplanar waveguide transition can be optimized by the use of staggered vias [70]. Staggered vias improve the electrical performance of the transition to a formidable extend. Below is a quick summary of guidelines for high frequency package design. High frequency performance can be improved by

minimizing the number of package structures, • reducing the length signal pathways, especially for laminate packages with- • out impedance matched transmission lines, using leadless packages where applicable, • considering impedance matched transmission lines in laminate packages • where applicable, utilizing ﬂip chip interconnect technology where applicable, • using coplanar waveguides and staggered via transitions. • CHAPTER 3. PACKAGE FUNDAMENTALS 48

3.4 The Leadless Package Concept TSLP

After dealing with single package structures, the leadless package concept TSLP is described in this chapter. TSLP represents a novel packaging concept which emphasizes especially on high frequency applications. Fully packaged applications operating in the high frequency and mm-wave region are presented in Chapter 5. These applications demonstrate the RF performance of the package. TSLP is the abbreviation for Thin Small Leadless Package which represent the main properties of the package concept. The package makes a contribution to actual industrial demands, e.g. reduced size, improved thermal performance and low cost (see also Fig. 1.1). The package is very thin. The total package height is solely 400 µm and has further potential for reduction. Moreover, lateral sizes are very small. Dimensions are typically in the millimeter region. For discrete components like diodes and transistors, package dimensions below 1 mm are realized. Fig. 3.28 compares the size of the package to that of a single sugar grain. The package is a leadless package, hence most explanations found in Chapter 3.1.3 apply to the TSLP.

Figure 3.28: Comparison of package size to sugar grain

3.4.1 Assembly Process

This section describes the assembly process of the package concept TSLP. Start- ing point is a copper leadframe. On this leadframe the contact pads are placed using photolithographic processes. These contact pads define the footprint of the package. Arbitrary footprint configurations can be realized which is a direct result of the utilized leadframe concept. The contact pads are usually made from CHAPTER 3. PACKAGE FUNDAMENTALS 49 nickel and have a thin gold layer on top. This gold layer is used for wirebonding purposes. A common value for the contact pad height is 50 µm. This height has further potential for reduction. Currently, a height of 20 µm for the contact pads is achievable. The typical lateral dimensions of the contact pads are 300 µm 300 µm. Contact pads sized down to 100 µm 100 µm can be realized, never-× × theless, board assembly and reliability compliance becomes more difficult as the dimensions of the contact area decrease. A photograph of one typical contact pad and its composition is shown in Fig. 3.29. The contact pad is encapsulated by a mold compound.

Mold compound

Galvanic Au

Galvanic Ni 50 µm

Electroless Ni

Electroless Au

Figure 3.29: TSLP contact pad

Next step in the assembly process of the TSLP is the die attach process. If wirebonds are employed, the chip is directly placed on one large contact pad. This pad is further referred to as the die pad. Typically, wirebonds made from gold with a diameter of 25 µm are used in the TSLP. After die attach, the individual chip pads are wirebonded to the remaining contact pads. For the flip chip version, small solder bumps are first applied to the chip. Details of this step are found in [61]. After the ball apply process, the chip die is placed up-side down on the pads on the copper leadframe. As an example, a photograph of flip chip mounted test circuits on the copper leadframe is presented in Fig. 3.30. The entire leadframe array is molded in the following step. A green packaging conformal halogen-free mold compound is used. After the molding process, the copper leadframe is completely etched away. The remaining nickel areas of the contact pads are then electroplated with a thin gold layer for PCB assembly purposes. Finally, the individual packages are singulated and electrically tested for proper operation. The assembly process is summarized in Fig. 3.31. CHAPTER 3. PACKAGE FUNDAMENTALS 50

Figure 3.30: TSLP leadframe with ﬂip chip samples

3.4.2 Package Properties

The leadless package concept TSLP shows properties which make a contribution to actual requirements on packages by the industry. The most important properties of the TSLP are presented in this chapter. In addition, diﬀerences and improvements to previously existing packaging technologies are highlighted. An experimental characterization of the package concept is given in the next chapter. For time- and frequency domain characterization, see Chapter 4.5.2 and Chap- ter 4.4.3, respectively. Mechanical, reliability and thermodynamical issues of the package concept are covered in [11], [71] and [61].

Assembly Technology

The package is based on a very ﬂexible leadframe concept (see Fig. 3.30). Nearly arbitrary footprint conﬁgurations can be realized, since photolithographic processes are used for leadframe manufacturing. For instance, it is possible to manufacture power and ground rings for supply and return current distribution, an important property which is not available to similar leadless packages (e.g. VQFN). In addition, the footprint is highly customizable. As an example, the leadframe pictured in Fig. 3.30 features circular shaped contact pads with a diameter of 150 µm. In general, square shaped pads with the lateral dimensions of 200 µm 200 µm are used. Fig. 3.32 demonstrates the capabilities of the employed leadframe× concept. CHAPTER 3. PACKAGE FUNDAMENTALS 51

Die Cu Leadframe NiAu Contact 2a. Flip-Chip Bonding

1. Die Bonding

2b. Wirebonding

4. Copper Removal 3. Molding and Final Plating

5. Singulation 6. Electrical Test

Figure 3.31: TSLP assembly process

Since the package is a leadless package, dimensions are very small. Standard package height is 400 µm and has further potential for reduction. Regarding pin count, up to 80 pins are supported to-date. Higher pin count leadframes with up to 216 contact pads are currently under investigation. Due to the leadframe concept, package assembly costs are low. Large numbers of packages can be produced in a short amount of time. Additionally, the package is a green package. Thus, no lead is used and the mold compound is free of halogens. CHAPTER 3. PACKAGE FUNDAMENTALS 52

Figure 3.32: Advanced TSLP leadframe

Power Applications

As previously mentioned, the TSLP provides excellent heat transfer characteristics. This enables power applications as well as employment of the package for applications operating in rather harsh environments. A typical example are so- called ”under-the-hood”electronics in automotive applications. Since the die is directly attached to the leadframe, the heat produced by the circuit can easily be transferred from its backside and through the Ni-contact pads to an external heatsink or a printed circuit board.

Electrical Performance

As first level interconnects, the package supports either wirebond technology or flip chip technology which is an important property of the package concept. Es- pecially when flip chip is used, excellent high frequency performance is achieved. Due to the small dimensions, signal pathways are very short. These short signal pathways are beneficial for the high frequency performance of the package. Typ- ical wirebond lengths range from 500 µm to 1 mm. In addition, the flat lands of the package can act as capacitors when the package is soldered on a board with a ground plane underneath. This capacitive effect slightly improves the performance when wirebond technology is utilized. Moreover, the parasitic inductance of the wirebond can easily be taken into account during circuit design since the inductance can be predicted accurately. In some applications, wirebond interconnects may act as an external matching network [72]. A comparison of wirebond and flip chip interconnects in TSLP is presented in Fig. 3.33 and Fig. 3.34. Con- tact pads with the dimensions 200 µm 200 µm and a height of 50 µm as well as gold wirebonds with a diameter of 25× µm were assumed. The length of the wirebonds is approximately 600 µm. Fig 3.33 displays the reflection coefficient S11 and Fig. 3.34 the transmission coefficient S21, respectively. The performance of the interconnect structures was analyzed up to 80 GHz using Ansoft HFSS. CHAPTER 3. PACKAGE FUNDAMENTALS 53

-10

-20

-30 [dB] 11

S -40

-50

-60 TSLP Flip Chip TSLP Wirebond -70 0 20 40 60 80 Frequency [GHz]

Figure 3.33: TSLP interconnect performance - S11 (Z0 = 50 Ω)

-2 [dB] 21 S

-4

TSLP Flip Chip TSLP Wirebond

-6 0 20 40 60 80 Frequency [GHz]

Figure 3.34: TSLP interconnect performance - S21 (Z0 = 50 Ω) CHAPTER 3. PACKAGE FUNDAMENTALS 54

The scattering parameter S11 of the flip chip interconnect is about 10 dB smaller compared to the scattering parameter S11 of the wirebond. The transmission coefficient S21 further demonstrates the superior performance of flip chip interconnect technology. However, depending on the application, the use of wirebond technology can still be an option. As already mentioned the parasitic inductance can easily be taken into account during circuit design. A detailed analysis of interconnect performance is presented in [73]. [73] further covers the influence of the pad dimensions and wirebond length on the electrical performance. Fig. 3.35 and Fig. 3.36 show the influence of the contact pad width on the scattering parameters S11 and S21 using wirebond interconnects. The contact pad width is varied from 100 µm to 300 µm. Due to the parasitic inductance of the wirebond interconnect, the influence of the pad is negligible.

The influence of the pad width on the scattering parameters S11 and S21 when flip chip technology is utilized is illustrated in Fig. 3.37 and Fig. 3.38, respectively. Since the parasitic elements of the flip chip bump are small, the pad dimensions have a noticeable impact on the electrical performance. Using smaller pad sizes improves the electrical performance of the transition to the chip. The obtained numerical analysis indicate an excellent high frequency performance of the package concept TSLP. This is demonstrated by several applications, which are presented in Chapter 5. Another major advantage are the System-in-Package capabilities of the TSLP. Several dies can be mounted on one leadframe and encapsulated in one single package. Additional passive elements can be integrated as well. TSLP is the first low-cost leadless plastic packages that offers these possibilities. The photograph presented in Fig. 3.32 shows an evaluation leadframe with various passive components, a supply voltage ring and several mounted dies. CHAPTER 3. PACKAGE FUNDAMENTALS 55

-10

-20 [dB] 11 S

-30

w = 100 µm -40

w = 200 µm

w = 300 µm

-50

0 20 40 60 80

Frequency [GHz]

Figure 3.35: Pad width inﬂuence on S11 using wirebond interconnects (Z0 = 50 Ω)

-2 [dB] 21 S

-4

w = 100 µm

w = 200 µm

w = 300 µm

-6

0 20 40 60 80

Frequency [GHz]

Figure 3.36: Pad width inﬂuence on S21 using wirebond interconnects (Z0 = 50 Ω) CHAPTER 3. PACKAGE FUNDAMENTALS 56

-10

-20

[dB] -30 11 S

-40

w = 300 µm

-50

w = 200 µm

w = 100 µm

-60

0 20 40 60 80

Frequency [GHz]

Figure 3.37: Pad width inﬂuence on S11 using ﬂip chip interconnects (Z0 = 50 Ω)

-1 [dB] 21 S

-2

w = 300 µm

w = 200 µm

w = 100 µm

-3

0 20 40 60 80

Frequency [GHz]

Figure 3.38: Pad width inﬂuence on S21 using ﬂip chip interconnects (Z0 = 50 Ω) Chapter 4

Characterization Techniques

In this chapter, package characterization techniques are discussed. This also includes high frequency characterization of involved package materials. For instance, the chip is usually encapsulated by a mold compound which has an impact on the transmission performance from the printed circuit board to the chip assembled in the package. The parameters of these materials need to be known at higher frequencies. Electrical package characterization is done in time domain as well as frequency domain. Especially time domain techniques prove to be very useful methods for package characterization. Time domain techniques can be used for numerous diﬀerent applications, which are covered in this chapter. Regarding frequency domain characterization, scattering parameters describing the performance of packages are obtained up to 65 GHz.

4.1 Material Characterization

From an electrical point of view, the electrical permittivity εr and the dielectric loss tangent tan δ of materials are of great importance. They describe the losses caused by the material itself. Further, the electromagnetic ﬁeld strength E~ and the magnetic ﬂux density B~ are linked to each other by the permittivity ε according to

D~ = ε0εrE~ (4.1)

−12 where ε0 is the electric ﬁeld constant (ε0 = 8.854 10 F/m) and εr the permittivity of the material. ·

Most material suppliers provide values for εr and tan δ only at very low frequencies, e.g. a few kHz. At higher frequencies, these values are practically unknown and must be determined. Package simulation, characterization and optimization

57 CHAPTER 4. CHARACTERIZATION TECHNIQUES 58 can only be performed accurately if the electrical properties of package materials are well known. Several methods of material characterization techniques are introduced here, as well as their advantages and disadvantages.

4.1.1 Capacitance Measurements

This technique is simply based on capacity measurement of the material under test. The capacitance C between two isolated electrodes depends on the material between the two electrodes and is expressed as

ε0ε A C = r . (4.2) l The surface area of the electrodes is denoted as A and the thickness of the dielectric material is l . Thus, if these values are known and the capacitance C is measured, the permittivity εr of the material can be directly calculated using Equation 4.2. This method is only valid for low frequencies. At higher frequencies stray capacitances at the edges of the electrodes increase and alter the results. Although is is possible to take stray capacitances into account [74], the method can only be employed up to about 2 GHz. With increasing frequencies the surface roughness of the material under test has a determining impact on measurement results. Assuming a surface roughness of less than 2 µm, capacitance measurements yield an accuracy of 8 percent when measuring the permittivity εr and 3 10−3 when measuring± the loss tangent tan δ, respectively. ± ·

4.1.2 Filled Transmission Guides

Other possibilities for material characterization include the use of filled transmission guides [75][76]. The transmission guides, e.g. coaxial cables or wave guides, are filled with the material under test. Afterwards, the transmission or reflection coefficient is measured and allows a calculation of the dielectric properties of the material.

Transmission Method

In this method the discoidal material sample is inserted into a shielded capacitor which is placed within a transmission guide. An illustration of this setup is presented in Fig. 4.1(a). Measurement of the transmission coeﬃcient S21 allows the calculation of the electric parameters of the material sample. The methods yields precise results. The accuracy is typically 1 percent for the permittivity. This accuracy is mainly determined by the tolerances± of the sample geometry. The dimensions of the inserted sample material need to be accurately known. Another drawback is the frequency limitation. The upper frequency limit is about 2 GHz. A detailed explanation of this transmission method is found in [77]. CHAPTER 4. CHARACTERIZATION TECHNIQUES 59

Material under test Material under test

(a) (b)

Figure 4.1: Filled transmission guides

Coaxial Discontinuity

The technique requires a discoidal material sample which is inserted between two coaxial guides. This is illustrated in Fig. 4.1(b). The permittivity is calculated after measurement of the transmission and reﬂection coeﬃcient S21 and S11. The advantages of this method are the easy usage and upper frequency limit of about 18 GHz. The tolerance of material dimensions should be 10 µm for accurate ± measurement results. Then, the value of the permittivity εr is determined with an accuracy of 5 percent. However, dielectric losses can only be measured for loss tangents of the± material tan δ 0.05. Extensive information on this approach is given in [78]. ≥

Open-Ended Reﬂection

Similar to transmission guide measurements, open-ended transmission guides are utilized for material characterization. The material is attached to the open-ended transmission guide, either an open-ended coaxial cable or a wave guide. The dielectric parameters are calculated from measurements of the reﬂection coeﬃcient S11. This method does not require special treatment of the material. The prereq- uisites are a polished surface and a minimum thickness of the material, depending on frequency. However, the surface roughness should be below 10 µm. In addition, no air gaps are allowed between the open-ended transmission guide and the material. Hence, the method is best suited for liquid materials. The upper frequency of this measurement technique is about 20 GHz. The tolerance of the measured permittivity εr is about 5 percent. Detailed information is given in [74] and [79]. An improved version± of this technique is presented in [80]. Additionally, [81] presents a full-wave analysis of the open-ended coaxial cable. CHAPTER 4. CHARACTERIZATION TECHNIQUES 60

Transmission Lines

Another possibility for determination of the dielectric properties are manufacturing of transmission lines, e.g. microstrip lines on the material [76]. This technique does not require a special sample preparation. Although the upper frequency of this method is about 80 GHz, the technique is not suited for accurate calculation of the dielectric parameters of materials, especially low loss materials (tan δ 10−3). The attenuation of transmission lines is signiﬁcantly higher compared to≤ coaxial transmission guides. Further, radiation occurs at higher frequencies. In addition, it is often diﬃcult to realize transmission lines on certain materials, for instance, mold compounds.

Resonator Techniques

Most accurate results are provided by resonance techniques. Numerous approaches exist, e.g. the use of cylindrical resonators [82], TE01p-resonators [83][84] or Fabry- Perot resonators [85][86][87]. The accuracy of the measured permittivity εr is typically 0.5 percent to 1 percent. The minimum measurable values of the loss tangent± range from tan± δ 10−5 to tan δ 10−4. As a disadvantage, res- ≥ ≥ onator techniques can only be employed at a ﬁxed frequency. The geometry of the resonator determines the resonant frequency of the structure, thus material parameters are extracted solely at the resonant frequency. Additional resonators are required for a broadband material characterization. Resonator techniques typically can be used up to 40 GHz. Fabry-Perot resonators allow material measurements even up to 300 GHz [86]. For the sake of simplicity, only the split-post resonator technique is outlined here. Based on [88], a dielectric measurement setup for packaging materials using split-post resonators at 3 GHz, 10 GHz and 20 GHz was installed in the course of this work.

4.1.3 Split Post Resonator Technique

Split-cylinder and similar split-post resonators allow great flexibility of the material under test. Originally the technique was intended for measurement of dielectric substrate materials [82]. Split-post resonators consist of two separate dielectric resonators with a narrow gap in-between. These resonators are placed in one-side open metallic cylinders where the open-sides face each other. The electromagnetic field is concentrated between the two cylinders. The substrate material is simply inserted into the gap to determine its dielectric properties. A performed evaluation showed that the split-post resonator technique can also be extended to measure mold compounds used for packaging. Fig. 4.2 shows the photograph of a 3 GHz split-post resonator along with some sample materials (substrate and mold compound). In contrast to similar resonator measurement techniques, it is not necessary that the material has a predefined CHAPTER 4. CHARACTERIZATION TECHNIQUES 61

Figure 4.2: Split-post resonator and sample materials shape. Typically, thin sheets as displayed in Fig. 4.2 of the material under test are suﬃcient. The outline can be of arbitrary shape and does not inﬂuence the measurement results. Further, the size is not important as long the material entirely covers the surface area of the resonating cylinders. For accurate results, only the thickness needs to be known accurately. The values of the permittivity εr and loss tangent tan δ are calculated by measuring the resonant frequency and quality factor of the resonator. First, resonant frequency and quality factor of the empty resonator are measured. Next, the material under test is inserted. This results in a resonant frequency shift as well as change of the quality factor. Now the permittivity εr and loss tangent tan δ can be determined. Fig. 4.3 shows an exemplary measurement result illustrating the shift in resonant frequency and quality factor change. Table 4.1 presents exemplary measurement results of various mold compounds. Several measurements of the same material were performed to determine the tolerances of the results. An extensive analysis of the accuracy of split-post resonators is presented in [89]. CHAPTER 4. CHARACTERIZATION TECHNIQUES 62

-10

-20 Sample in Resonator Empty Resonator

-30

-40

[dB] -50 21

S -60

-70

-80

-90 9,50 9,75 10,00 10,25 10,50 10,75 11,00 Frequency [GHz]

Figure 4.3: Resonance shift due to material in resonator (Z0 = 50 Ω)

Table 4.1: Measurement results of various mold compounds

Material Frequency εr tan δ CEL 9240HF 3.164 GHz 3.77 0.01 1.24E-02 2E-04 ± ± 9.796 GHz 3.79 0.02 1.02E-02 5E-04 ± ± 19.83 GHz 3.82 0.02 1.11E-02 4E-04 ± ± EME G770I 3.165 GHz 3.81 0.002 9.3E-03 1E-04 ± ± 9.809 GHz 3.82 0.02 7.97E-03 2E-05 ± ± 19.874 GHz 3.82 0.01 9.0E-02 6E-04 ± ± EME G760D-F 3.165 GHz 3.79 0.01 6.31E-03 7E-05 ± ± 9.810 GHz 3.81 0.01 6.4E-03 1E-04 ± ± 19.876 GHz 3.81 0.01 6.7E-03 2E-04 ± ± KMC 2520L 3.165 GHz 3.91 0.01 2.32E-02 8E-04 ± ± 9.805 GHz 3.87 0.02 1.83E-02 4E-04 ± ± 19.870 GHz 3.83 0.02 1.8E-02 2E-03 ± ± CHAPTER 4. CHARACTERIZATION TECHNIQUES 63

4.2 Calibration

Especially for high frequency measurements, proper knowledge of the employed measurement instruments and measurement methodology is mandatory for accurate measurement results. The entire measurement setup should be regarded. This includes the instrument itself, as well as attached cables, transitions and similar parts of the setup. Each components induces additional reﬂections and power loss which alters the measurement results if not taken into account ac- cordingly. One key component for proper measurements and accurate results is calibration of the measurement instrument. This is achieved by measuring several components whose performance and characteristics are well known. These are compared by the instrument to actual measurement results. From the deviation of the results, the measurement instrument is capable to calculate the impact of any peripheral components, e.g. cables, on the results [90]. Thus, a measurement reference plane is established. All parts of the measurement setup up to this reference plane are properly taken into consideration by the measurement instrument. Additional in-depth information about error sources, error correction and calibration procedures is given in [91].

Figure 4.4: Coaxial to microstrip technology in universal test ﬁxture

A vector network analyzer is usually outfitted with built-in coaxial test ports. However, semiconductor packages are usually soldered on substrates and printed circuit boards. As a result, a transition from coaxial to planar waveguide technol- CHAPTER 4. CHARACTERIZATION TECHNIQUES 64 ogy, e.g. microstrip or coplanar waveguide, is necessary to perform any measurements on packages. An example of such a transition is shown in Fig. 4.4. It shows a BGA package soldered on a Rogers RO3003 substrate [92], which is mounted in a test fixture [93]. The coaxial to microstrip transition causes additional reflections, losses and signal distortion, especially at higher frequencies. Hence, it is desired to subtract the transition from the measurement results to measure only the package characteristics. This is done by establishing a reference plane directly at the package connector through an appropriate calibration procedure. Thus, the transition is considered as a fixed part of the measurement setup and subtracted from subsequent measurements. The effects of a coaxial to microstrip transition are depicted in Fig. 4.5 using time domain measurements. Fig. 4.5 displays an output voltage step before and after a coaxial to microstrip transition. Clearly visible are the influence of the connector itself and its reflection, as well as the degradation of the voltage step due to the transition.

1,0

0,8

Reflected Transition 0,6

0,4 Voltage [V] Voltage Transition

0,2

Before Transition 0,0 After Transition

0 20 40 60 80 100 120 140 160 180 200 Time [ps]

Figure 4.5: Step before and after transition

Several calibration techniques have been developed and exist nowadays, for instance [94][95][96][97][98]. All have in common that a reference plane is established. Additional eﬀects caused by the measurement setup are subtracted from the measurement results up to this reference plane. Below some common calibration techniques and their applicability to package characterization are discussed. CHAPTER 4. CHARACTERIZATION TECHNIQUES 65

4.2.1 Short-Open-Load-Through (SOLT)

Short-Open-Load-Through (SOLT) is one of the most common calibration techniques. This is mainly due to its simplicity, easy handling and straightforward implementation. It is based on the measurement of a one-port short, open and 50 Ω load (i.e. match) standard, as well as a direct through connection of the measured ports. These standards are sufficient for a complete two-port calibration procedure. However, the realization of accurate match standards becomes more difficult as frequencies increase. Hence, the accuracy of the SOLT procedure strongly depends on the quality of the match standards. As mentioned, a coaxial to microstrip transition is mandatory for semiconductor package measurements. As a consequence, the SOLT standards must be realized in planar technology in order to establish the reference plane after the coaxial to microstrip transition. Precise and broadband 50 Ω resistances as match standards can only be manufactured up to a few GHz in planar technology. Hence, SOLT using planar standards is not well suited for high frequency measurements. For accurate and reproducible results, the calibration standards and evaluation boards should be manufactured using the same substrate technology, especially if a test fixture is used. Due to this, ceramic carriers and specially designed calibration substrates containing high quality thin film resistors as 50 Ω loads are not considered. High quality calibration substrates including highly accurate match standards are available on the market for wafer probe calibration techniques [99].

4.2.2 Through-Reﬂect-Line and Line-Reﬂect-Line

As an major advantage, the Through-Reflect-Line (TRL) calibration technique does not rely on a match standard. Instead, the reference plane is established using a direct through connection, another through connection with suitable electrical length (l = λ/4) and an arbitrary reflect standard, either an open or a short circuit, which can be non-ideal (ρ 1, 1). Further, TRL standards can be manufactured and used in coaxial as well≈ − as planar technology. This proves to be another significant advantage, since the same substrate material can be used for package evaluation boards and the TRL standards. One major drawback of the TRL calibration procedure is its frequency limitation. TRL is limited to a frequency span of 1:8 (start frequency to bandwidth ratio) [100], thus, if the start frequency is 1 GHz, only measurements up to 8 GHz can be performed using the standard TRL procedure. Many measurement instruments provide the possibility to extend the start to bandwidth ratio to 1:64 by measuring an additional line standard during the calibration procedure. Thus, one through and two line standards, instead of only one line calibration standard respectively, is used. Fur- thermore, very long lines are necessary for measurements at low frequencies, since the required line length of the calibration standard is determined by the wavelength. Time domain characterization using a VNA with equipped time domain option requires a large bandwidth and further very low measurable frequencies CHAPTER 4. CHARACTERIZATION TECHNIQUES 66

[101]. The bandwidth limitation and especially the low frequency limit of the TRL calibration procedure restrict the use of the built-in time domain option of the VNA. To handle the low frequency limitations, TRL calibration can be combined with an additional load standard. The calibration is performed in two frequency bands. For the low frequency band, the load standard is used. At a break frequency, the load standard is replaced by the line standard. This technique is also known as Through-Reflect-Match (TRM) [95]. A detailed mathematical derivation of the general TRL procedure is found in [102]. Fig. 4.6(a) and Fig. 4.6(b) show manufactured TRL calibration standards on Rogers RO3003 substrates. The Line-Reflect-Line (LRL) [103] method is a modified version of the TRL calibration technique. It uses an additional line standard as an alternative to the through connection. An integer multiple of 180◦ phase difference at the center frequency is required for the line lengths. This technique is advantageous when a direct through connection of the ports is not attainable. For instance, coaxial cables of the same connector type require an additional adapter which introduces a certain electrical length between the two ports, thus a through connection with zero electrical length is not achieved. In-depth information about Line-Reflect- Line calibration is given in [103]. Similar to TRM, the line standard in the LRL procedure can be replaced by a match standard for low frequencies. This method is referred to as Line-Reflect-Match (LRM) [104].

4.2.3 Time Domain De-embedding

This technique is based on a previously performed coaxial SOLT calibration. It uses additional time domain procedures to calculate the characteristics of the coaxial to microstrip transition afterward. The technique only uses one line standard of arbitrary but large enough length and two planar open standards with an arbitrary but large enough difference in line length. Fig. 4.6(c) shows a suitable calibration substrate used for the Time Domain De-embedding procedure as an example. From measurements of the open line standards and through line standards at both ports, the transition is fully characterized. The influence and characteristics of the transition is subtracted from the measurement results afterward. This is done by modifying the calibration coefficients stored in the VNA. Therefore, it is more a de-embedding technique than a calibration procedure. Fig. 4.7 shows the incident voltage step before and after applying the de-embedding procedure. As it can be seen from Fig 4.7. a very smooth voltage step with almost no distortion is obtained after the transition. By comparing Fig. 4.7 to Fig. 4.5, one can see that the coaxial to microstrip transition is properly taken into account by the method. The technique is applicable from very low to high frequencies, since it is based on a coaxial SOLT calibration. This initial SOLT calibration procedure determines the frequency span. Additional background information and an in-depth mathematical analysis of the Time Domain De-embedding method is presented in [105]. CHAPTER 4. CHARACTERIZATION TECHNIQUES 67

(a) (b) (c)

Figure 4.6: TRL and Time Domain De-embedding planar standards

4.2.4 Gating

Vector network analyzers with built-in time domain option often provide gating capabilities [101][106]. Gating is used to blank out certain part of the device. Hence, only the electrical characteristics of the device under test within the de- ﬁned gate are obtained, the parts outside the gate are neglected. This is achieved by combining time domain and frequency domain measurements via the Fourier- and inverse Fourier transform (see Chapter 4.5.1, Equations 4.24 and 4.25 found later in this chapter). Fig. 4.8 and Fig. 4.9 illustrate the gating technique. In Fig. 4.8 the measured time domain voltage step after the coaxial to microstrip transition is shown, but before application of the gate. The start and end points of the gate are indicated by the dashed lines, the colored area represents the gated area. All components which are located outside the gate are not regarded. Fig. 4.9 also demonstrates this by showing the voltage step after applying the gate. CHAPTER 4. CHARACTERIZATION TECHNIQUES 68

1,0

0,8

0,6

0,4 Voltage [V] Voltage

0,2 Before Transition After Transition 0,0

0 20 40 60 80 100 120 140 160 180 200 Time [ps]

Figure 4.7: Step before and after time domain de-embedding

Gate

1,0

0,8

0,6

0,4 Voltage [V] Voltage

0,2

0,0

0 20 40 60 80 100 120 140 160 180 200 Time [ps]

Figure 4.8: Step before gating CHAPTER 4. CHARACTERIZATION TECHNIQUES 69

Although the coaxial to microstrip transition is entirely blanked out, the voltage step is still aﬀected by distortion and degradation caused by the transition as indicated in Fig. 4.9.

1,0

0,8

Influence of Transition 0,6

0,4 Voltage [V] Voltage

0,2

0,0

0 20 40 60 80 100 120 140 160 180 200 Time [ps]

Figure 4.9: Step after gating

4.2.5 Application to Package Characterization

For package characterization, the reference plane established through calibration procedure should be directly at the package connector. Thus, only package characteristics themselves are measured. As previously mentioned, SOLT calibration is not an option due to the lack of accurate planar calibration standards manufactured on low-cost substrate materials. TRL as well as Time Domain De- embedding are well suited to take the entire measurement setup up to the package connector properly into account. Both techniques utilize standards in planar technology and are capable to establish the reference plane directly at the package. The measured reﬂection coeﬃcient S11 of a Ball Grid Array package using both TRL and Time Domain De-embedding is presented in Fig. 4.10. The package contains a testchip with an on-chip open standard. The measurement setup was entirely included in the calibration procedure, thus only the package was measured. Fig. 4.10 shows a very good agreement between TRL calibration and Time Domain De-embedding. Both calibration techniques yield accurate measurement results. However, TRL calibration has a lower frequency limit, as outlined previously. Hence, the package are measured only down to 5 GHz. CHAPTER 4. CHARACTERIZATION TECHNIQUES 70

-5

-10

-15 [dB]

-20 11 S

-25

-30

-35 Time Domain De-Embedding

TRL Microstrip

-40

5 10 15 20 25 30 35 40

Frequency [GHz]

Figure 4.10: Comparison microstrip TRL and Time Domain De-embedding method (Z0 = 50 Ω)

Further, gating capabilities and their applicability to package characterization were evaluated. Fig. 4.11 compares the reflection coefficient S11 of the BGA package using TRL and gating, respectively. The gated measurement results are based on a coaxial two-band TRL calibration using a load standard for the lower frequency band. For low frequencies, both techniques yield comparable results. At higher frequencies, the obtained results are different, though. The deviation in the results is due to the coaxial to microstrip transition, which is not entirely de-embedded from the measurement results. This is in particular observable at high frequencies. In conclusion, both TRL calibration and Time Domain De-embedding give reliable and accurate results for package characterization in the frequency domain. The utilization of both techniques require low effort and is straightforward. Time Domain De-embedding has been proved useful for low frequency measurements where very long lines as TRL calibration standards are mandatory. Besides, TRL makes the utilization of the built-in time domain option of VNAs difficult due to the bandwidth limitation of the calibration procedure. Using this time domain option is a precondition for time domain package characterization by means of a VNA (see Chapter 4.5 and Chapter 4.5.1). Gating techniques give accurate re- CHAPTER 4. CHARACTERIZATION TECHNIQUES 71

-5

-10

-15

[dB] -20 11 S

-25

-30

TRL Coaxial and Gating

-35

TRL Microstrip

-40

5 10 15 20 25 30 35 40

Frequency [GHz]

Figure 4.11: Comparison microstrip TRL and coaxial TRL with applied gate (Z0 = 50 Ω)

sults only at lower frequencies. Nevertheless, gating can be used for a quick and rough estimation of the device under test since the general characteristics of the measured device are captured.

4.3 Measurement Setup

In the following, the utilized measurement setup is introduced. All presented measurement results were obtained by a two-port Anritsu 37397C vector network analyzer [101]. The bandwidth of the instrument ranges from 40 MHz to 65 GHz. Further, the VNA is equipped with a time domain option, thus, the instrument is not limited to only frequency domain measurements. Time domain techniques are explained and evaluated later in this chapter. A test fixture [93] is a major part of the measurement setup. In contrast to wafer probe stations, the test fixture provides a flexible and inexpensive way to contact printed circuits board and substrates to perform measurements. The distance of the test ports to each other can be adjusted in lateral direction to a great extend. This allows the mounting of different-sized boards and substrates in the test fixture. As coaxial to planar CHAPTER 4. CHARACTERIZATION TECHNIQUES 72 transmission guide transition, launchers [93] are used along with the universal test fixture. These launchers include coaxial 1.85 mm v-connectors, whose upper frequency limit is 70 GHz. A photograph of the measurement setup is presented in Fig. 4.12. Fig. 4.4 gives a photograph of the utilized v-launchers.

Figure 4.12: Measurement setup

Further, coaxial 1.85 mm cables suitable for frequencies up to 70 GHz [107] connect the ports of the VNA and the launchers mounted in the test ﬁxture. The VNA supports numerous calibration techniques in planar as well as coaxial technologies. A 1.85 mm TRL and SOLT calibration kit [108] is used for coaxial calibration of the instrument. Regarding planar calibration, custom made calibration standards for TRL and Time Domain De-embedding are utilized. Fig. 4.6 shows a photograph of the planar standards. CHAPTER 4. CHARACTERIZATION TECHNIQUES 73

4.4 Frequency Domain Characterization Tech- niques

This sections deals with package characterization in the frequency domain. Scat- tering parameters are used in the high frequency region to describe the electrical performance of devices. In general, the term ”high frequency”applies to operating frequencies whose wavelengths are comparable to the dimensions of the device. After a short overview of scattering parameters, a de-embedding technique suitable for package characterization is presented. This is followed by a presentation of measurements results of actual packages.

4.4.1 Scattering Parameters

For the sake of completeness, a brief introduction to scattering parameters is presented in this chapter. Voltages and currents are defined as integrals of the electric field strength and magnetic field strength along an integration path. At high frequencies, the solution of these integrals strongly depend on the integration path. Thus, voltages and currents are no longer well-defined. In addition, the necessary efforts for current and voltage measurements increase. As a result, the electrical performance of devices is described by means of scattering parameters in the high frequency region. Scattering parameters consider the traveling waves, rather than voltages or currents. Fig. 4.13 illustrates this.

Source two-port network Load

a1 b 2 a L

Z 1 I 1 I 2 U U Z 1 1 2 2 L

b1 a 2 b L

Figure 4.13: Two-port network and traveling waves

The scattering parameters relate the traveling waves bi scattered or reﬂected from the network to those traveling waves ai incident upon the network. For the two- port network shown in Fig. 4.13 this is done according to the following set of equations:

b1 = S11a1 + S12a2 (4.3) CHAPTER 4. CHARACTERIZATION TECHNIQUES 74

b2 = S21a1 + S22a2. (4.4)

If the load impedance Z2 is equal to the characteristic impedance of the transmission line, the reflected wave a2 becomes zero. Hence, no reflections of incident waves occur at the load. The standardized waves ai and bi traveling to and back from the two-port network are defined as

Ui + ZiIi ai = (4.5) 2 (Zi) |ℜ | q ∗ Ui Zi Ii bi = − . (4.6) 2 (Zi) |ℜ | q

In general, the reference impedances Zi are real and equal to the characteristic wave impedance Zwi of the transmission lines leading to port i. Under this condition the deﬁnition of the standardized waves can be written as

Ui Ii√Zwi ai = + (4.7) 2√Zi 2

Ui Ii√Zwi bi = . (4.8) 2√Zi − 2

Measurement of scattering parameters is done by terminating all ports except the measured port with the characteristic wave impedance Zw. Under this precondition all traveling waves ai incident upon the network except the wave propagating to the measured port become zero. The scattering parameter is obtained by measuring the incident and reﬂected waves ai and bi of the measured port according to

bi Sii = aj =0(j = i). (4.9) a 6 i

In general, the scattering parameters Sij are measured by terminating the appropriate ports and hence setting the traveling waves to the network, i.e. the reﬂected waves from the load, to zero. This is done automatically by the utilized measurement instruments. An extensive introduction to scattering parameters and related topics is presented in [109].

4.4.2 De-embedding

Integrated circuits are usually encapsulated by a mold compound to protect the die from external hazards. Because of this, direct measurement of the package CHAPTER 4. CHARACTERIZATION TECHNIQUES 75 performance is not applicable. A straight two-port characterization requires the probe or connector of the second port to be attached on the chip inside the package. Since the chip pads or wirebond pads are typically not accessible due to the mold compound, straightforward transmission measurements cannot be performed. By etching processes the encapsulant can be removed. However, this alters the surrounding area of the signal pathway inside the package and thus the electrical performance of the transmission. One-port measurements of fully assembled packages including the mold compound can be performed without additional eﬀort, though. Two-port scattering parameters entirely characterize the electrical performance of signal pathways in a package. A package de-embedding technique using port reduction methods [110] has been investigated and evaluated in the course of this thesis. It is based on a series of one-port measurements performed on fully assembled packages and calculates the two-port scattering parameters from the measured data. Starting point for this de-embedding method is the deﬁnition of the scattering parameters for a two-port network (see Fig. 4.13) according to

b1 = S11a1 + S12a2 (4.10) b2 = S21a1 + S22a2 (4.11) and the definition of the reflection coefficient ρL of a one-port impedance matched load

bL ρL = . (4.12) aL Further, the wave propagating from the unknown two-port network is equal to the wave traveling toward the load. The same is true for the wave reﬂected from the load and traveling toward the two-port network, hence

b2 = aL (4.13)

a2 = bL. (4.14)

Considering this property and inserting Equation 4.12 into Equation 4.11 yields

S21a1 b2 = . (4.15) 1 S22ρL − After substitution of b2 in Equation 4.10 with Equation 4.15, the following expression for the input reﬂection coeﬃcient ρIN is obtained:

b1 S21S12ρL ρIN = = S11 + . (4.16) a1 1 S22ρL − CHAPTER 4. CHARACTERIZATION TECHNIQUES 76

Thus, Equation 4.16 translates the reflection coefficient ρL of the load through the unknown two-port network to the reflection coefficient ρIN of the two-port network. This reflection coefficient can be directly measured. For package structures, S21 = S12 can be assumed which reduces the number unknown components in Equation 4.16 to three, namely S11, S21 and S22 of the two-port network. There- fore, three different loads are required to calculate the unknown values that define the electrical characteristics of the two-port network. It should be noted that the load devices can be arbitrary. The mathematical analysis tool Mathematica [111] was employed to solve the resulting linear system of equations and express the scattering parameters S11, S21, S22 in terms of the measured reflection coefficients ρL1, ρL2 and ρL3, respectively. The methodology is further illustrated in Fig. 4.14. First, the reflection coefficients S11 of three arbitrary one-port standards are measured. This yields a first set of scattering parameters S11a, S11b and S11c (Fig. 4.14(a)). Then, these already characterized standards are assembled in a package and measured again. ∗ ∗ ∗ Another set of scattering parameters S11a, S11b, S11c is obtained (Fig. 4.14(b)). These scattering parameters basically represent the initial scattering parameters S11a, S11b, S11c transformed through the unknown two-port device according to Equation 4.16.

1 2 3

(a)

unknown 2-port device 3 known 1-port devices

? 1 2 3

(b)

Figure 4.14: Theory of de-embedding procedure

Several measurements were performed to evaluate the de-embedding technique. In a ﬁrst step, two-port network samples were measured and characterized by scattering parameters. These samples included transmission lines and through connections in TSLP and BGA packages. Next, one-port standards were characterized. These were attached to the two-port network samples and measured CHAPTER 4. CHARACTERIZATION TECHNIQUES 77 afterwards. Based on these measurements, the scattering parameters of the already known two-port networks were calculated using the obtained set of three linear equations. Exemplary results are presented in Fig. 4.15, which shows the calculated and measured scattering parameter S21 of a transmission line mounted in the universal test ﬁxture.

0,0

-0,2

-0,4

-0,6

-0,8 [dB] -1,0 21 S

-1,2

-1,4

-1,6

Calculated results

-1,8

Measured results

-2,0

0 2 4 6 8 10 12 14 16 18 20

Frequency [GHz]

Figure 4.15: De-embedded transmission line (Z0 = 50 Ω)

Besides some minor noise which can be neglected, the calculated scattering parameters of the two-port network are considered equal to the measured parameters. Thus, the de-embedding procedure is capable to accurately calculate the scattering parameters of an unknown two-port network using only one-port measurements.

4.4.3 Frequency Domain Package Characterization

The proposed package de-embedding method was utilized to determine the performance of packages in frequency domain. Therefore, a test chip suitable for frequency domain package characterization was designed and manufactured. The chip contains a total of six diﬀerent one-port structures. These are an open circuit, a short circuit, a 50 Ω load, a 75 Ω resistance, an inductance as well as a capacitance. An illustrative image of the chip layout is shown in Fig. 4.16. The dimensions of the chip are 650 µm 470 µm. × CHAPTER 4. CHARACTERIZATION TECHNIQUES 78

Figure 4.16: Layout of test chip

The reflection coefficients S11 of these structures were measured using a probe sta- tion and wafer probes. After this initial characterization, the chips were mounted in several packages including TSLP and BGA packages. Next, the packages were soldered on Rogers RO3003 high frequency laminates. For measurement of the one-port reflection coefficients, the setup described in Chapter 4.3 was employed. Further, TRL calibration and Time Domain De-embedding techniques were applied to establish the reference plane at the package connector. Then, the one-port measurements to obtain the reflection coefficients of the assembled standards were performed. Afterwards, the calculations of the two-port scattering parameters were done using Agilent Advanced Design System 2003 [60]. An example for frequency domain characterization is presented in Fig. 4.17 and Fig. 4.18, respectively. The calculated scattering parameter S11 of a TSLP-24 is depicted in Fig. 4.17. The chip was assembled using wirebond technology. Gold wirebonds with a diameter of 25 µm were used. Since the length of these wirebonds is about 1.5 mm, the reflection coefficient S11 is very high. The transmission coefficient S21 is shown in Fig. 4.18. Due to the wirebond length, resonance effects occur at about 33 GHz and 46 GHz. In the presented example, the TRL calibration method was used. In general, the de-embedding method works independent from the utilized calibration procedure. Another measurement result is presented in Fig. 4.19 and Fig. 4.20. The scattering parameter S11 of a BGA packages is shown in Fig. 4.19. The utilized BGA is not designed for high frequency applications, hence serious impedance mismatch can be seen in Fig. 4.19. This is caused by wirebonds with a length of about 1.5 mm and additional conductors used for signal redistribution on the substrate. Hence, the entire signal pathway inside the package is several millimeters long, which cause reflections, losses and resonances as seen in Fig. 4.19 and Fig. 4.20. The scattering parameter S21 is depicted in Fig. 4.20. Transmission performance degrades for frequencies above 5 GHz to a great extend. CHAPTER 4. CHARACTERIZATION TECHNIQUES 79

-5

-10 [dB]

-15 11 S

-20

-25

-30

0 5 10 15 20 25 30 35 40 45 50

Frequency [GHz]

Figure 4.17: Scattering parameter S11 of TSLP-24 (Z0 = 50 Ω)

-5

-10 [dB]

-15 21 S

-20

-25

-30

0 5 10 15 20 25 30 35 40 45 50

Frequency [GHz]

Figure 4.18: Scattering parameter S21 of TSLP-24 (Z0 = 50 Ω) CHAPTER 4. CHARACTERIZATION TECHNIQUES 80

-5

-10

-15 [dB] -20 11 S

-25

-30

-35

-40

0 5 10 15 20 25 30 35 40 45 50 55 60 65

Frequency [GHz]

Figure 4.19: Scattering parameter S11 of BGA (Z0 = 50 Ω)

-10

-20 [dB]

-30 21 S

-40

-50

-60

0 5 10 15 20 25 30 35 40 45 50 55 60 65

Frequency [GHz]

Figure 4.20: Scattering parameter S21 of BGA (Z0 = 50 Ω) CHAPTER 4. CHARACTERIZATION TECHNIQUES 81

4.5 Time Domain Characterization Techniques

Time domain techniques have primarily been used for impedance characterization [21][22] and failure analysis [23][24][24] on rather large devices. Typical examples are the fault localization of a long cable, which is broken at some unknown point, or failure analysis on a large printed circuit board. This characterization technique is based on a voltage step created by a source, which is applied to the device under test. The voltage step is partly reflected at discontinuities inside the device under test and sent back toward the source. The reflected amount of energy is measured by the reflection coefficient. It is defined as

Vreflected Z Z0 ρ = = − . (4.17) Vincident Z + Z0

The impedance Z0 designates the reference impedance of the measurement setup which is typically 50 Ω. The complex impedance of the discontinuity is denoted Z. The voltages Vreflected and Vincident denote the reflected voltage due to the discontinuity and the incident voltage, respectively. Hence, the voltage level of the reflected waveform is directly related to the complex impedance of the discontinuity. The instrument receives the reflected waveform and calculates a voltage profile depending on time of the device under test. The voltage profile represents the impedance behavior inside the device under test. This technique is commonly known as time domain reflectometry [112]. The measurement methodology is further illustrated in Fig. 4.21.

Voltage Profile of DUT

Reflected voltage step

Source (Z0) DUT (Z) outputs voltage (e.g. cable, PCB step or pulse or package)

Incident voltage step

Figure 4.21: TDR operation principle

In Fig. 4.22 a brief overview of some common lumped elements and their voltage proﬁle is given. The complex impedance of an inductor and capacitor is

ZIND = jωL (4.18) CHAPTER 4. CHARACTERIZATION TECHNIQUES 82

1 Z = (4.19) CAP jωC where L and C denote the values for inductance and capacitance, respectively. The circle frequency ω is

ω = 2πf. (4.20)

Thus, at DC and low frequencies, an inductive termination acts as a short circuit, while a capacitive termination resembles an open circuit. The voltage proﬁle of these terminations is further depicted in Fig. 4.22.

Series Inductance V

Z0 Z0

t V Shunt Capacitance

Z0 Z0 t

Inductive Termination V

t V Capacitive Termination

Z0 t

Figure 4.22: Common discontinuities

The location of failures and discontinuities can easily be calculated since the propagation time of the signal is measured. The speed of a propagating wave inside a medium is CHAPTER 4. CHARACTERIZATION TECHNIQUES 83

c0 c = (4.21) √εeff

8 where c0 is the speed of light in vacuum (c0 = 3 10 m/s) and εeff the eﬀective dielectric constant of the medium where the wave· is propagating. The spatial distance l of the discontinuity from the source can be calculated straightforward if the eﬀective dielectric constant is known using

c0t l = ct = (4.22) √εeff where t designates the time the signal requires to travel to the discontinuity in question. This propagation time is measured and displayed by the instrument. Thus, time domain reflectometry is well suited for failure analysis. Broken wirebonds or conducting traces on substrates and their position can be located effortless with very good accuracy. Semiconductor packages are rather small devices. Especially for leadless packages the dimensions typically are in the millimeter region. Furthermore, packages can contain numerous different discontinuities, e.g. vias, wirebonds or traces on substrates. For time domain characterization of the package it is mandatory that different discontinuities can clearly be separated from each other. The risetime of the incident voltage step plays a crucial role and is one major factor for the minimal distance between two discontinuities to be distinguished. It determines the spatial resolution of the measurement system and its capabilities to separate individual discontinuities. If two discontinuities are separated by a large distance, they can be distinguished easily. However, when they move together, the respective waveforms begin to intersect. Thus, if the risetime is not steep enough, the rising edge of the incident pulse covers both discontinuities at once. As a result, both discontinuities cannot be resolved and may appear as one single discontinuity. This is further illustrated in Fig. 4.23. Fig. 4.23 shows a microstrip line with two impedance changes and their corresponding waveforms. At first, the sections of the microstrip lines and their impedance can clearly be determined. However, as the narrow microstrip sections move together, the waveforms and thus the voltage profiles begin to intersect. If they move even closer, the broad microstrip part between the two narrow sections cannot be clearly resolved any longer. Thus, a shorter risetime results in a higher spatial resolution as a direct consequence. As a rule of thumb [113], two discontinuities can be separated from each other if the distance between them is at least

c0trise lmin = . (4.23) 2√εeff CHAPTER 4. CHARACTERIZATION TECHNIQUES 84

V V

t t

Figure 4.23: Impact of risetime on spatial resolution

As before, c0 denotes the speed of light, trise is the risetime of the incident voltage step and εeff the eﬀective dielectric constant of the medium. For package characterization, a sub-millimeter resolution is mandatory. Assuming an eﬀective permittivity εeff of 4, a common value for package mold compounds and substrates, a risetime of about 13 ps is needed to obtain the desired sub-millimeter spatial resolution.

4.5.1 Realization

This chapter deals with the realization and implementation of time domain measurements systems. Two approaches exist. The ﬁrst uses a conventional time domain reﬂectometer (TDR), the second one utilized a vector network analyzer with equipped time domain option [114].

Time Domain Reﬂectometer

The most common and more traditional measurement instrument used for time domain reflectometry is the time domain reflectometer. A TDR directly works in time domain. A signal generator generates the output voltage step. Actual instruments that are available on the market to-date create a voltage step with CHAPTER 4. CHARACTERIZATION TECHNIQUES 85 a rise time down to 35 ps [28]. Using Equation 4.23 and assuming an effective dielectric constant εeff of 4 for the mold compound, this risetime yields a spatial resolution of 2.625 mm. To obtain lower risetimes and thus increase the spatial resolution, an external source enhancement module (SEM) [113] can be used in conjunction with actual time domain reflectometers [115]. Fig. 4.24 shows a photograph of a TDR with the source enhancement module.

Figure 4.24: TDR with source enhancement module [3]

This module receives the 35 ps voltage step provided by the TDR and converts it to an output voltage step with a risetime of about 9 ps. This step is applied to the device under test afterwards. A 70 GHz sampling head receives the reflected waveform from the device under test and calculates a voltage and an impedance profile. A block diagram of this measurement setup is further shown in Fig. 4.25. In addition, normalization is utilized [116]. Normalization is a error-correcting process in time domain similar to the calibration of vector network analyzers. The method can significantly reduce or remove all kind of error types. These include reflections due to impedance mismatch and losses caused by cables and connectors. Normalization requires only one step generator and one calibration standard. The characteristics of the measurement setup are gained by performing two measurements. The first part of TDR calibration removes systematic errors due to trigger coupling, crosstalk and reflections from cables as well as connectors by measuring a short standard. The frequency response of the test system is derived from the measured short. The second part of the calibration generates the digital filter. This is done by measuring a termination having an impedance equal to the characteristic impedance of the transmission guide. These two measured waveforms are stored and subtracted directly from the measured response of the CHAPTER 4. CHARACTERIZATION TECHNIQUES 86 device under test. Additional information about the normalization procedure is given in [117] and [118].

Display of Voltage Profile

tRISE = 35 ps DUT

SEM

tRISE = 9 ps

Figure 4.25: TDR measurement setup block diagram

Fig. 4.26 compares the output voltage step of the TDR and TDR with SEM, respectively. The waveform using the SEM is affected by noise. This is due to the amplification performed by the SEM. The 200 mV output voltage step of the TDR is amplified up to 4 V and cut off in order to increase the risetime. As a consequence, noise of the original voltage step is also amplified. The distorted signal provided by the SEM makes it rather difficult to distinguish between artifacts caused by the noise and effects of actual discontinuities inside the package. The step of the TDR without source enhancement module is not distorted, however, the risetime of 35 ps is not sufficient for high resolution package characterization since the mandatory sub-millimeter resolution is not achieved.

Vector Network Analyzer

In addition to conventional TDRs, vector network analyzers can also be used for time domain reflectometry [119][106]. Vector network analyzers are essentially used for measurements and device characterization in the frequency domain. In contrast to a TDR, a VNA generates a sinusoidal waveform which is applied to the device under test. The frequency of the output waveform is swept over a certain frequency range. The maximum frequency is limited by the bandwidth of the instrument. Similar to a TDR, the incident sinusoidal waveform is reflected from the DUT and received by the VNA. Hence, a VNA does not create a time dependent voltage profile of the DUT. Instead, the frequency dependent characteristics of the measured device are obtained [120]. However, many state-of-the-art instruments also provide a time domain option. This option converts the measured CHAPTER 4. CHARACTERIZATION TECHNIQUES 87

0,25

TDR without SEM

TDR with SEM

0,20

0,15

0,10 Voltage [V]

0,05

0,00

-0,05

0 50 100 150 200 250 300

Time [ps]

Figure 4.26: TDR and TDR with SEM Comparison frequency domain data into time domain by means of the Fourier transform and inverse Fourier transform, respectively. The Fourier transform and inverse Fourier transform are deﬁned as

−∞ F (jω) = f(t) e−jωtdt (4.24) ∞ Z 1 −∞ f(t) = F (jω) ejωtdω. (4.25) ∞ 2π Z Thus, the vector network analyzer with built-in time domain option essentially simulates a conventional time domain reflectometer. The bandwidth of the network analyzer determines the rise time of the virtual voltage step. Fig. 4.27 shows the influence of the bandwidth on the achievable risetime. Using an instrument with a bandwidth of 65 GHz results in a risetime of approximately 8 ps of the voltage step. According to Equation 4.23, the spatial resolution of this measurement setup is about 0.6 mm. In comparison to the step generated by the TDR, the voltage step provided by the VNA is very smooth and not affected by any distortion at all. This is a direct result of the high bandwidth and advanced calibration techniques of the instrument. In addition, vector network analyzers with time domain option often allow the selection of different window functions which are applied during the Fourier CHAPTER 4. CHARACTERIZATION TECHNIQUES 88

1,2

1,0

0,8

0,6

0,4 Voltage[V]

0,2

20 GHz Bandwidth

0,0

65 GHz Bandwidth

-0,2

-20 -10 0 10 20 30 40 50 60

Time [ps]

Figure 4.27: Bandwidth inﬂuence on voltage step risetime transform (Equation 4.24) and inverse Fourier transform (Equation 4.25), respectively [121]. Using a rectangular window decreases the risetime down to about 4 ps on the cost of increased ripple of the voltage step. Fig. 4.28 compares the output step of the VNA using rectangular and normal windowing. Utilizing a rectangular window function increases the accuracy when time domain reﬂectometry is only used for fault localization. The spatial resolution to locate discontinuities increases to 0.3 mm. However, the additional ripple yields slightly inaccurate results when impedance analysis of packages is performed.

4.5.2 Time Domain Package Characterization

For the comparative measurements and to evaluate time domain techniques for package characterization, TSLP and LFBGA96 (Low proﬁle Flat Ball Grid Array with 96 solder balls) packages were assembled. Each package contains a test chip which was designed solely for package characterization purposes in time domain. Several known on-chip standards are realized on this test chip. These are open circuits, short circuits, 50 Ω resistances and a 75 Ω mismatch. After package assembly, the packages were soldered on Rogers RO3003 and Rogers RT Duroid 5880 substrates [92]. A photograph of the two packages types on evaluation modules is presented in Fig. 4.29. The dimensions are 3.5 mm 3.5 mm for the TSLP and 10 mm 10 mm for the BGA packages, respectively.× For measurements, a × CHAPTER 4. CHARACTERIZATION TECHNIQUES 89

Rectangular window

1,2

Nominal window

1,0

0,8

0,6

0,4 Voltage [V]

0,2

0,0

-0,2

-80 -70 -60 -50 -40 -30 -20 -10 0 10 20

Time [ps]

Figure 4.28: Output step using different window functions test fixture as shown in Fig. 4.12 is used. The fixture utilizes v-connectors which are suitable for frequencies up to 70 GHz [93].

Figure 4.29: Photograph of TSLP and BGA packages on test modules

A measurement results of one LFBGA96 package on RT5880 substrate is depicted in Fig. 4.30. The graph represents the voltage proﬁle of the package and shows the impedance behavior of the individual package structures. The on-chip open standard was measured. The graph can be separated into several sections (see designations in Fig. 4.30). Section 1 is the microstrip line on the RT5880 substrate. CHAPTER 4. CHARACTERIZATION TECHNIQUES 90

The conductors on the substrate inside the packages can be seen in section 2. These conductors show mainly inductive behavior with a small capacitive effect. The inductive behavior of the conductor is due to the missing ground plane inside the package. The capacitive effect is caused by an adjacent conductor, which causes small coupling. Section 3 is the wirebond inside the package. The bond areas on substrate and chip side introduce a capacitive behavior which can be located in the voltage profile (start and end of section 3 in Fig. 4.30). Finally, the on-chip open standard is seen in section 4. Considering the graph shown in Fig. 4.30, the impedance characteristics and behavior of the signal pathway can be determined straightforward. The entire signal pathway inside the package (seen in Fig. 4.30) is approximately solely 3 mm long. This high-resolution and accurate time domain characterization of such small devices is rendered possible by the short risetime of the incident voltage step and hence the achieved sub-mm spatial resolution. In addition, accuracy is considerably increased by the utilization of proper calibration techniques. Due to this, the incident voltage step is smooth and not affected by additional noise or distortion.

1 2 3

4 200 mV / / Div mV 200

10 ps / Div

Figure 4.30: Voltage proﬁle of a BGA package

Fig. 4.31 demonstrates the inﬂuence of the bandwidth on actual package measurements. The spatial resolution clearly becomes better as bandwidth increases. Additional bandwidth allows the separation between individual package components, which would not be possible otherwise. A comparison of measurement results obtained from a TDR and a VNA is given in Fig. 4.32. While both graphs show the same characteristics, the results from the VNA are hardly distorted. As a consequence, locating discontinuities inside the CHAPTER 4. CHARACTERIZATION TECHNIQUES 91

1,2

1,0

0,8

0,6

0,4 Voltage[V]

0,2

20 GHz Bandwidth

0,0

65 GHz Bandwidth

-0,2

60 80 100 120 140 160 180 200 220 240

Time [ps]

Figure 4.31: Bandwidth influence on package characterization package and their respective behavior proves to be more accurate. This becomes evident when the microstrip section (section A in Fig. 4.32) and chip bonding area (section B in Fig. 4.32) is considered. The VNA results clearly show a capacitive effect at the end of the microstrip line caused by the ground plane beneath the Rogers substrate. In contrast, this effect and its behavior cannot be located clearly when the TDR results are considered. The additional noise and distortion contribute to an inaccurate characterization and localization of this discontinuity. The chip bonding area is a similar example. While its capacitive behavior can be located from the VNA measurements without much effort, the distortion of the TDR graph gives no clear insight into the electrical performance of the chip bonding area. Fig. 4.33 shows the voltage profile of two signal pathways inside a BGA package soldered on RO3003 substrate leading to an on-chip short standard. Fig. 4.33 and subsequent presented graphs show measurement results that were obtained using the VNA measurement setup. Again, several package components can be identified. These are the microstrip line on the Rogers substrate and the PCB to package transition (approximately at 110 ps), the conductors on the substrate (110 ps to 140 ps), the wirebond (110 ps to 140 ps) and the short standard on-chip. While both graphs show the same basic characteristics, a capacitive coupling can be located directly in one graph (Short 1). This effect is explained when the layout of the substrate is considered. Below the copper trace on the top substrate layer for Short 1 is an additional grounded copper trace on the bottom CHAPTER 4. CHARACTERIZATION TECHNIQUES 92

B 200 mV / Div 200

VNA TDR

10 ps / Div

Figure 4.32: Voltage profile of a BGA package - TDR and VNA comparison side. This leads to a capacitive coupling effect, which is pointed out in Fig. 4.33. Since the conductor on the bottom side is missing for the other signal pathway (Short 2), the voltage profile does not show this effect. Hence, this and similar coupling effects can be located precisely and analyzed with high accuracy using time domain measurement techniques. As previously mentioned, time domain techniques are well suited for failure analysis and fault localization. Shown in Fig. 4.34 are two voltage profiles of two BGA packages. The signal pathway to the chip is supposed to be identical. In both cases the trace leading to the 75 Ω on-chip resistance was measured. However, one graph evidently indicates an open behavior. This is due to a broken wirebond inside the package. The x-ray photograph of the BGA substrate and the interconnects is shown in Fig. 4.35. The circle in Fig. 4.35 marks the broken wirebond. Consequently, using time domain reflectometry, the failure and further its position inside the package can accurately be evaluated without much effort. The measurement results one one TSLP soldered on RO3003 substrate are presented in Fig. 4.36. The package basically contains only the small sized contact pads and wirebonds as first level interconnects. In this case the length of the wirebonds is approximately 1.2 mm. Due to their length, the wirebonds show a strong inductive behavior. Therefore, Fig. 4.36 can be separated in three major sections. Section 1 represents the microstrip line on the Rogers substrate. In section 2 the inductive characteristics of the wirebond is shown. The terminating standards on chip are associated to section 3. In addition, a small capacitive effect is observed at about 140 ps due to the chip pad capacitance. CHAPTER 4. CHARACTERIZATION TECHNIQUES 93

1,0

Capacitive coupling

0,5

0,0

-0,5 Voltage [V]

-1,0

Short 1

-1,5

Short 2

-2,0

80 90 100 110 120 130 140 150 160 170 180

Time [ps]

Figure 4.33: Diﬀerent signal pathways leading to on-chip short standard

3,0

Broken wirebond

2,5

75 Ohm Impedance

2,0

1,5

1,0 Voltage [V]

0,5

0,0

-0,5

-1,0

80 90 100 110 120 130 140 150 160 170 180

Time [ps]

Figure 4.34: Broken bondwire voltage proﬁle CHAPTER 4. CHARACTERIZATION TECHNIQUES 94

Figure 4.35: X-ray photograph of a BGA package

1 2 3

Time [ps]

Figure 4.36: TSLP voltage proﬁle Chapter 5

Experimental Results

The performed measurement results of fully packaged applications in TSLP are presented in this chapter. Several test samples were assembled and measured to evaluate the electrical performance and especially the suitability of the package concept TSLP for high frequency applications. The considered components are actual integrated circuits manufactured in CMOS and Silicon Germanium bipolar semiconductor technology used by Infineon Technologies AG Munich, Germany. The circuits operate at very high frequencies. Further, wirebonds as well as flip chip bumps as first level interconnect technologies were utilized for certain applications. The assembled samples range from rather simple discrete components with very low pin counts to complex parts of communications systems in order to show that the package concept TSLP is well suited for a wide range of RF and mm-wave applications.

5.1 17 GHz WLAN Receiver

As a first RF demonstrator, a fully integrated 17 GHz wireless local area network (WLAN) receiver is considered. The chip is manufactured in 130 nm Standard CMOS technology and is intended for high data rate wireless LAN applications in the 17.2 GHz ISM band. WLAN system are increasingly used in offices and public areas to allow wireless high-speed network access from personal comput- ers and mobile devices. Traffic is expected to dramatically increase in the near future. One way to expand the network capacity is to extend the frequency range and bandwidth, respectively. The fully packaged chip provides sufficient gain and linearity for complex modulation schemes for WLAN applications in the high frequency range. The chip is assembled in a TSLP-24 package. The package dimensions are 3.5 mm 3.5 mm and the overall package height is 400 µm. Standard gold wirebonds with× a diameter of 25 µm are used as first level interconnects. The wirebonds have a length of about 500 µm. The parasitic inductance of the wirebonds is approximately 400 pH. These parasitic elements

95 CHAPTER 5. EXPERIMENTAL RESULTS 96 have already been considered during the chip design, hence the wirebonds act as an additional external matching network. Since the wirebonds represent the only major parasitic element of the leadless package concept TSLP, their impact on the overall performance can be taken into account very eﬃciently. Fig. 5.1 shows a polished-cut image of the package on an evaluation board. The photograph shows the die, the TSLP contact pads and the wirebond ﬁrst level interconnects. Additionally, the package footprint is displayed in Fig. 5.1.

Mold compound Wirebond interconnect TSLP contact pad Die

300 µm

Rogers RO4003 substrate

Figure 5.1: Polished cut image

The architecture implements a double-conversion receiver [122][123] with a divi- sion factor of four between the oscillator frequency and the intermediate frequency (IF). Off-chip intermediate frequency filtering is avoided by using a high IF. A block diagram describing the receiver architecture is shown in Fig. 5.2. It consists of the low noise amplifier (LNA), a dual conversion stage with an intermediate frequency amplifier, a voltage controlled oscillator (VCO) and a 4:1 divider stage together with a baseband output driver. Further implemented are buffers for the local oscillator (LO) frequencies and a 2:1 divider to provide output for an external phased-locked-loop. The receiver is designed with respect to high gain and linearity which are mandatory properties for complex modulation schemes used in WLAN applications. This work focuses on the performance of the fully packaged chip, hence circuit design and implementation of the building blocks would go beyond the scope of this thesis. A detailed description is found in [72]. CHAPTER 5. EXPERIMENTAL RESULTS 97

Figure 5.2: Receiver block diagram

The package is soldered on an evaluation board in order to perform measurements. A photograph of this board is shown in Fig. 5.3. Rogers RO4003 [92] with a thickness of 300 µm was selected as substrate material. A ratrace coupler generates the diﬀerential input signals which are applied to the circuit [124].

Figure 5.3: Receiver module CHAPTER 5. EXPERIMENTAL RESULTS 98

The measured gain of the circuit as a function of frequency is shown in Fig. 5.4. The baseband frequency is constantly set to 100 MHz. The chip provides its maximum gain of about 35 dB at 17.2 GHz, (see graph in Fig. 5.4. Fig. 5.5 shows the measured compression point and two tone intermodulation results. The two tones are 100 MHz apart. The input 1dB compression point is 49.6 dBm. For the measurements, a 50 GHz Agilent spectrum analyzer was used. All measurements include on-board microstrip lines and SMA connectors as shown in Fig. 5.3. A summary of the receiver performance is given in Table 5.1.

Figure 5.4: Receiver gain CHAPTER 5. EXPERIMENTAL RESULTS 99

Figure 5.5: Receiver two tone measurement

Table 5.1: Receiver performance summary

Supply Voltage RX 1.5 V Supply Voltage VCO 1 V 3 dB RF Bandwidth 17 - 17.35 GHz Gain 35 dB RX Noise Figure (SSB) 9.9 dB RX Input-CP @ 17.2 GHz -49.6 dBm RX Input IP3 @ 17.2 GHz -39.8 dBm Phase Noise @ 1 MHz Oﬀset -105 dBc/Hz LO1 Leakage to RF -53.6 dBm LO2 Leakage to RF -72.5 dBm Total Power Consumption RX 245 mW Die Area 1.2 mm Technology Standard 0.13 µm CMOS 6 Cu-metal layers CHAPTER 5. EXPERIMENTAL RESULTS 100

5.2 30 GHz Frequency Divider

A static frequency divider is considered as a second application. The divider circuit has a divide ratio of 16 and operates up to 30 GHz. Frequency Dividers are used in a wide variety of applications. They play an important role in the growing mobile and wireless communications market, since divider circuits allow the realization of phased-locked-loop (PLL) frequency synthesizers. Fig. 5.6 shows the block diagram of the frequency divider. The circuit has four asynchronous divider stages. Each stage consists of a master-slave D-type flip-flop. The inverted output of the individual stages is fed back to the data input. Each flip-flop performs a divide-by-two operation, thus an overall divide ratio of 16 is achieved.

Input D QN D QN D QN D QN Output

C Q C Q C Q C Q

Bias Network

Figure 5.6: Frequency divider block diagram

The schematic of one master-slave flip-flop is depicted in Fig. 5.7. The element is realized in emitter-coupled logic using series gating between clock and data inputs. To allow operation at supply voltages down to 3.6 V, single emitter followers are used. To obtain higher speed of operation, cascaded emitter followers can be used [125]. However, they require higher supply voltages, therefore cascaded emitter followers were not considered. The circuit internally uses differential signaling. Single-ended signals can also be used for input and output. A pream- plifier performs the single-ended to differential conversion, if single-ended signal are applied. An output buffer converts the differential output signal of the last divider stage to a single-ended signal. A chip photograph is depicted in Fig. 5.8. The chip is fabricated in a Silicon Germanium BiCMOS technology [126], where only the bipolar process is used. The layout of the frequency divider was optimized for short critical signal paths and reduced parasitic capacitances. The chip dimensions are 800 µm 650 µm. × The circuit was assembled in TSLP using wirebond and flip chip technology, respectively. For the wirebond version, a TSLP-7 was chosen. The flip chip version was assembled in a customized TSLP-6. The packages were soldered on evaluation boards to allow measurements of the device. CHAPTER 5. EXPERIMENTAL RESULTS 101

Vcc

D Q DN QN

CLK CLKN Bias

Master Slave

Figure 5.7: Flip-ﬂop schematic

Figure 5.8: Frequency divider chip photograph

5.2.1 Flip Chip Version

For the flip chip version of the frequency divider, a TSLP with six pins (TSLP-6) to connect the input and output, supply voltage, ground, as well as a power down control input was used [127]. The diameter of the circular shaped contact pads is 150 µm. AuSn-flip chip bumps with a diameter of approximately 30 µm were employed as first level interconnects. A photograph of the packaged circuit on the evaluation board is shown in Fig. 5.9. CHAPTER 5. EXPERIMENTAL RESULTS 102

Figure 5.9: Frequency divider soldered on Rogers RO4003 substrate

A polished cut image of the package is given in Fig. 5.10. Clearly visible are the chip itself, the contact pads of the package and the solder balls, as well as the microstrip line on the Rogers RO4003 substrate. The height of the contact pads is about 50 µm. The overall package height is 400 µm. To perform measurements, the package was soldered on a Rogers RO4003 high frequency substrate with a thickness of 300 µm. All measurements include losses due to the connectors and the evaluation board. The input sensitivity of the flip chip frequency divider is depicted in Fig. 5.11. The sensitivity represents the minimum input power needed by the circuit for operation and is the most important performance indicator. The dashed line represents the maximum input power applicable to the circuit. The maximum operating frequency is found to be near 30 GHz. This upper frequency is limited by the circuit itself rather than the package. Further, the fully packaged divider requires insignificant more input power compared to on-wafer measurements. For low frequencies, approximately up to 3 GHz, more input power is needed. This is due to the fact that the first divider stage requires a minimum slew rate of the clock signal. Therefore, the amplitude has to be increased in order to achieve the necessary slew rate, hence a higher input power is necessary. The lowest measured frequency is 1 GHz. CHAPTER 5. EXPERIMENTAL RESULTS 103

Moldcompound 40 µm AuSn Bump Chip 150 µm Contact Pin 50 Ω Microstrip Line

RO4003 Substrate h = 0.31 mm

500 µm Ground Plane

Figure 5.10: Frequency divider polished cut image

-10

-20 Sensitivity[dBm]

-30 TSLP-6

Bare-Die

Max. Power

-40

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

Frequency [GHz]

Figure 5.11: Frequency divider input sensitivity - ﬂip chip version CHAPTER 5. EXPERIMENTAL RESULTS 104

5.2.2 Wirebond Version

In order to compare interconnect performance, a frequency divider using wirebonds as first level interconnects was assembled in TSLP. For the wirebond version, a leadframe design with seven contact pads (TSLP-7) was considered. The utilized gold wirebonds have a typical length of 700 µm and a diameter of 25 µm. The package was soldered on a Rogers RO4003 high frequency substrate. Again, all measurements include losses caused by the substrate and the connectors. The measured input sensitivity is presented in Fig. 5.12. The dashed trace indicates the maximum input power applicable to the circuit. Directly compared to the flip chip version of the frequency divider, the wirebonded version requires approximately 10 dB more input power, even at low frequencies. This is due to the additional losses caused by the wirebonds. However, the circuit still operates up to 30 GHz if sufficient input power is provided. Thus, the utilization and choice between wirebonds technology or flip chip technology strongly depends on the application. Although flip chip shows superior performance compared to wirebond technology (see Chapter 3.4.2), the use of wirebonds is still an option for applications such as the presented frequency divider.

-5

-10

-15 Sensitivity[dBm]

-20

TSLP-7 -25

Bare-Die

-30 Max. Power

-35

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

Frequency [GHz]

Figure 5.12: Frequency divider input sensitivity - wirebond version CHAPTER 5. EXPERIMENTAL RESULTS 105

5.3 77 GHz Schottky Diodes

Originally the TSLP was intended for discrete components like transistors or diodes. The concept was later extended to support medium pin count solutions. As an application example for discrete components, high frequency Schottky diodes were considered. These diodes are intended for automotive applications and are designed for best performance in the 80 GHz region. The components were assembled using flip chip bumps and standard wirebonds as first level interconnects. The diodes are packaged in a TSLP-7 for the wirebond version and a TSLP-4 for the flip chip version, respectively. The packages are soldered on a Rogers RO3003 high frequency substrate with a thickness of 130 µm. This reduced thickness is mandatory to avoid parasitic higher order modes. Since scattering parameters are measured up to 110 GHz, propagation of unwanted higher order modes is possible if a thicker substrate is used. Fig. 5.13 shows a photograph of the used measurement board. Also included on the board are calibration structures.

Figure 5.13: 77 GHz Schottky diodes on Rogers RO3003 substrate

The diodes were measured utilizing a vector network analyzer and wafer probes in a ground-signal-ground (GSG) conﬁguration. The GSG probes have a probe tip pitch of 100 µm. The bandwidth of the measurement instrument is 110 GHz. Scattering parameters of the diodes were measured up to this frequency. Cali- bration was performed using a high frequency calibration substrate in order to include all characteristics of the measurement setup up to the probe tips in the measurements.

The measured reflection coefficient S11 of the diode in non-conducting state is presented in Fig. 5.14. The bias voltage was set to VBIAS = 0 V, i.e. there is no current flow and the diode acts as an insulator. Fig. 5.14 compares the wirebond and flip chip performance of the components. The wirebond version shows CHAPTER 5. EXPERIMENTAL RESULTS 106 increased parasitic effects and resonances. In contrast, the flip chip version of the diodes shows very good performance in the frequency range around 80 GHz. The scattering parameter S11 should be close to 0 dB since the diode basically represents an open circuit in non-conducting state.

-2

-4

-6 [dB] 11

S -8

-10

-12 Wirebond Flip Chip -14 0 10 20 30 40 50 60 70 80 90 100 110 Frequency [GHz]

Figure 5.14: Scattering parameter S11 - VBIAS =0V(Z0 = 50 Ω)

The measured scattering parameter S11 of the diode in conducting state is shown in Fig. 5.15. The bias voltage is set to VBIAS = 0.7 V. In this case, there is a current flow through the diode and the diode acts as a conductor. Assuming an ideal component, the reflection coefficient S11 should be 0 dB, since an ideal diode in conducting state acts as a short circuit. Again, one can see from Fig. 5.15 that the diode in TSLP-7 using wirebond interconnects shows more resonances and parasitic effects compared to the diodes in TSLP-7 using flip chip technology. The TSLP is very well suited for discrete components and applications in the mm-wave region if flip chip technology is used. Parasitic elements are very small, which is mainly due to the short signal pathways and small dimensions of the package. Low losses and no resonances occur. In contrast, the performance becomes unpredictable in the higher GHz region, if wirebond technology is used. Unwanted resonances and increased parasitic components can seriously deterio- rate the performance of the assembled chip, especially if the length of wirebonds increase. CHAPTER 5. EXPERIMENTAL RESULTS 107

-2

-4

-6

[dB] -8 11 S -10

-12 Wirebond -14 Flip Chip -16 0 10 20 30 40 50 60 70 80 90 100 110 Frequency [GHz]

Figure 5.15: Scattering parameter S11 - VBIAS = 0.7 V (Z0 = 50 Ω)

5.4 79 GHz VCO

The last presented RF application in TSLP is a voltage controlled oscillator (VCO) working in the 80 GHz range. For signal generation in the mm-wave region, diodes are often used. However, these diodes have a limited life span and replacement usually requires high effort. In addition, the use of these diodes is rather expensive. Another possibility for signal generation is the implementation of a VCO. VCOs oscillating in the upper mm-wave region emerged just recently. [128] presents a VCO manufactured in Silicon Germanium bipolar technology for automotive radar applications in the 80 GHz range. An extended version of the circuit presented in [128] was assembled in a TSLP-24 package. The VCO has a total of three differential outputs. These are one 2.4 GHz output, one 19.125 GHz output and the 79 GHz output, respectively. Besides the high frequency performance, another major issue is the thermal performance. The circuit has a total power consumption of about 2 W, thus additional heat transfer methods are mandatory in order to avoid damage of the circuit. As a consequence, the use of flip chip technology is not an option since flip chip bumps as first level interconnects provide insufficient heat transfer. Further it is not possible to attach an external heat sink without considerable effort when using flip chip technology. Hence, the die was assembled in the TSLP using wirebond technology as first level interconnect technology. CHAPTER 5. EXPERIMENTAL RESULTS 108

(a)

(b)

Figure 5.16: Photograph of VCO die on TSLP leadframe

A photograph of the VCO die on the TSLP leadframe before molding process is presented in Fig. 5.16. To reduce the total wirelength, the die was placed partly CHAPTER 5. EXPERIMENTAL RESULTS 109 beyond the die pad as it can be seen in Fig. 5.16(a). Previously performed electromagnetic ﬁeld simulations showed improved electrical performance using this die placement. The insert in Fig. 5.16(a) displays the diﬀerential high frequency output and the attached wirebond interconnects. Another photograph of the wirebond interconnect is presented in Fig. 5.16(b). The length of these wirebonds is approximately 300 µm. This results in a total parasitic inductance of about 250 pH. To perform measurement, the TSLP was soldered on an evaluation board. Special emphasis was put on the high frequency characteristics during the design of the board. As substrate material, Rogers RO3003 with a thickness of 130 µm was chosen. This low thickness prevents the propagation of parasitic modes, which are otherwise excited in the upper mm-wave region. 50 Ω microstrip lines are used as waveguide for the high frequency signals. The length of these microstrip lines is minimized for the 79 GHz output in order to minimize the attenuation of the waveguide. A photograph showing the evaluation board and the soldered package is presented in Fig. 5.17.

Figure 5.17: 79 GHz VCO in TSLP-24 on evaluation board

For measurements, wafer probes in a ground-signal-ground conﬁguration and a pitch of 100 µm were used. Instead of standard via holes, radial stubs [129] were designed for the 79 GHz interface to establish a ground connection for the wafer probes. At the target frequency the radial stubs act as a short circuit, but feature less parasitic inductance compared to via holes. The measurement setup used to measure the output power is displayed in Fig. 5.18. CHAPTER 5. EXPERIMENTAL RESULTS 110

Figure 5.18: 79 GHz VCO measurement setup

The measured oscillation frequency and corresponding output power using a supply voltage VSS of 5.7 V is summarized in Table 5.2. The oscillation frequency can be adjusted by a tune voltage Vtune, which can range from 0 V to 5 V. The tuning range of the VCO is about 7 GHz.

Table 5.2: VCO output power (VSS = 5.7 V, I = 387 mA)

VTune fVCO Output Power

0 V 75.07 GHz 5.45 dBm 1 V 79.136 GHz 5.75 dBm 2 V 80.384 GHz 6.67 dBm 3 V 81.088 GHz 6.4 dBm 4 V 81.536 GHz 5.83 dBm 5 V 81.888 GHz 5.6 dBm CHAPTER 5. EXPERIMENTAL RESULTS 111

Using a supply voltage VSS of 5.7 V results in a current consumption of 387 mA and a power consumption of about 2 W. The die features a temperature sensor and translates the measured chip temperature into a voltage VTEMP . A supply ◦ voltage VSS of 5.7 V results in a die temperature of about 100 C. To increase the output power of the VCO, the supply voltage can be increased. However, the power consumption and temperature also increase as a direct consequence. Table 5.3 presents the measurement results when a supply voltage VSS = 6 V is applied to the circuit. The measured temperature still does not exceed 100◦C. Thus, the additional heat can be directly transferred through the TSLP leadframe to the external heatsink with high eﬃciency. This in an important advantage of the package concept TSLP. In conclusion, the voltage controlled oscillator, fully assembled in a low-cost leadless plastic package, provides considerable output power even with the use of wirebond interconnect technology. This is achieved by the very short wirebonds and low parasitic elements of the package.

Table 5.3: VCO output power (VSS = 6 V, I = 413 mA)

VTune fVCO Output Power

0 V 74.656 GHz 5.99 dBm 1 V 78.848 GHz 6.11 dBm 2 V 80.128 GHz 6.92 dBm 3 V 80.85 GHz 6.92 dBm 4 V 81.31 GHz 6.47 dBm 5 V 81.664 GHz 6.11 dBm Chapter 6

Conclusion and Outlook

A low-cost leadless package concept (TSLP - Thin Small Leadless Package) aim- ing at applications in the RF and mm-wave range is presented in this thesis. Package characterization techniques have been investigated and applied to actual packages, including the TSLP. Especially time domain techniques have been proved to be suitable for a versatile usage including impedance characterization of packages, failure analysis as well as fault localization with high accuracy. A time domain measurement setup with a sub-mm spatial resolution has been introduced, which allows the accurate characterization of today’s small sized packages. The achieved sub-mm spatial resolution of the measurement setup is due to the use of a vector network analyzer equipped time domain option and high bandwidth as well as appropriate calibration techniques. Regarding frequency domain measurements, a de-embedding method using only one-port measurements and port order reduction methods has been evaluated and successfully applied to package characterization. The package concept TSLP makes a strong contribution to industrial demands on todays and future packaging technologies. The suitability of the package for high frequency applications is demonstrated by several assembled integrated circuits operating in the upper GHz range. The considered applications range from discrete component like 77 GHz Schottky diodes to complex 17 GHz wireless local area network receiver implementations. The suitability for mm-wave applications is especially shown by means of a fully packaged and fully operational 79 GHz voltage controlled oscillator. Actual high frequency applications mounted in a low-cost plastic package are presented for the first time. Currently the TSLP is under evaluation for future 24 GHz automotive radar systems. The qualification of the package, which includes extensive temperature and reliability analysis, is expected to start in the very near future. So far, only single chip applications in TSLP have been considered. Future fields of work include the evaluation of the package concept TSLP for multichip and System-in-Package applications. The evaluation of the RF and mm-wave capabilities of multichip- modules and System-in-Package solution is one major development topic. System- in-Package is considered to be one of the most significant future topics in pack-

112 CHAPTER 6. CONCLUSION AND OUTLOOK 113 aging technology. Another promising packaging solution are wafer level packages. So far, assembly and manufacturing cost are high compared to plastic package solutions. Further, wafer level assembly is subject to manufacturing tolerances to a great extend, hence it is desired to reduce these tolerances. However, wafer level packages offer highly flexible package design capabilities. Redistribution is possible due to the utilized thin film technology. In addition, passive components can be integrated as well as antenna structures, thus wafer level packages provide ex- ceptional System-in-Package capabilities. Further, high frequency performance is remarkable due to short signal pathways and the possibility to design impedance matched transmission lines. Future development topics include the minimization of manufacturing tolerances as well as the evaluation of wafer level packages for multichip modules working in the mm-wave region. Anhang A

Einleitung

Die Halbleiterindustrie kann zu jenen Industriezweigen gezählt werden, die durch größtes Wachstum und rasanten technischen Fortschritt charakterisiert werden können. Entsprechend dem Moore’schen Gesetz verdoppelt sich die Anzahl der Transistoren auf einem Siliziumchip etwa alle 18 Monate. Die demnach fortlau- fend steigende Integrationsdichte fuhrt¨ unmittelbar zu extremer Verkleinerung der Chipdimensionen und der integrierten Strukturen bis hin zum Nanobereich. Unabhängig davon bleiben die Größen und Interfacetechnologien im menschli- chen Umfeld konstant. Als direkte Konsequenz steigen die Anforderungen an die Leistungsfähigkeit der Bestuckungs-¨ und Verbindungstechnologien, welche die Schnittstelle zwischen Halbleiterchip und menschlichem Umfeld darstellen, rasant an. Es lässt sich also ein dringlicher Bedarf an neuen und innovativen Gehäuselösungen ableiten, um die schnelle Entwicklung der Halbleitertechnolo- gie und die Anforderungen zukunftiger¨ integrierter Schaltungen bewältigen zu können. Aktuelle Anforderungen an Halbleitergehäuse sind in Abbildung 1.1 zu- sammengefasst und unterstreichen zusätzlich die Notwendigkeit fur¨ innovative Weiterentwicklungen und technologische Verbesserungen. Uberdies¨ sind Gehäuse- anforderungen in zahlreichen Gehäuseroadmaps, beispielsweise der ITRS [4] oder JISSO [5], ausfuhrlich¨ beschrieben. Jedes in Abb. 1.1 dargestellte Entwicklungsthema, wie etwa verbesserte Wärme- abfuhr, reduzierte Abmessungen oder erweiterte Hochfrequenzeigenschaften, muss als entscheidender Funktionalitätsparameter zukunftiger¨ Gehäusetechnologien betrachtet werden. Im Zentrum der Gehäuseentwicklung stehen, basierend auf wirt- schaftlichen Uberlegungen,¨ geringer Kostenaufwand im Zuge der Produktion und optimierte Entwicklungs- und Produktionszyklen ( Time-to-Market“). Vom tech- ” nischen Standpunkt betrachtet, mussen¨ Gehäuse unterschiedlichste funktionale Leistungsmerkmale aufweisen. Zunächst einmal bieten Gehäuse Schutz vor mechanischen Belastungen, Luftfeuchtigkeit und ähnlichen Einflussen.¨ Ein wichtiger Parameter ist die thermische Leistungsfähigkeit des Produktes, da die vom Chip produzierte Wärme effizient abgefuhrt¨ werden muss. Außerdem benötigen kom- plexe Anwendungen, etwa Empfänger- und Senderimplementierungen fur¨ Mobil-

114 KAPITEL A. EINLEITUNG 115

Functionality (System Integration)

Speed Size

CostCost & TimeTime to MarketMarket

Thermal Low/High Performance Power

Reliability & Failure Analysis

Abbildung A.1: Trends in der Gehäuseentwicklung funkanwendungen, flexible Signalverteilung und gemeinsame Versorgungs- sowie Massenetze. Letztlich ermöglichen Gehäuse eine einfache Handhabung der Schal- tung und PCB-Montage.

A.1 Stand der Technik

Der gegenwärtige Stand der Technik ist durch eine breite Anzahl von verschiede- nen Gehäusetechnologien geprägt. Die meisten aktuellen Halbleitergehäuse können je nach Abmessungen, Herstellprozess und strukturellem Aufbau einer der folgen- den Gruppen zugeordnet werden:

Leadframe-Gehäuse (DIP, SOP, ...) • Laminat-Gehäuse (BGA, LFBGA, LGA, ...) • Leadless-Gehäuse (VQFN, TSLP, ...) • Chip Scale-Gehäuse (CSPs) • Wafer Level-Gehäuse (WLP, UWLP, ...) •

Leadframe-Gehäuse stellen eine kostengunstige¨ Gehäuselösung dar, sind jedoch oft mit Einbussen hinsichtlich ihrer elektrischen Leistungsfähigkeit behaftet [6]. Laminat-Gehäuse, wie beispielsweise das Ball Grid Array (BGA)-Gehäuse, ermö- KAPITEL A. EINLEITUNG 116 glichen eine hohe Kontaktdichte und bieten bei geeigneten Vorkehrungen eine verbesserte elektrische Leistungsfähigkeit [7]. Das Design von Laminat-Gehäusen ist aufgrund des verwendeten Substrates im Gehäuse sehr flexibel. Das Substrat bietet erweiterte Verdrahtungsmöglichkeiten, sowie die Möglichkeit zur Realisie- rung gemeinsamer Versorgungs- und Massenetze. Jedoch sind die Kosten eines Laminat-Gehäuses, verglichen mit anderen Plastikgehäusetechnologien, relativ hoch. Ursprunglich¨ wurden Plastikgehäuse nicht fur¨ Anwendungen im Millimeter- wellen- und Hochfrequenzbereich konzipiert [8]. Mit den seit kurzer Zeit in Ent- wicklung stehenden Chip Scale-Gehäusen [9][10] und Leadless-Gehäusen [11] wird versucht, in den Hochfrequenzbereich vorzudringen. Die Gehäusedimensionen sind klein, Signalwege generell sehr kurz und die Herstellkosten fur¨ diese Gehäusetypen sind vergleichsweise gering. Fur¨ Hochfrequenzanwendungen wurden bisher typischerweise Keramikgehäuse verwendet [12][13][14]. Dem Vorteil dieser Gehäuse im Bereich der Hochfrequenz- eigenschaften muss der Nachteil der kostenintensiven Herstellung gegenuber¨ ge- stellt werden. Außerdem sind Keramikgehäuse gewissen Toleranzproblemen sowie Verkleinerung ( Shrinkage“) während des Herstellungsprozesses unterworfen. ” Die meisten der kostengunstigen,¨ aktuellen Gehäuselösungen sind nicht fur¨ Hoch- frequenzanwendungen geeignet. Parasitäre Elemente beeinflussen deutlich die Lei- stungsfähigkeit integrierter Schaltungen. Beispielsweise zeigen die Kontakte der Leadframegehäuse ein stark induktives Verhalten, welches Verluste und Fehl- anpassung verursacht. Aus diesen Grunden¨ entsteht der Bedarf an neuen und innovativen Gehäusekonzepten, um aktuellen Anforderungen, besonders verbes- sertes Hochfrequenzverhalten, Rechnung zu tragen. Mögliche Lösungen wurden beispielsweise in [15][16][17] vorgestellt, jedoch wurde bisher keine aktuelle Hoch- frequenzanwendung präsentiert, welche die elektrische Leistungsfähigkeit dieser neuartigen Konzepte demonstriert. Im Zuge dieser Arbeit ist es gelungen, ein neues und innovatives Gehäusekonzept (TSLP) zu präsentieren, welches in Ver- bindung mit kostengunstiger¨ Herstellmöglichkeit alle technischen Attribute fur¨ Anwendungen im Hochfrequenz- und Millimeterwellenbereich vorweist. Bisher konzentrierte sich die Gehäusecharakterisierung im Wesentlichen auf die thermischen und mechanischen Eigenschaften, wie es beispielsweise in [16] zu sehen ist. Elektrische Charakterisierung spielte eine untergeordnete Rolle und wurde nur im unteren Frequenzbereich bis einige GHz durchgefuhrt.¨ Beispiele finden sich in [19][20]. Jedoch hat das Gehäuse bei höheren Frequenzen einen wesentlichen Einfluss auf die elektrische Leistungsfähigkeit der Schaltung. Ef- fekte wie etwa Signalubersprechen¨ sind in diesem Zusammenhang besonders zu erwähnen. Zudem verhalten sich Gehäusestrukturen nicht mehr wie konzentrierte Elemente, sondern mussen¨ als verteilte Elemente in Betracht gezogen werden, da die Wellenlänge bei steigender Frequenz in den Bereich der Gehäusedimensionen ruckt.¨ Aus diesen Grunden¨ wurde der elektrischen Charakterisierung in letzter Zeit immer mehr Bedeutung beigemessen [4]. Vor allem die Möglichkeiten der Zeitbereichsanalyse sind sehr vielversprechend. Zeitbereichsreflektometrie kann KAPITEL A. EINLEITUNG 117 zur Impedanzanalyse [21][22], als auch zur Fehlerlokalisierung verwendet werden [23][24][24]. Bisher wurden diese Techniken jedoch nur auf relativ große Baugrup- pen angewandt, wie etwa Transmissionsleitungen oder größere Leadframegehäuse [25][26][27]. Da jedoch die Abmessungen der Gehäuse immer kleiner werden, ge- staltet sich die Anwendung von Zeitbereichsmessungen an Gehäusen neuer Bau- art als durchaus schwierig. Hierbei stellt die Anstiegszeit des anliegenden Span- nungssprungsignals den wesentlichen limitierenden Faktor dar. Diese Anstiegs- zeit bestimmt das zeitliche Auflösungsvermögen des Messaufbaus. Aktuelle, auf dem Markt erhältliche Messgeräte bieten Anstiegszeiten von 35 ps, was in einer Ortsauflösung von 2.6 mm resultiert [28]. Um jedoch aktuelle Gehäuse, deren Di- mensionen im Millimeterbereich liegen, zu charakterisieren, ist mindestens eine Auflösung von unter einem Millimeter erforderlich. Bisher war eine genaue und hochauflösende Zeitbereichsanalyse von modernen Gehäusetypen aufgrund der er- forderlichen Anstiegszeit nicht realisierbar. Die Verwirklichung von entsprechend genauen Zeitbereichsanalysen ist daher als eines der Ziele dieser Arbeit definiert worden.

A.2 Motivation und Ziele der Arbeit

Wie bereits in Abschnitt A.1 angedeutet, wird im Zuge dieser Arbeit ein innovatives und neuartiges Gehäusekonzept präsentiert. Das Gehäuse TSLP (Thin Small Leadless Package) wurde insbesonders hinsichtlich eines breiten Anwendungsbe- reiches im Hochfrequenz- und Millimeterwellenbereich entwickelt. Ziel der Ar- beit ist die elektrische Charakterisierung des Gehäusekonzepts TSLP, besonders in Hinblick auf dessen Hochfrequenzeigenschaften. Das Gehäuse wurde auf Ba- sis von 3D Feldsimulationsprogrammen unter Variation der Gehäusegeometrien analysiert. Alle Ergebnisse zeigen eine vielversprechende Leistungsfähigkeit und besondere Eignung fur¨ Hochfrequenzanwendungen. Ein wesentlicher Teil dieser Arbeit beschäftigt sich mit Charakterisierungsmöglich- keiten aktueller Halbleitergehäuse. Zeit- als auch Frequenzbereichstechniken zur Charakterisierung wurden dabei in Betracht gezogen und entwickelt. Auf Grund- lage des bereits erwähnten vielseitigen Anwendungsportfolios von Zeitbereichsme- thoden, wurden im Zuge der Arbeit alle Aspekte der Realisierung in Zusammen- hang mit Anwendungen im Bereich der Gehäusecharakterisierung betrachtet. Es ist gelungen, einen Messaufbau fur¨ genaue Zeitbereichsmessungen mit einer Orts- auflösung von unter einem Millimeter zu konfigurieren. Hinsichtlich Frequenzbe- reichsmessungen wurde eine Messmethode untersucht, um Streuparameter eines unbekannten Zweitors, welches das Gehäuse repräsentiert, aus reinen Eintormes- sungen zu errechnen. Um die Leistungsfähigkeit des TSLP zu zeigen, wurden aktuelle Hochfrequenzan- wendungen aufgebaut und vermessen. Um ein umfangreiches Gebiet möglicher Anwendungen abzudecken, wurden Schaltungen mit diskreten Bauteilen bis hin KAPITEL A. EINLEITUNG 118 zu komplexen Teilen von Kommunikationssystemen untersucht. Die herausra- gende elektrische Leistungsfähigkeit des entwickelten Gehäuses wird durch einen vollständig aufgebauten und voll funktionsfähigen 79 GHz spannungsgesteuerten Oszillator demonstriert. Kapitel 2 dieser Arbeit gibt einen Uberblick¨ uber¨ Simulationstechniken, welche im Zuge dieser Arbeit angewandt wurden. Zwei der gängigsten Methoden werden näher vorgestellt, sowie deren Vor- und Nachteile hervorgehoben. Messungen an Testobjekten zeigen Ubereinstimmung¨ mit Simulationsergebnissen und validieren die verwendeten Simulationsmethoden. Kapitel 3 beschreibt aktuelle Gehäusetechnologien und elementare Strukturen, welche im Gehäusebau zur Anwendung gelangen. Die Funktionen und Leistungs- merkmale dieser Strukturen werden untersucht. Zusätzlich werden elektrische Kompaktmodelle, welche das elektrische Verhalten dieser Elemente wiedergeben, entwickelt. Diese Modelle sind fur¨ schnelle Funktionsanalysen von Gehäusedesign von besonderer Bedeutung. Weiters wird das Gehäusekonzept TSLP, sowie dessen vorteilhafte Eigenschaften, detailliert vorgestellt. In Kapitel 4 werden Charakterisierungstechniken von Gehäusen näher erläutert. Neben Zeit- als auch Frequenzbereichsmethoden, werden auch Möglichkeiten zur Charakterisierung von Gehäusematerialien behandelt. Messungen im Zeitbereich ergeben Impedanzprofile und eignen sich hervorragend fur¨ Fehleranalyse und Lo- kalisierung von Defekten im Gehäuse. Im Frequenzbereich bis 65 GHz werden die Eigenschaften der Gehäuse als Streuparameter beschrieben. Die aufgebauten Hochfrequenzanwendungen stellen den zentralen Inhalt des Ka- pitels 5 dar. Erstmals wurden aktuelle Hochfrequenzschaltungen in einem kostengunstigen¨ Plastikgehäuse aufgebaut. Die im Zuge von Messungen erzielten Er- gebnisse demonstrieren die Leistungsfähigkeit und Eignung des Gehäusekonzepts TSLP fur¨ zukunftige¨ Anwendungen im Hochfrequenz- und Millimeterwellenbe- reich. Dies wird durch einen spannungsgesteuerten Oszillator, welcher im 80 GHz- Bereich arbeitet, weiter untermauert. Bibliography

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Name Mario Engl Address Parkstr. 40/2, D-82008 Unterhaching Birth Date April 3rd, 1978 Birth Place Waidhofen a. d. Thaya, Austria Nationality Austrian

Education

1984 - 1988 Primary school, Privatgymnasium Neulandschule, Wien X 1988 - 1996 Grammar school, Privatgymnasium Neulandschule, Wien X

Studies

1996 - 2003 Electrical Engineering, Option: Communications and Radio Frequency Engineering, Diploma thesis ”Parasitics Extraction of Monolithic Integrated Inductors”, Technical University of Vienna. 2003 - 2006 Doctorate Study, Faculty of Technical Electronics, Doctorate Thesis ”Package Characterization Techniques and Evaluation of a Low-cost Leadless Plastic Package for mm-Wave Appli- cations”, University of Erlangen-Nuremberg.

Experiences

1994 - 1995 Vacation work at Fa. Denk, Vienna 1996 - 2001 Total of 11 month vacation work at Schindler Aufzuege und Fahrtreppen AG, Vienna 1998 - 2001 Part time working student based on a flexible 35 / month contract at Schindler Aufzuege und Fahrtreppen AG, Depart- ment of Logistics, Vienna, Austria 2002 - 2003 Infineon Technologies AG, Corporate Research, High Fre- quency Circuits, Munich, Germany. 2003 - 2006 Infineon Technologies AG, Corporate Assembly and Test, De- vice Modeling, Munich, Germany.

130 Acknowledgements

I would like to express my sincere thanks to my advisor Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel for giving me the opportunity to carry out this thesis and his kind support during the work. My gratitude also goes to Prof. Dr.-Ing. Georg B¨ock for critical reading of the manuscript. The work presented was supported by Inﬁneon Technologies AG, Munich, Germany. I would like to thank Heinz Pape and his team for supporting my thesis. Special thanks are due to my colleagues Dr. Wolfram Eurskens and Dr. Klaus Pressel for many informative and helpful discussions. I would like to take this opportunity to thank my parents for supporting my studies and for giving valuable advises in any situation of my life. Especially I want to express my thanks to my kind mother Monika as well as Harald for their support and for always giving me a warm welcome. Their encouragement contributed enormously to the motivation of my studies and accomplishment of this work. Finally, I would like to thank my little sister Angelika for countless joyful hours. Her kind nature always managed to cheer me up in any situation.

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