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Silanna Presentation Silanna Manufacturing Radiation Hardened Integrated Circuits for Space: The Journey Andy Brawley – VP of Manufacturing Presented at NSW Trade & Investment 18th June 2015 www.silanna.com [email protected] What are we? Silanna Silanna is a semiconductor component supplier to the Upstream Space Market 2 Who are we? Silanna is a semiconductor manufacturing company using a silicon-on-sapphire (SoS) process technology for high-performance RF-CMOS applications. A vertically integrated company that can design a product, manufacture the chips on its own process line, test and qualify the product, as well as provide route to market. Modern Building situated in the Australia Centre – Sydney Olympic Park NSW 150mm SoS CMOS wafer fab with 1100m2 Class 1-10 Cleanrooms 150mm Compound Semiconductor Fab with 550m2 Class 1 Cleanroom, Production Shift - 24 hrs/day, 7 days/week 3 New Compound Semiconductor Research Facility A $30M Investment in New Processes and Tool Types Deposition – Molecular Beam Epitaxy - Veeco Gen200 Dual Chamber Etch - PlasmaTherm LLC Versaline LL ICP Rapid Thermal Processor - Mattson 2800CS E-Beam Evaporator - Temescal X-ray Diffractometer - PANalytical X'Pert-PRO MRD Photoluminescence Mapping System - Nanometrics Vertex Hall Measurement System - Coherent Scientific System capable of depositing nitrides such as AlN, GaN, AlGaN etc 4 What do we do? Applications that use our chips 5 Deep Space Probes The farthest man-made object from the Earth is the Voyager 1 spacecraft, that has an RCA-built SoS microprocessor on-board. It was launched in 1977 and left our solar system in 2003. As of today it is more than 19 billion kilometres from earth and still functioning 6 Space Environment – just a little bit nasty REF: http://www.sail-world.com/index.cfm?nid=94565 In 2003 a large magnetic storm caused more than 47 satellites to malfunction, including the total loss of a scientific satellite valued at $640m. The largest magnetic storm ever recorded – Carrington of 1859 – If such a super-storm occurred today, the cost could be as high as $30bn 7 Space Radiation Effects 8 SoS vs. Competing RF Processes Bulk CMOS Process SoS Process contact silicon layer body gate contact oxide contact contact contact isolation gate contact gate gate tie oxide n+ p+ p+ n+ n+ p+ n-well p-well p-epitaxial layer insulating sapphire substrate p+substrate p-channel FET n-channel FET n-channel FET p-channel FET Oxide-isolated devices SiGe BiCMOS Process GaAs HBT Process trench isolation emitter AlGaAs p+ base contacts isolation implant SiGe collector oxide contact emitter emitter contact contactbody base base base contacts contact gate tie contact contact gate collector p+ n+ contact n-collector p+n+ p+ n-wellp+ n+ n+ p-welln+ p+ n- GaAs collector n+subcollector n+ p- n+ GaAs subcollector p-substrate semi-insulating GaAs substrate npn-bipolar HBT npn-bipolar p-channel FET n-channel FET 9 SoS Radiation Basics SiO2 Dielectrically N-channel P-channel isolated Sapphire transistors Ultra-thin Short lifetime Radiation induced layer ideal improves + charge only for SEE/SEU shifts Vt (Gauss’ Law) SEE/SEU Fully-depleted structure solves TID effects Gate Gate Oxide +++++++++++++++++++++ Source Ldd Ldd Drain NO Back-bias or Fully-depleted Channel NO field thermal effects NO back-channel effect inversion Zero volt Reduced or latchup Vt Edevices-fields NO body effect Zero substrate NO junction or major kink capacitance spiking Sapphire 10 How we support Space applications ELECTRONICS that has: Easy integration of RF, passives, mixed signal, and EEPROM on a single die Radiation-hard and Cryogenic temperature operation Optically transparent substrate for use in optical applications Lower parasitic capacitance = Higher Speed + Lower Power Consumption Fully depleted transistors, improving linearity, speed, and low voltage performance Excellent RF performance: o fmax typically 3X ft (60 GHz at 0.5 µm and 100 GHz at 0.25 µm) o very high linearity transistors (+38 dBm IP3 mixers) o high Q integrated inductors (QL > 40 at 2 GHz for 5 nH inductor) High isolation (>50 dB between adjacent devices) Processed in standard CMOS facilities on large wafers with low cost advantages 11 How we offer Space applications (2) SYSTEMS that include: ISO 9001:2008 LRQA certification AS9100 Rev.C LRQA accreditation US Defence MicroElectronic Activity (DMEA) Trusted Foundry clearance to “secret” level International Traffic in Arms Regulation (ITAR) free 12 Performance Advantages 1000GHz IBM and Semiconductor Industry Association Lower Cost, Roadmap Silanna Higher Returns 100GHz Transistor Cost of Speed building a Wafer Fab $50B $4B $200M free 1nm 100nm 1000nm Transistor Size 13 Our customers Peregrine Semiconductor based in San Diego CA USA. Aerospace Corp Jet Propulsion Lab Air Research Lab Lockheed Martin Alcatel Alenia MRC Army Research Lab NASA Goddard Astrium Northrop Grumman Boeing Oak Ridge National Lab Defence Microelectronic Activity Rockwell Collins DSTO Space Micro General Dynamics Thales Honeywell Ultra Communications 14 SpaceWire Link Isolator Target Features RIN1- EN 4 high speed (400 Mbps) RIN1+ ROUT1 I RIN2+ / ROUT2 channels O C RIN2- O GND N 2 transmit, 2 receive (Data+Strobe) T R DOUT2- O VDD Cable-side: LVDS DOUT2+ L DIN2 DOUT1+ DIN1 Module-side: LVTTL or LVDS DOUT1- EN- V LVTTL: LV049 Mode R VDDI G VDD E E G R DC-DC DC-DC LVDS: Repeater Mode GNDI V GND LVDS failsafe LV049 Mode Isolation voltage: 1 kVrms Integrated DC-to-DC isolator to power cable-side from module-side Cable-side data lines align well with SpaceWire cable connection LV049 Mode is functionally & signal-pin compatible w/ standard dual LVDS transceiver devices (ie. TI/NSC DS90LV049 series) 15 Low Noise Applications CSIRO SKA Radio Telescope LNA chip designed by LaTrobe University Silanna Antenna Receiver Chip 16 Integrated Wide Band Receiver 0.5 to 1.8 GHz 200 Receivers FROM THIS ASKAP Project Leader, Dr Dave DeBoer, with a receiver for CSIRO's prototype phased array feed. TO THIS “SKA is not possible without miniaturization” 17 Very Low Temperature Applications Centre for Quantum Computer Technology 90 x 900nm Quantum Computer Fabrication of external metal contacts aligned to buried Silanna voltage pulse phosphorus doped generator for Qubit transistor nanostructure operating at 30mK Single Atom Nanoelectronics Atomic-scale lithography 1 nm 2 mm 100μm 30μm SCANNING TUNNELING MICROSCOPE HUMAN EYE OPTICAL MICROSCOPE SCANNING ELECTRON MICROSCOPE 18 Low Power - High Density Applications Single-chip Military GPS Receiver 19 Optics on Sapphire (micro-displays) • XGA, VGA, SVGA demonstrated • RGB LED’s • No bulky optics • Standard UTSi CMOS process Full color micro-display on UltraCMOS sapphire Space and Naval Warfare Systems Center (SSC) in San Diego and Optron Systems collaborated on the fabrication of a first-generation, monochrome microdisplay. In 1999, Radiant Images, Inc., a spinoff from Optron Systems, was formed to commercialize the invention. 20 Photonics on Sapphire Optical Transceiver 21 MEMS on Sapphire Similar process to standard MEMS Standard SoS process Minor design rule changes Designed for optical, magnetic, & capacitive sensing Simple, standard post-CMOS processing Low-loss substrate helps MMW RF 22 Low cost prototypes A large cost of chip development is mask tooling and prototype wafers Compressed Reticle program significantly reduces tooling cost Small runs of protos or production possible Multiple mask layers on one Reticle 23 Production Flow for Space Products Program SOW Silanna Semiconductor Europe Overall Program Management Product Development Product development & Design Design-Simulations-Layout PDR Tape Out Full documentation set up CDR Quality assurance Mask Shop (Singapore) Mask MaskShop Foundry (Silanna Australia) Wafer Fab Wafer processing PROD. DEV. Spec DEV. PROD. PID & SCC9000 & PID WAT/WLR Backgrinding Design Validation Assembly (Europe) Wafer sawing Characterization Assembly (Packaging and bonding) MR Program Management Mechanical screening Logistic - Quality Management Logistic - Thermal cycles Wafer Sawing PIND test Precap Assembly Leakages Radiation Test & Screening (Europe) Test Wafer probe Electrical test Electrical test Screening DC, AC, RF and PN Data Package validation Electrical screening (Burn in, Life & Product control - Customer CSI test,…) Qualification and Periodic Tests 24 Chip Manufacturing Services Ideal for RF/Mixed Signal and Digital designers Silicon-on-Sapphire 0.5 µm Single Poly Triple Metal SoS 0.25 µm Single Poly Triple Metal SoS 3 variants of each High volume - High mix – High Flexibility 6 weeks fab cycle time – Compressed reticle Cadence & AWR Process Design Kit (PDKs) Wafer dicing + Prototype assembly services “Use SoS for your advanced RFIC designs” 25 Compressed Reticle Compared to Multi-Project Wafers No schedules – start when ready Wafer dedicated to customer design Potentially thousands of devices per wafer Can use for low volume production Quicker re-spin times Much lower chip cost Easy transition to production 26 Prototype IC Packaging Laser scribe and break – sapphire and quartz Die bonding Wirebonding – wide range of open cavity plastic & ceramic packages Expertise in Assembly with 20+ years experience in IC assembly ESD safe Class 10K clean room Fast turn including same day delivery of small quantities 27 Questions please 28 Excellence Awards 2004 Western Sydney Industry Awards Presented by NSW Premier Bob Carr 2006 EDN Innovation
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