Short Term Course on Scope of the Course 4. Post-routing Simulation for Performance Analysis. FPGA Specific Structural Optimization Advanced DSP The course aims at providing a comprehensive with respect to Speed and Area. coverage of techniques for designing efficient 6 Configuration Bit Stream Generation for Actual Design Techniques VLSI architectures for DSP, especially for Implementation on FPGA (F22222222222228888888REE for teachers from applications like IOT, machine learning and big data. Towards this, architectural optimization The course may be viewed as a consolidated TEQIP-III Colleges) both at block level as well as at logic level will form of a semester long, graduate course on be considered. The key issues that will be taken VLSI DSP system/architecture design. up are as follows: Participants from academia may thus find the ♦ ♦ Graphical Representation of DSP Algorithms course to be useful to develop similar courses at ♦ ♦ Retiming for Throughput Maximization their respective institutions. Alternatively, the ♦♦ Pipelined and Parallel Filter Structures course may also be used as a reference by ♦♦ Bit Serial Digital Filters industrial professionals interested in VLSI design ♦♦ Distributed Arithmetic and Multiplierless of signal processing and communication systems. Realization The course assumes minimal prerequisites - an ♦♦ Redundant Arithmetic undergraduate level knowledge of digital circuit ♦ ♦ DSP Architectures: Datapath and Control design and elementary DSP operations is ♦♦ Speed-Power-Area-Accuracy Tradeoff sufficient for one to be able to attend the course. ♦♦ Synchronous vs. Asynch. Designs ♦♦ Memory Bandwidth Management ♦ About the Speakers ♦ DSP for Embedded Applications The course also intends to have a few Prof. Mrityunjoy Chakraborty obtained Lab sessions in order to demonstrate digital Bachelor of Engg. (1983), M.Tech. (1985) and design flow on Field Programmable Gate Array Ph.D. (1994) from , IIT (FPGA), where the following modules may be Kanpur and IIT, respectively. He joined covered: IIT, as a lecturer in 1994, where he 1. Behavioral and Structural Description for presently holds the position of a full professor. Design Representation and Design Entry. 2. Validation through Functional Simulation. Prof. Chakraborty has held many invited, 3. Partitioning, Placement and Routing. visiting positions in reputed universities abroad. September 25-29, 2018 He is currently an associate editor of the IEEE (http://www.addt.iitkgp.ac.in/) Transactions on Circuits and Systems, Part I (2004-2007, 2010-2011) and part II (2008-2009),

Coordinator as a guest editor of the EURASIP JASP and a Prof. Mrityunjoy Chakraborty TPC member for many important IEEE ([email protected]..in) conferences. The teaching and research interests of Prof. Chakraborty are in digital and adaptive

Department of Electronics & Electrical signal processing, VLSI signal processing, wavelets and DSP for wireless communications, Communication Engineering in which he has guided several Ph.D. students Indian and published extensively. Prof. Chakraborty is a Kharagpur - 721302 fellow of the INAE.

Prof. Anindya Sundar Dhar obtained Registration Fees Bachelor of Engg. in Electronics and How to Apply: Telecomm.Engg. from Bengal Engg. College NO fee to be paid by teachers from TEQIP- (1987), followed by M.Tech. (1989) and III colleges towards registration, boarding • For Teachers and Students: Interested Ph.D. (1994) from IIT Kharagpur. He is candidates may please visit the webpage of and lodging. For others, the following rates presently a professor in Electronics and apply: IIT Kharagpur at http://iitkgp.ac.in/. At the Electrical Communication Engg., with bottom right, you will find “All Events”. teaching and research interests in VLSI  Rs.9,000.00 for teachers from Click on “Apply for CE Events” where architecture design for real time signal universities/ colleges. you will find the link to apply for various processing and communication. Prof. Dhar is  Rs.6,000.00 for students/research courses. It will also provide a link for a key person in the various VLSI related scholars. payment. activities in the institute and has been  Rs.15,000.00 for people from Industry, offering many challenging courses in this and R&D labs (DRDO, ISRO etc) • For Industry and Defense Research area over years, apart from carrying out Labs.: For profile creation, follow the guided, independent and sponsored research  Registration fee includes 18% GST, above procedure. For payment of in the above areas. registration fees, either pay online as access to all lectures and lab sessions, above, or, pay by sending a demand draft About IIT, Kharagpur course material and course banquet. drawn in favor of `CEP-STC, IIT

The IIT is located at Kharagpur, an important Kharagpur’, payable at Kharagpur. The  Accommodation will be arranged on draft may be sent to : railway town about 116 km west of . payment basis in institute guest houses

(subject to availability, on first-come-first- Prof. M. Chakraborty serve basis) Dept. of E. & E.C.E. IIT, Kharagpur 721302, WB Guest House Room Rents:

Technology Guest House: Contacts : D/B AC Rooms(Single occupancy) – Rs 1000. D/B AC Rooms(Double occupancy) – Rs 750 Prof. M. Chakraborty, Prof. A. S. Dhar (per person). Dept. of E. & E.C.E., IIT, Kharagpur 721302

Visveswaraya Guest House: Email : [email protected] D/B AC Rooms(Double occupancy) – Rs 300 [email protected] Kharagpur is well connected to almost all (per person). Phone : 03222-283512 (O), 283516 (O) part of the country by train. There are D/B Non AC Rooms(Double occupancy) – Rs 03222-283513 (R), 283517 (R) frequent train services from Howrah railway 150 (per person). station to Kharagpur. The institute is about 5 3 & 4 Bedded Non AC Rooms – Rs. 150 (per km away from Kharagpur station and can be person) reached by taxis, auto-rickshaws, cycle- rickshaws etc. IIT, Kharagpur is the oldest Sir Asutosh Mukherjee Guest House: IIT in the country and is the first among AC Rooms (Single Occupancy) – Rs. 500 equals in terms of diversity in curricular as well as extra-curricular activities.