EMA Currents Summer 2010 An Informative e-Newsletter from EMA Design Automation Newsletter

EMA Now Offers OrCAD/ FPGA Design Bundles

EMA Design Automation recently announced the availability of OrCAD/Aldec FPGA design and simulation bundles, which provide a complete flow for PCB and FPGA Creating a Toleranced Transfer design. “The OrCAD® product line provides a powerful set of tools Function in PSpice A/D for PCB design. With the recent By Andrew G. Bell, Senior Staff Engineer, ITT Geospatial Systems addition of the Cadence OrCAD FPGA System Planner, users now The use of toleranced models for worst-case properties (shown in Figure 2). For example, to have a solution to help integrate analysis (WCA) is a common practice to deter- implement the transfer function the FPGA onto their boards. mine whether a design will meet the specified Continued on page 4 > design requirements. Typically, parts will vary in value due to how they were manufactured, how they are used, and environmental conditions. the numerator would be set equal to “250” and Also in this issue: Simulation circuits that include these toleranced the denominator would be set equal to “s**2 + models can be used in tandem with the Monte 10*s+100” (note that the s2 term syntax is s2 = Adding Assertions to your Carlo feature in Cadence® PSpice® Advanced s**2 and not s^2). FPGA Design Process Analysis to determine the worst case performance Assertions are becoming the talk of a circuit. But the question arises: how do you One of the limitations with the “LAPLACE” transfer of the FPGA industry; in this article “tolerance” a transfer function? function model is that the model cannot be we answer your commonly asked toleranced. A toleranced model would allow the questions. designer to evaluate variations in DC gain and Page 3 > pole-zero locations. To build a toleranced transfer function model, the transfer function must be PLM for a Small Business translated into models which can be toleranced, Learn how Omnify’s PLM solution like resistors. The technique I propose for this is designed to help small and is to convert the transfer function into a simple medium sized businesses. mathematical simulation diagram where gain Page 5 > blocks and integrators are used to “solve the differential equation” (many years ago, analog Tech Tip computers were used to solve differential equations This articles provides some easy in much the same way, using Operational Ampli- ways to save yourself time using Figure 1: PSPICE LAPLACE Figure 2: Properties of Behavioral Model LAPLACE Model fiers which could be programmed as gain blocks, Cadence OrCAD PCB Editor. integrators, and summers). From there, the gain Page 8 > First, the PSpice A/D behavioral transfer function Continued on page 2 > …and Much More! model “LAPLACE” can be found in the ABM library (and is shown in Figure 1). Of course, higher order transfer functions can be implemented by modification of the “DENOM” and “NUM” model EMA Currents EMA Adds Future Continued from front cover VCVS. Then, the resistor value will be set equal to blocks can be replaced with a combination of a the desired gain and the resistor tolerance will be Electronics to voltage controlled current source (VCCS), a 1 set equal to the tolerance for the gain. To indepen- Component Data ohm parallel resistor, and a voltage controlled dently tolerance the pole location and the DC gain voltage source (vcvs). The resistor is then toler- of the transfer function, they must be split into two Management anced to match the amount of variability needed gain blocks of 628 rads/sec [R4] and 2.5 (V/V) Solution for each gain block. [R5]. The R4 resistor value and tolerance establish- es the value of the pole location and its variation. In EMA recently announced the To illustrate the proposed approach, consider the this case, the pole location is 100 Hz, or 628 rads/ addition of Future Electronics to following simple example. Suppose you want to sec. The R5 resistor value and tolerance establishes the list of component distribu- tolerance the following transfer function: the DC gain of the transfer function, or 2.5V/V. tors included in the new 4.0 ver- Y(s) 1570 sion of Component Information  ™ X (s) s  628 Portal (CIP), EMA’s component data management solution. First, the transfer function must be translated into a CIP provides design teams an simple mathematical form by multiplying the numer- automated method to manage ator and denominator by the inverse of the highest Figure 5: Fully Toleranced PSPICE Simulation Diagram

their electronic part data. It is order of the “s” term multiplied by U(s)/U(s): The pole location (determined by R4) has a ±10% 

® 

 tightly integrated with Cadence  tolerance, while the DC gain (determined by R5) has ® 1  1570  OrCAD Capture CIS, providing Y (s)  1570  s  s  Y (s) U(s) a ±5% tolerance. A 250 run Monte Carlo simulation access to component distributor         628 (using PSpice Advanced Analysis), which measures X (s) s 628  1 1   X (s) U(s) data directly within the OrCAD  s   s  the DC gain [MAX(V(VOUT3)/V(Vin))] and 3dB fre- design environment while im- quency [Cutoff_Lowpass_3dB(V(VOUT3)/V(VIN))], proving both data accuracy and Next, split the numerator and denominator into can be used to verify that the toleranced transfer operating efficiency. two transfer functions. The numerator transfer function produces the desired variations. As shown function, Y(s), can be rearranged as in both Figures 6 and 7, the variations are close to “Since its initial release in July of Y (s) 1570  1  1 the expected values: 2008, customer adoption of CIP  1570* ⇒Y(s)1570* *U (s) 15.0 U (s) s  s    continues to increase because     s customers see real value in an Percent of Samples and the denominator transfer function, U(s), can out-of-the-box data management 7.5 be rearranged as solution,” said Manny Marcano, president and CEO of EMA Design U (s) 1 1  ⇒ U (s)  X (s) − 628* *U (s)   0 Automation. “With CIP, engineers X (s)  628  s  85 90 100 110 115 1  Cutoff_Lowpass_3dB(V(VOUT3)/V(VIN)) are able to benefit from all the  s  n samples = 250 minimum = 89.7727 maximum = 109.668 n divisions = 10 10th %ile = 91.8983 3*sigma = 16.9473 mean = 99.8145 median = 99.7239 advantages that come with a sigma = 5.6491 90th %ile = 107.923 A simulation diagram, shown in Figure 3, can centralized part library without Figure 6: Pole Variation Histogram then be directly constructed from the two transfer having to become bogged down functions using gain blocks, a summer, and an 14.0 with designing and implement-

integrator. All these models can be found in the Percent of Samples ing a component database from 9.3 PSpice A/D ABM library. A PSpice A/D version of scratch.” the simulation diagram, shown in Figure 4, can also be constructed. 4.7 CIP 4.0 adds the ability to search

0 parametric data from the Future 2.3 2.4 2.5 2.6 2.7 MAX(V(VOUT3)/V(Vin))

Electronics part catalog to its n samples = 250 minimum = 2.37578 maximum = 2.62268 n divisions = 10 10th %ile = 2.40577 3*sigma = 0.206353 mean = 2.49943 median = 2.49952 existing list of supported sigma = 0.0687844 90th %ile = 2.59363 ® ® distributors, Digi-Key , Newark , Figure 7: DC Gain Variation Histogram and Premier Farnell®. Users Figure 3: Simulation Diagram have online access to these part This was a simple example of how to tolerance distributor databases, allowing a transfer function. This technique can easily be them to easily find available duplicated for higher order and more complicated parts that meet their perfor- transfer functions, with the added advantage that mance and financial require- both PSpice A/D frequency and time domain simu- ments directly from their Figure 4: PSpice Simulation Diagram lations can be analyzed. engineering desktop. Once the To tolerance the transfer function, each gain block desired part is found, For more information e-mail [email protected]. will be translated into a VCCS, a resistor, and a • Continued on page 3 > 2 Summer 2010

Continued from page 2 Adding Assertions to your FPGA CIP enables automatic download of the selected device parametric Design Process data directly into the component By Chris Banton, Product Marketing Manager, EMA Design Automation database, saving time and avoiding data entry errors that Assertions are quickly becoming a standard part These properties provide a way to speed up are common with manual of the FPGA design and verification process, verification through faster and more accurate bug methods. making the ability to create and use assertions a identification, while ensuring all aspects of the required skill-set for FPGA designers. But what design have been exercised appropriately. Going beyond distributor import exactly are assertions, and how can utilizing Remember that design verification really means the functionality, CIP provides them benefit yourself and your company? point at which you can declare the design “ready advanced component data for production”. This does not mean using asserts management capabilities. Our application engineers and account managers and covers will lead to less simulations (although Design teams can easily import receive questions on assertions on an almost it probably will). What it does do is allow you to external data into the component daily basis. Below are answers to the most com- get to that “ready for production” point faster and database, define user roles, and monly asked questions on the topic: with greater confidence that you really have fully track database changes to keep exercised the design (which is the real goal). everyone in synch as the design What are Assertions? progresses. With CIP, users are Before we answer this question, we have to in- Why Should I Bother With Assertions? provided with an automated troduce design properties first, as assertions are A major reason to begin using properties and methodology to implement, a subset of design properties. Design properties assertions, even when considering your current populate, and access their part are the formal way of specifying the desired or project list and workload, is the fact that your data while ensuring consistency undesired behavior of the design. This behavior design specification is already full of design and proper design practices are can be specified in many different ways, but properties; they are just expressed in plain Eng- being maintained. there are two methods that are lish. Adding assert and cover used the most frequently: the statements is a way of embed- For more information on CIP, assert statement and the cover Assertions can be very ding those design properties please visit www.ema-eda.com/ statement. If you are interest- beneficial in your day- from your specification in the currents/CIP, call 877.362.3321, ed in using assert statements actual design code in a format or e-mail [email protected]. (assertions), then you typically to-day design work by that your verification tools can will also want to employ cover understand. Since your verifica- statements as well. allowing you to catch tion tool can now interpret your bugs much faster and design specifications, it can Assert statements allow you now provide you direct data to embed monitors in your deliver the completed as to whether you are meet- design to verify that bad design much earlier. ing those high level design behavior never happens. If requirements. As a result, your unanticipated or bad behavior verification tools will be doing does occur, the monitor will be flagged, allowing the hard work for you. They will alert you when you to quickly locate the point of failure. Asser- some properties do not hold and tell you if your tions can be very beneficial in your day-to-day testbench tested all functional aspects of your design work by allowing you to catch bugs much design. faster and deliver the completed design much earlier. The larger the design you are working on, How do Assertions Work? the more visible the benefits of using assertions Many designers want to know how assertions and will be. coverage work before learning how to use them. Imagine adding a time dimension to the traditional Cover statements, on the other hand, allow you Boolean logic: instead of static values, it would to check that good behavior is exercised during have to operate on paths that represent sequences verification. Coverage improves your design quality of states of your design. Such extension of by making the verification process more thorough. Boolean logic exists and is called temporal logic. With coverage, the verification engineer is informed Properties, assertions, and coverage implement if certain behaviors of your design are not tested. It principles of temporal logic. Using this temporal is better to discover this during verification then logic, your simulator will then build internal state after manufacturing or delivering the design to Continued on page 4 > your customer. 3 EMA Currents

Continued from front cover Continued from page 3 How Much Money do I have to Spend to Start However, they are still lacking the machines, implementing behaviors described by Implementing Assertions? ability to design and verify the the properties you have defined and comparing Adding assertions to your design flow should FPGA itself,” said Manny Marcano, the state of those machines against the state of have a minimal impact on your budget. As president and CEO of EMA Design your design to evaluate assertions and coverage. mentioned, the training required to be able to Automation. “By including Aldec design using assertions is fairly minimal. What Active-HDL™ in these bundles, What Languages can be used to Express is needed are simulations tools that can interpret we have filled that gap, providing Properties, Assertions, and Coverage? the properties you are specifying so you can multi-language design entry and Another concern for designers considering the make your simulator design intent “aware”. This simulation for FPGA logic.” use of assertions is understanding what language powerful verification technique is not available in assertions can be used in. The dedicated language the standard vendor offerings. Aldec® Active-HDL™ The increased functionality and to express properties, assertions, and coverage is one high performance, mixed-language RTL performance available within for property-based verification is Property Specifi- Simulator that provides the ability to include today’s FPGAs have resulted in cation Language (PSL). These three items are also assertion and coverage capabilities into your a growing use of programmable a part of verification languages, such as System design environment. logic across all areas of elec- , OpenVera, or e. tronic design. While this has led We hope this compiled list of questions helps clarify more design teams to select an Which Assertion Language Should the world of assertions and design properties. FPGA based implementation, this a User Choose? Employing these techniques in your FPGA develop- additional functionality presents Any of the above languages can be used; it all ment environment can automate some of your most a rising design and verification boils down to personal preference. However, time consuming tasks, increasing your value as a challenge. The OrCAD/Aldec those designing in VHDL typically will find PSL designer and helping your company’s bottom line. FPGA Bundles provide the tools the most comfortable fit (a PSL subset is also needed to handle the increasing included in the new version VHDL IEEE Std 1076- For more information about Active-HDL and complexity of FPGA development. 2008), while Verilog users will gravitate toward FPGA verification, please visit www.ema-eda. Going beyond what typical vendor System Verilog (as it’s a natural extension of com/currents/aldec. For additional questions, supplied simulators can provide, Verilog). OpenVera and e tend to be used more in please contact EMA at 877-362-3321 info@ema- these bundles deliver a scalable Verilog environments as well. eda.com. • vendor independent platform to accommodate even the most Will I be able to Synthesize My Sources After complex mixed language FPGA Adding Assertions? verification tasks. In addition, the Some are hesitant to learn about assertions Aldec simulator provides a signifi- because they think they will not be able to cant speed increase over vendor synthesize their sources after adding assertions. supplied offerings and contains This is not true. However, some steps need to be no limitations on design size. taken to avoid problems during synthesis. Two “Bundling OrCAD and Aldec solu- common methods are: tions together provide a powerful • If you like to keep your assertions very close to FPGA solution to the mainstream the related HDL code, you can write them market at very competitive price directly in the VHDL or Verilog source. To points,” said David Rinehart, vice prevent the synthesis tool from reading them, you EMA Currents Content president at Aldec. can place them in specially marked comments or surround them with pragmas disabling synthesis Have you ever wanted to share some of your The OrCAD/Aldec FPGA Bundles experience with the engineering community? Do • If you like to keep them separate from the add FPGA design entry and simu- you have a topic you would really like to spout off related HDL code, simply place them in separate lation to OrCAD products at an in- about? How would you like to get paid to do just files and exclude those files from synthesis cremental cost starting at $1,756. that? Here is your chance to get your name in For more information, please visit front of thousands of engineers. EMA is looking How Much Time do I Need to Learn Assertions? www.ema-eda.com/currents/ for technical writers to contribute content for You need four to eight hours of guided training orcadaldec, call 877-362-3321, or publication. We are looking for articles, technical to learn everything you need to immediately start e-mail [email protected]. tips, short tutorials, and white papers on current using properties, assertions, and coverage in your technologies and techniques centered on any of designs. Attaining a high proficiency level requires the products and solutions sold and supported more time, but it is the breaking of old habits that by EMA. If this sounds like something you would really counts. The time spent once for learning will be interested in, please contact us at info@ema- pay back repeatedly in faster, better work. eda.com for all the details.

4 Summer 2010 Selecting a Product Lifecycle Management Power IC Model Library for Cadence (PLM) Solution that Addresses PSpice Technology Small Business Needs Adds TI Model Line- By Chuck Cimalore, Chief Technology Officer, Omnify up in 3.0 Release

Version 3.0 Power IC Model A small or medium sized business (SMB) that PLM solutions designed for the large enterprise Library™ has over 300 time- is looking to gain a competitive advantage often manage few developmental logistics, and domain simulation models for will often do so by improving their products instead tout the capability to encompass supply power electronic designs. Several and streamlining their operations. In these chain management, packaging, and post-devel- previously unavailable Texas situations, decision makers will look toward opment phases. For the smaller business looking Instruments (TI) models debut Product Lifecycle Management (PLM) technology to improve products, the process should begin in version 3.0, and future library to support these changes. By implementing with the engineers who face issues with data updates are anticipated to focus a Product Lifecycle Management system, management and communication with contract on many of TI’s newest and most companies can simplify and shorten each phase of manufacturers and external partners. popular components. the product development process. Selecting new technology is a challenge for any organization, but A common misconception is that large PLM The Power IC Model Library can be especially difficult for the SMB since most vendors with monolithic software systems are includes model netlists in PSpice software (particularly PLM software) is designed the only vendors that can address all product syntax, schematic symbols for to meet the needs of a large enterprise. development needs. In reality, many of these large both Cadence OrCAD® Capture systems, which have been designed with large and legacy schematics, and a set To begin the selection process, the SMB first organizations such as automobile manufacturers of example application circuits needs to understand what the PLM system in mind, include functionality that is irrelevant to for many of the IC models. The should accomplish for its organization. PLM the development needs of a small organization. models are compatible with OrCAD can provide key functionality to streamline each Further, the SMB (with its limited cash flow) is Capture version 16.x software. phase of a product’s lifecycle, from product paying for functionality that will likely never apply conception and design to manufacturing and to its product design process. “The Power IC Model Library for support, while improving communication across PSpice has models of parts that both internal and external constituencies. A Many smaller companies are beginning to look are simply not available from successful PLM implementation can help reduce toward implementing PLM software designed for any other EDA company,” said time-to-market and decrease product costs, and their market segment. In return, several large PLM Manny Marcano, President and also dramatically reduce waste and rework. Once and ERP vendors are attempting to “scale down” CEO of EMA Design Automation. a company determines that PLM software will their products to address the PLM needs of the “AEi Systems has proprietary address the challenges within their organization, SMB. Unfortunately, because these systems are relationships with nearly all of the question now becomes which PLM software typically built on their legacy foundations, their the top analog IC manufacturers. is best suited for their company. heredity does not allow them to adapt easily to These relationships provide the evolving needs of the smaller organization. unique access to the part Because the SMB operates with a smaller cash Moreover, these systems still require lengthy (and characteristics needed to produce flow, develops fewer products, and has a smaller costly) implementation phases. models with the accuracy our customer and supplier base as compared to a customers expect. large enterprise, the PLM system not only needs Implementation time and costs are critical factors to address all development challenges, but it needs for the SMB to consider when selecting a PLM sys- “This library makes the PSpice to be tailored to the distinct market segment. tem. SMBs cannot afford to reassign their valuable simulator even more compelling The increasing emphasis on outsourcing has resources to long PLM implementation projects. for engineers in the power supply dramatically changed the operational landscape of Most software designed for the large enterprises market. Many EDA vendors only the SMB, and must be a key consideration when have considerably lengthy implementation process- have access to information in the choosing the correct PLM system. Too often the es of more than six months. Alternatively, software manufacturer data sheets. This is SMB will select a PLM system that includes designed for the SMB has a quicker implementation simply not sufficient to create a broad functionality, but fails to drill down into the process and can have the company up and running precise model of a controller or daily challenges of engineers and developers to within days or weeks, depending upon the vendor regulator,” stated Charles embrace the need to share product data outside and level of integration with other systems. Hymowitz, Managing Director of the SMB’s four walls. Continued on page 6 > AEi Systems. “Data sheets Continued on page 6 >

5 EMA Currents

Continued from page 5 Continued from page 5 Selecting a PLM system can be a challenge if a company is not aware of the options available do not have the level of detail SMBs often have a competitive advantage within the marketplace. But if an organization required, so those companies over their larger competitors when it comes to starts the process by understanding what the tech- and modelers who rely solely on customer support and responsiveness. SMBs nology should address, and further understand the data sheet input will necessarily can react quicker to the evolving needs of their needs of their unique business and market seg- produce inferior, inaccurate customers and market, with intimate sup- ment, they can select a PLM tool that will allow the models.” port and new or enhanced products. This should also be an important consideration for the SMB organization to develop products more efficiently and ultimately transform their organization. AEi Systems and EMA are when choosing a PLM system. SMBs should keeping the price of version 3.0 consider such purchases to be a “partnership” The PLM solution from Omnify® helps manufac- of the Library the same as the with the vendor. For the SMB, their PLM system turers manage their product data from concept current version: $1,995, plus needs to be easy to use, have a low total cost of to obsolescence in a unified environment. Omnify yearly maintenance of $495. For ownership (TCO), and be from a vendor who is supplies a single, secure location to manage all more information on the Power IC dedicated to the success of that SMB. the essential information for designing, manu- Model Library, please visit www. facturing, and supporting your products, and ema-eda.com/currents/powerIC, Finally, companies frequently overlook the impor- enhances visibility into all aspects of product call 877.362.3321, or e-mail tance of employee buy-in when selecting a new development with features such as: [email protected]. PLM application. If it is necessary for employees to learn an encyclopedia of information before • Product Data Management using the software, the staff will be more resistant • Bill of Material (BOM) Management Switch Mode Power to using the tool and improving the product de- Supplies (SMPS) velopment process will be a greater challenge. In • Engineering Change Management order to see a quicker return on investment (ROI), • Document Management Workshop employees need a user-friendly PLM tool that • Project Management requires limited ramp-up-time. If employees feel EMA recently hosted a series comfortable using the software, they will be more • Quality/CAPA Management of SMPS workshops, which likely to use it for a range of purposes. Within a • Training Records Management showed how to use PSpice A/D smaller business, employees are expected to take • Compliance Management and Cadence PSpice Advanced on multiple functions, so it is likely they will need Analysis to design and analyze to understand many aspects of the software. If the For more information on Omnify, please visit switch mode power supplies. software is easy to learn and easy to use on a daily www.ema-eda.com/currents/omnify. • Attendees learned: basis, companies will see a greater and quicker transformation across the development process. • What is needed for SMPS simulation • What PSpice technology offers for SMPS design simulation Students Use OrCAD to Design Solar • Advantages of a unified simulation/implementation Powered Car environment By Joe Mignano, Marketing Specialist, EMA Design Automation You can request a free version of these workshop materials by The Coppell Solar Racing Team of Coppell filling out this form: High School in Coppell, Texas (just north of www.ema-eda.com/currents/ Dallas, Texas), is one academic institution smps. currently utilizing this program. They used the Cadence OrCAD PCB Design Suite for Academic Stay tuned for news on additional Institutions to design a single-passenger SMPS workshops taking place vehicle recharged only by solar power. throughout North America over the rest of this year. The solar electric vehicle designed by the team EMA established the OrCAD North America was entered in the 2010 Hunt-Winston School Academic Program to help colleges and Solar Car Challenge race. The goal of the race universities better prepare their future graduates was to teach high school students around the for the PCB design workplace. This program world how to build roadworthy solar cars. The provides industry-standard, commercial-grade race began on July 18, starting at Texas Motor software tools at reduced prices to accredited Continued on page 7 > colleges and universities for educational purposes. 6 Summer 2010 Continued from page 6 (one at 72 volts and one at 12 volts). The 12 volt Stay Connected with Speedway in the Dallas/Ft. Worth area and ending system was the auxiliary system that powered at the National Renewable Energy Laboratory in the fans, brake lights, flashers, and telemetry EMA and “Team Golden, Colorado. The team finished first in the equipment. The 72 volt system was the main OrCAD” Advanced Division, averaging 34.73 mph during power systems for the car, which included an the race. 1170 watt photovoltaic (solar) array, a 5 kilowatt battery array, the Maximum Power Point Trackers Several social media pages have There were several reasons why the Coppell (MPPT) that adjusted the voltages from the solar been launched that are aimed at Solar Racing Team chose OrCAD products to array to be compatible with the battery array, and keeping customers and others assist in their electrical design. The biggest a motor and controller. in the EDA and MCAD industries factor was an electrical team mentor’s positive informed of the latest news, events, experience with OrCAD products throughout his promotions, and technical tips. professional career. For Twitter users, one page has “I’ve used OrCAD PCB design technologies quite been created for those involved a bit in my career, and have always found them with EDA (www.twitter.com/ema_ easy to use,” said Gary Kidwell, an electrical team eda) and another has been created mentor. Kidwell currently works as a principal for those involved with MCAD member of the technical staff at Interphase Corp (www.twitter.com/ema_mcad). in Plano, Texas, and has worked for 30 years in These two pages provide a steady embedded computer technology. “What I like stream of information on all the best about using OrCad for this project is you EDA and MCAD technologies sold do not have to have a big library set up to begin and supported by EMA. using it. I thought that made it a good fit for the Figure 2: Image of Schematic for Solar Car high school kids who have zero experience with For YouTube users, there is a schematic capture, and don’t even really know Deciding on the correct software package was “Team OrCAD” YouTube Chan- what it is.” important to the team, but being able to acquire and install it efficiently was also important. nel (www.youtube.com/user/ “The students needed the OrCAD PCB Design “Our Account Manager was great,” said Michael TeamOrCAD) packed with all the Suite primarily to draw out and insert pages into Yabubovsky, lead engineering instructor for the latest OrCAD PCB design technol- the electrical design, such as fuses, switches, team and a pre-college engineering teacher at ogy movies from Cadence and motors, and connectors. As a result, I wanted to Coppell High School. “He helped us find the its worldwide channel partners pick out a tool they could learn fairly quickly and right product and assisted us as we purchased (including EMA). EMA’s YouTube have the basic components already built that they and installed it. The installation was a little tricky Channel (www.youtube.com/ could put in their schematic. Some of the parts because we were installing it on the school’s EMADesign­Automation) contains we have built ourselves, but most came with the computer and had to work in a pretty strict movies focused on all the technol- library that comes with OrCAD Capture,” said environment. The technical support provided by ogy sold and supported by EMA, Kidwell. “It was very easy to build a new part EMA was helpful, and we were able to install all as well as product integrations and within OrCAD Capture when we needed to.” our software without any issues.” enhanced capabilities provided to users of OrCAD technology. “After using this software from EMA, the students on the team have a much greater Lastly, there is now a Facebook understanding of the electrical system of a car page for OrCAD users. The “Team and how it works. Before we began using the OrCAD” Facebook page (www. OrCAD PCB Design Suite, they were not nearly facebook.com/TeamOrCAD) is de- as knowledgeable about the electrical system signed for OrCAD users to interact and how it really functioned. They only knew that with users and resellers across the it did. In previous competitions, they used the world. The page is continuously same setup that other teams have used without updated with movies, application knowing why,” said Yabubovsky. “Electronics is notes, and other useful information not an easy subject for most students, and these from Cadence and their worldwide students are finding it easier to understand after channel partners, including EMA. using the OrCAD software.” Figure 1: Image of Schematic for Solar Car Stay tuned for additional ways to The students liked the software and were able The schematics for the main and auxiliary power use social media to stay connected to get up to speed very quickly. The car was systems were completed at the end of March. In with EMA and “Team OrCAD”! designed to have two electrical systems running Continued on page 8 >

7 EMA Currents Summer 2010

EMA Now Offers Continued from page 7 the future, the Coppell Solar Racing Team plans Autodesk’s 2011 to use PSpice A/D and OrCAD PCB Editor to Digital Prototyping design custom interface boards to gain an even Software better understanding of electronic design. If you are part of an academic institution with EMA recently announced it will an electronic design program, please contact offer Autodesk’s latest 2D and 3D EMA at 877.362.3321 or [email protected] for design and engineering software more information how you can acquire OrCAD for manufacturers. products at an extremely affordable price. We are also interested in hearing about how other Digital Prototyping with academic institutions are using their OrCAD software gives products and what they are using them for. • manufacturers the ability to digitally Figure 3: Image of Schematic for Solar Car design, visualize, and simulate how a product will work under real world conditions before it is built. Digital Prototyping reduces Scripting Capability in OrCAD Capture reliance on physical prototypes, By , Inc. which helps reduce cost and speed time to market in highly competitive industries. As part of the Cadence 16.3 release, OrCAD provides a rich set of its own TCL commands Capture was enhanced to include support for Tcl/ that gives immense power to the users to interact “The EMA/Autodesk solution for scripting language. This capability provides with both Capture UI and database through the Digital Prototyping provides a immense power for users to interact with both scripting interface. revolutionary design experience the OrCAD Capture user interface and the design that offers significant benefits to database, and greatly extends a user’s ability to OrCAD Capture provides two sets of pre-defined engineers,” said Greg Roberts, develop custom applications and scripts for their Tcl commands: design environment. director of marketing at EMA. “The • User-action Tcl commands 2011 release of Autodesk products • Database Tcl commands unites direct manipulation with The desire for specialized productivity the more traditional parametric improvements and tool efficiency drives the need User-action Tcl Commands based workflows for a faster and for scripting and customization in a user’s design environment. With scripting and customization, User-action Tcl commands correspond to the easier to use interface. This release designers can apply automation to manual operations within the GUI performed by the allows designers and engineers to processes and complete projects faster, difficult user. Every user action that can be performed capture and embed engineering operations can be streamlined and custom in OrCAD Capture is now executable in the form and product knowledge directly features that do not exist natively can be created, of a Tcl command. These capabilities allow into virtual models, and it provides further enhancing and extending the OrCAD users to perform a large set of pre-defined and a new and easy-to-use product Capture environment. customized operations automatically for specific for creating compelling product needs. They also help designers when debugging documentation.” TCL Commands custom scripts, as they provide a definite The Tcl/Tk language provides an extensive set mechanism for step-by-step script re-creation. For more information on EMA’s of scripting functionality. The core functionality Autodesk offerings, please visit includes procedures and commands for data The Journaling option provides the facility to www.ema-eda.com/products/ manipulation, control constructs, mathematical capture, store, and later replay a customized autodesk.aspx, call 877.362.3321, expressions, file I/O routines, system calls, command or copy for use in an external script. or e-mail [email protected]. registry handling, GUI designing, and many more. This option is set through the TCL command The always growing additional packages of Tcl/Tk “SetOptionBool Journaling TRUE” and allows are just making almost everything possible that manual actions to display the corresponding can be done using any procedural language. TCL commands. All these TCL commands can be replayed individually. OrCAD Capture also The integrated TCL interpreter in OrCAD Capture automatically stores these commands in a TCL allows any commands from these Tcl/Tk packages script file that can be replayed to repeat the steps. to run seamlessly. On top of that, OrCAD Capture Continued on page 9 >

8 EMA Currents Summer 2010

Continued from page 8 set pPartInstsIter [$pPage NewPartInstsIter New On-Demand For example, if a user performed the following $lStatus] action: Demos set pInst [$pPartInstsIter NextPartInst Click the “Place Wire” icon and then draw a $lStatus] From beginners to advanced users, wire from coordinates 4.00, 1.00 to 6.00, 1.00 there are demos for every skill level # iterate over all parts the action is captured and stored as a Tcl command ready to be viewed at: www.ema- in the command window as “PlaceWire 4.00 1.00 while {$pInst!=$lNullObj} { eda.com/currents/multimedia. 6.00 1.00”. Executing this Tcl command would set lPropNameCStr [DboTclHelper_ have the exact same effect as placing the wire Signal Navigation and manually with the “Place Wire” command. sMakeCString “PartVersion”] Intersheet References in set lPropValueCStr [DboTclHelper_ OrCAD Capture sMakeCString “1.1”] Are you spending time trying to track signals that span multiple #add the property to part schematic pages? This presentation shows how OrCAD Capture allows set lStatus [$pInst SetEffectivePropStringValue you to navigate design connectivity $lPropNameCStr $lPropValueCStr] across multiple schematic pages set pInst [$pPartInstsIter NextPartInst quickly and effectively. www.ema- $lStatus] eda.com/currents/movie1. } Autowiring in OrCAD Capture delete_DboPagePartInstsIter $pPartInstsIter Spending too much time manually defining connectivity in your sche- $lStatus -delete Figure 1: User Action TCL Command matics? This presentation dem- } onstrates how unique automated Database Tcl Commands wiring capabilities in OrCAD Capture OrCAD Capture also provides a rich set of Tcl These database Tcl commands can be run within free you from tedious point and click commands that allow users to interact with design the OrCAD Capture command window as well methodology, allowing you to focus and library databases directly. These database as in a standalone Tcl shell. This window allows on engineering and adding value to Tcl commands allow for both querying and users to modify their custom Tcl procedures as your product. www.ema-eda.com/ manipulation of the design and library objects. All needed within a session. The modified script currents/movie2. types of design and library objects (schematics, can be sourced again in the command window pages, parts, pins, nets, wires, globals, off-pages, to display the changed behavior. Any Tcl-aware Automate your New Part ports, library packages, graphic objects, etc.) application can also use these commands Introduction Process with OrCAD and their properties can be queried, iterated, and directly within its process space. Tcl commands CIP provides OrCAD Capture CIS manipulated using Tcl commands. are available to get active sessions, create new users instant access to millions sessions, get active design/schematic/pages, of orderable parts in the Future The database Tcl commands provide the same open any design or library in the session, and Electronics, Newark, Digi-Key, and power as OrCAD Capture software design kit then perform the iterations to retrieve and Premier Farnell databases, with de- application programming interfaces (SDK APIs). manipulate the desired set of database objects. vice parameters, RoHS compliance Due to their ability to directly interact with the status, cost, quantity on hand, and database objects, engineering organizations and Automatic Script Loading and Procedure Calls mechanical dimensions. This demon- end users can build large sets of customized The scripting framework in OrCAD Capture stration will highlight how easy it is design verification and manipulation procedures provides various mechanisms for automatic to download part distributor informa- using these Tcl commands. script loading and automatic calling of Tcl tion directly into OrCAD Capture CIS. procedures. This framework allows users to have You also will discover how CIP can As an example, if a user wants to simultaneously customized sets of operations and behaviors help automate new part requests and manipulate all the parts on a schematic page and automatically available when starting OrCAD streamline the part selection process, add a custom property “PartVersion” with a value Capture and for various types of trigger events. If how you can get better control of of “1.1”, the following custom Tcl procedure can a user wants to always place a set of custom title the CIS database, and how to ensure be utilized for this: blocks on a new page, they can use this feature a more reliable and shorter design to run a custom Tcl procedure automatically cycle. www.ema-eda.com/currents/ proc addPropertyToAllPartsOnPage { pPage } { whenever a new page is created. movie3. set lNullObj NULL Continued on page 10 > set lStatus [DboState]

9 EMA Currents Summer 2010

EDA Industry Continued from page 9 • Run OrCAD Capture with a replay script: Framework examples include: OrCAD Capture can be started from the com- Focus Shifts to mand line along with a replay Tcl script file. • Automatic loading of scripts at startup: All the user actions mentioned in the script file Integration and OrCAD Capture automatically sources capture/ automatically run as OrCAD Capture starts. Profitability tclscripts\capinit.tcl file at startup. Also, all Tcl files present inside the capture\tclscripts\capAutoLoad Inter-Process Communication with folder are sourced automatically during startup. Today, systems and semiconductor OrCAD Capture using Tcl Using this method, users can make custom scripts companies are undergoing a OrCAD Capture provides a sample Tcl package and procedures available by default. disruptive transformation so named “capCommServer” that can be used as a profound that even the best-known • Automatic calling of TCL procedures on event bidirectional communication mechanism between companies will be impacted. The triggers: OrCAD Capture provides Tcl procedure OrCAD Capture and any other standard Tcl-aware EDA industry now stands at a hooks to execute scripts upon event triggers. The application. Users can write custom client and crossroads where it also must custom Tcl callback procedure is registered using server-end Tcl procedures and use this mechanism change in order to continue as a the “RegisterAction” Tcl command. Any number as a framework for establishing bidirectional successful, independent business. of Tcl callback procedures can be registered communication between the two applications. Any Without that change, EDA will against an event. They all are called in sequence of the user-action or database level Tcl commands become a fragmented industry when the particular event is triggered. can be run inside OrCAD Capture from other offering suboptimal, poorly To place a set of custom title blocks on a applications using this approach. targeted solutions that fail to solve new page, the addition could call a custom customer problems. As a result, Tcl procedure ‘AddPageCustomTitleblocks’ Tcl/Tk Setup the huge leap forward provided automatically at every new page creation. OrCAD Capture TCL/TK framework works with by the electronics revolution will The registration of the Tcl procedure would the Tcl/Tk libraries version 8.4, which is part of come to a standstill. The result? be performed with the following command: the standard 16.3 installation. A squandered opportunity for technology innovation, and a RegisterAction“_cdnOrOnNewSchematicPage” Additionally, application developers can use diminished contribution by the “capTrue” “” “AddPageCustomTitleblocks” “PM” advanced Tcl features or Tk GUI extensions electronics industry to re-build the where (ttk, BWidgets, etc.) to develop their custom applications. To do this, developers are advised global economy. New page creation hook unique name = to download and install ActiveState ActiveTCL _cdnOrOnNewSchematicPage The disruptive transformation we version 8.4, which is available for free at www. are speaking of is not about EDA Custom TCL procedure to call on new page activestate.com/activetcl/downloads. developing new design tools. It creation = AddPageCustomTitleblocks is not about new methodologies. • Adding a custom menu within the Accessory Details of the setup process are provided in the It is not about the functional menu: Tcl customization allows users to add scripting interface help document that comes verification crisis, or the move custom menus within the Accessories menu with the download. TCL/Tk specific information in to electronic system level (ESL) through the command “AddAccessoryMenu”. this document applies to OrCAD Capture versions design, or any of the issues that These commands can be used with Register 16.3-S013 and later. have dominated discussions about Action hooks “_cdnCapTclAddPageCustom EDA to date. It is about something Menu” and “_cdnCapTclAddDesignCustom Samples and Application Information much larger. It begins with a shift Menu” to automatically create these menus A detailed application note along with several from design creation to integration when OrCAD Capture is started. scripting samples is available at www.ema-eda. com/currents/tcltk. For more information on Tck/ in the electronic systems industry, For example, to add a custom menu “Capture and results in a new focus on Tk scripting capabilities, please contact EMA at Communication Server” with submenus “Start” and 877.362.3321 or e-mail us at [email protected]. • profitability. This realization, in “Stop” as well as their associated Tcl callback pro- turn, opens the way to EDA360, cedures, the following Tcl command would be used: a new vision for what the EDA industry can become. AddAccessoryMenu “Capture Communication Server” “Start” “::capCommServer::StartServer” To tell the story, however, we must AddAccessoryMenu “Capture Communication take a step back for a moment Server” “Stop” “::capCommServer::StopServer” to where everything starts—the electronics consumer.

To read the rest of this article, please visit www.cadence.com/ eda360. Figure 2: Custom Menus 10 EMA Currents Summer 2010 PSpice Technology to be Used by STMicroelectronics

Cadence announced in April that STMicroelectronics, a global leader in integrated circuits for communi- cations, consumer, computer, auto- motive, and industrial applications, has selected PSpice technology to provide simulation capabilities to its customers to evaluate the OrCAD PCB Editor Time Saving Tips company’s analog and power IC’s. By Bill Zembek, Technical Support Specialist, EMA Design Automation Customers will be able to run a free version of PSpice technology, In today’s design industry, resources are limited To directly change the active layer, use the a robust and widely used platform, and time schedules are more critical than ever. following shortcuts: within specific circuit testbenches. Your PCB tool needs to keep pace by making • To make the top layer the active later, hit “1” every keystroke count. OrCAD PCB Editor after implementing this code: funckey 1 options “Recommending PSpice technology provides a very flexible environment to help with subclass TOP to our customers is a great way to design efficiency and productivity. enable them to test-drive our analog • To make 2nd layer the active layer, hit “2” and power IC products,” said Car- Once you have mastered the basics of OrCAD after implementing this code: funckey 2 options subclass SIGNAL_2 melo Papa, corporate vice president PCB Editor, there are several ways to take and general manager of STMicro- full advantage of this You can program function keys electronics’ Industrial and Multi- technology’s functionality. OrCAD PCB Editor Segment Sector (IMS). “Evaluating One such way is the use of for as many layers as are on your board. Another method to our chips with Cadence software will “hot key” shortcuts. These provides a very flexible strengthen our customers’ confi- shortcuts allow you to get change the active subclass is by dence in receiving the highest qual- away from using the mouse environment to help clicking the right mouse button ity ICs needed for their success.” to perform tedious tasks that with design efficiency (RMB): can be performed quicker “We are honored and excited by with the use of the keyboard. and productivity. RMB > Quick Utilities > Change Active Subclass STMicroelectronics recommending that their customers use PSpice Below are a few tasks made easier through the technology in an integrated evalu- use of “hot key” shortcuts. To begin using these Adding Vias ation environment,” said Charlie shortcuts, simply type the lines of code indicated Adding a via to your design has traditionally been Giorgetti, corporate vice president below into your local env file. done with a double click of the left mouse button (LMB). However, the use of the space bar can of product marketing at Cadence Change Active/Alternate Layers save you thousands of mouse clicks per year. To Design Systems. “STMicroelec- You can increment or decrement the active or set up this functionality in OrCAD PCB Editor, add tronics’ decision to recommend alternate layer in your PCB design by using the this shortcut to your local env file: PSpice software confirms that our following shortcuts: global PSpice simulation environ- funckey “ “ “pop bbdrill -cursor” ment is the first choice for today’s • To increment the active subclass, hit the “+” analog design engineers.” character after implementing this code: The spacebar entry is represented by “ “. Other funckey + subclass -+ keys can be assigned as a shortcut, but the space The first product families that can • To decrement the active subclass, hit the “-” bar is easy to use without having to look down at deploy PSpice technology will be character after implementing your keyboard. DC-DC converters and ViPERTM. this code: funckey - subclass -- All industrial and multi-segment Add Connect and Adding a Vertex sector analog and power IC prod- • To increment the alternative subclass, hit the Instead of using the left mouse button (LMB) to “a” character after implementing this code: ucts will eventually be included. add a vertex point during Add Connect, consider funckey a altsubclass -+ For more information, please hitting the “x” key every time you want to add a visit www.ema-eda.com/currents/ Continued on page 12> stmicro

11 EMA Currents Summer 2010

Continued from page 11 • To snap to the via element, hit “v” vertex during routing. Below is the code to add to after implementing this code: funckey v your env file for this shortcut: “prepopup;pop dyn_option_select ‘Snap pick to@:@Via’” funckey x “pick_to_grid -cursor” Assign Commands to the Middle Mouse Wheel Deleting Elements The Button command can be used to assign the I use this function key more than any other one. Middle Mouse Wheel scroll commands. This Just pass your cursor over a cline, segment, via, command works with SHIFT, CONTROL and text, or shape and hit “d” to delete it. No click of SHIFT-CONTROL combinations while scrolling the mouse required! Here is the code for your with the mouse in some cases: Cadence OrCAD env file: • To move the middle mouse wheel up a Classroom Training funckey d “prepopup; pop dyn_option_select subclass using the shift button, implement @:@Delete” this code: button Swheel_up subclass -+ Increase your PCB design productivity by attending our • To move the middle mouse wheel down an Rotating and Mirroring a Component in-depth, hands-on classroom alternative subclass using the shift button, You can hit “r” to rotate a component during implement this code: button Swheel_down training sessions. All our class- movement. Here is the code for your env file: altsubclass -+ room courses are taught by professional instructors with • To scroll up with the middle mouse wheel funckey r iangle 90 years of training and applica- while pressing the control key, implement this tion experience. Learn more at code: button Cwheel_up “roam y -$roamInc” Hit “m” to mirror a component during htpp://www.ema-eda.com/cur- movement. Here is the code for your env file: • To scroll down with the middle mouse wheel rents/training. while pressing the control key, implement this funckey m “pop mirror” code: button Cwheel_down “roam y $roamInc” EMA classroom training is coming • To scroll up with the middle mouse wheel soon to a city near you… Snapping while pressing the shift and control keys, Seattle, WA While moving an object, you can use a shortcut implement this code: button SCwheel_up “roam September 13 – September 24 as opposed to your mouse to snap to various x -$roamInc” elements: • To scroll down with the middle mouse wheel Ottawa, ON • To snap to the figure element, hit “f” after while pressing the shift and control keys, September 20 – September 24 implementing this code: funckey f “prepopup; implement this code: button SCwheel_down pop dyn_option_select ‘Snap pick to@:@ “roam x $roamInc” Sunnyvale, CA Figure’” September 27 - October 8 • To snap to the intersection element, hit Please contact EMA Technical Support at 877.362.3321 or [email protected] to St. Paul, MN “i” after implementing this code: funckey i learn more about these and other time saving September 27 - October 8 “prepopup;pop dyn_option_select ‘Snap pick to@:@Intersection’” ideas in OrCAD PCB Editor. • • To snap to the arc/circle center element, hit “c” after implementing this code: funckey c “prepopup;pop dyn_option_select ‘Snap pick to@:@Arc/Circle Center’” EMA Design Automation, Inc. 225 Tech Park Drive Rochester, New York 14623 Phone: 585.334.6001 Toll Free: 877.362.3321 Fax: 585.334.6693 eMail: [email protected] Web: www.ema-eda.com

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