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Tero Säntti a Co-Processor Approach for Efficient Java Tero S¨antti A Co-Processor Approach for Efficient Java Execution in Embedded Systems TUCS Dissertations No 108, September 2008 A Co-Processor Approach for Efficient Java Execution in Embedded Systems Tero S¨antti To be presented, with the permission of the Faculty of Mathematics and Natural Sciences of the University of Turku, for public criticism in Auditorium Alpha on November 10, 2008, at 12 noon. University of Turku Department of Information Technology University of Turku, FI-20014 Turku, Finland 2008 Supervisors Adjunct professor, Ph.D. Juha Plosila Department of Information Technology University of Turku FI-20014 Turku Finland D.Sc. (Tech) Seppo Virtanen Department of Information Technology University of Turku FI-20014 Turku Finland Reviewers Professor Dake Liu Department of Electrical Engineering University of Link¨oping S-58183 Link¨oping Sweden Professor Timo D. H¨am¨al¨ainen Department of Computer Systems Tampere University of Technology FI-33101 Tampere Finland Opponent Professor Jan Madsen Department of Informatics and Mathematical Modeling Technical University of Denmark DK-2800 Lyngby Denmark ISBN 978-952-12-2155-2 ISSN 1239-1883 Abstract This thesis deals with a hardware accelerated Java virtual machine, named REALJava. The REALJava virtual machine is targeted for resource con- strained embedded systems. The goal is to attain increased computational performance with reduced power consumption. While these objectives are often seen as trade-offs, in this context both of them can be attained simulta- neously by using dedicated hardware. The target level of the computational performance of the REALJava virtual machine is initially set to be as fast as the currently available full custom ASIC Java processors. As a secondary goal all of the components of the virtual machine are designed so that the resulting system can be scaled to support multiple co-processor cores. The virtual machine is designed using the hardware/software co-design paradigm. The partitioning between the two domains is flexible, allowing customizations to the resulting system, for instance the floating point sup- port can be omitted from the hardware in order to decrease the size of the co-processor core. The communication between the hardware and the software domains is encapsulated into modules. This allows the REALJava virtual machine to be easily integrated into any system, simply by redesign- ing the communication modules. Besides the virtual machine and the re- lated co-processor architecture, several performance enhancing techniques are presented. These include techniques related to instruction folding, stack handling, method invocation, constant loading and control in time domain. The REALJava virtual machine is prototyped using three different FPGA platforms. The original pipeline structure is modified to suit the FPGA envi- ronment. The performance of the resulting Java virtual machine is evaluated against existing Java solutions in the embedded systems field. The results show that the goals are attained, both in terms of computational perfor- mance and power consumption. Especially the computational performance is evaluated thoroughly, and the results show that the REALJava is more than twice as fast as the fastest full custom ASIC Java processor. In addition to standard Java virtual machine benchmarks, several new Java applications are designed to both verify the results and broaden the spectrum of the tests. i ii Acknowledgements It gives me great pleasure to be able to express my gratitude to the individ- uals and institutions that have influenced and enabled the research in this thesis. First and foremost, I would like to thank my supervisor Ph.D. Juha Plosila for his continuous support, guidance and inspiration during the work leading up to this thesis. I am also very grateful to D.Sc. (Tech) Seppo Virta- nen, who examined this thesis thoroughly and provided excellent comments. I also wish to thank professors Dake Liu from University of Link¨oping and Timo D. H¨am¨al¨ainen from Tampere University of Technology for their detailed reviews of this thesis and for providing insightful comments and sug- gestions for improvement. Their recommendations and suggestions raised the quality and the clarity of the final manuscript. I gratefully acknowledge the funding from the late Department of Ap- plied Physics and the Department of Information Technology during the first part of my postgraduate studies. The second part was funded by the “Teknologiateollisuuden 100-vuotiss¨a¨ati¨o” -foundation of the Federation of Finnish Technology Industries, for which I am very grateful. The funding from the foundation allowed me to concentrate on the research and bring the work to a conclusion. I would also like to thank the Turku Centre for Computer Science (TUCS) for their financial support. I wish to thank all the colleagues and co-workers in the Department. Especially Joonas Tyystj¨arvi is thanked for participating in the research and co-authoring several publications. I also wish to thank professors Jouni Isoaho, Ari Paasio and Johan Lilius (from Abo˚ Akademi) for all the dis- cussions related to the research in this thesis and other topics as well. The legendary group of people from the room 013 should also be mentioned. It has been a pleasure and a privilege to share the journey from a bunch of wannabe scientists to something more substantial with each of you. The office staff and the technical personnel deserve a special acknowledgement for all the help and support in their respective fields throughout the years. iii My friends have also been supporting and understanding during my doc- toral studies. Especially all the wonderful people from Hayashi and Three Beers are thanked for listening to my ramblings about the research, and for providing occasional breaks from the work. The multidisciplinary discus- sions on all topics gave me much needed perspective at times. I am grateful to my mother Merja S¨antti and my brother Kari S¨antti for their support and encouragement over the years. I also wish I could have shared these moments with my late father Jari S¨antti, who always encour- aged me to do my best at whatever I choose to start. Remembering his advice helped me in the darkest times during this work. My final, most personal and sincerest thanks go to Johanna Tuominen. You have always kept the faith in me and my research. Your love and sup- port in all areas of life have been the cornerstones of my life. Turku, September 2008 Tero S¨antti iv Contents 1 Introduction 1 1.1 Objectives............................. 3 1.2 List of Publications and Research Contributions . 5 1.3 OverviewoftheThesis. .. .. .. .. .. .. 9 1.4 RelatedWork........................... 9 1.4.1 Software Solutions . 10 1.4.2 Hardware Solutions . 10 1.4.3 Co-Designed Java Virtual Machine . 12 1.4.4 History and Current Trends . 13 2 Java Virtual Machine Technology 15 2.1 Advantages of Virtual Machines . 15 2.2 Motivation for Choosing Java . 16 2.3 JavaLanguage .......................... 17 2.4 JavaVariants ........................... 18 2.4.1 Configurations and Profiles in J2ME . 19 2.4.2 History .......................... 21 2.5 Generic Java Virtual Machine Architecture . 22 2.5.1 Lifespan of the Java Virtual Machine . 22 2.5.2 Data Placement Inside a JVM . 23 2.5.3 Bytecode Instruction Set . 25 2.5.4 JavaMethods....................... 27 2.5.5 Classes, Class Files and Class Loading . 28 2.5.6 Exception Handling . 31 2.6 Java Virtual Machine Implementations . 32 2.6.1 Using Hardware Systems in Virtual Machine Imple- mentations ........................ 36 2.7 ChapterSummary ........................ 38 3 Conceptual Model of the REALJava Virtual Machine 39 3.1 ExecutionModel ......................... 39 3.1.1 Other Execution Models for Co-Processors . 40 v 3.2 Partitioning............................ 41 3.3 StructureoftheCo-Processor . 42 3.3.1 General Purpose Processor Pipeline Architecture . 42 3.3.2 The Modified Architecture for the Java Co-Processor . 43 3.3.3 SharedResources. 45 3.3.4 InstructionPreprocessing . 46 3.3.5 Operand Access, ALU and Result Storing . 47 3.3.6 Caches, Stack and Registers . 48 3.3.7 Details of Instruction Folding . 49 3.4 SoftwarePartition .. .. .. .. .. .. .. 53 3.4.1 Virtual Machine Software . 54 3.4.2 Bytecode Execution and Method Invocation and Return 56 3.4.3 Co-Processor Allocation with Multithreading . 58 3.4.4 Co-Processor Memory Management . 60 3.4.5 Garbage Collection . 61 3.4.6 Porting the Software . 62 3.5 DataStructures.......................... 63 3.5.1 Bytecode Storage Model . 63 3.5.2 StackLayout ....................... 64 3.5.3 Heap Management . 65 3.5.4 Other Data Structures . 66 3.6 ChapterSummary ........................ 67 4 Prototyping the REALJava Virtual Machine 69 4.1 Major Changes from the Conceptual Model to the FPGA Implementation.......................... 69 4.1.1 Changes in the SW Partition . 70 4.2 Description of the FPGA Platforms . 71 4.2.1 XESS XSA-3S1000 . 71 4.2.2 Xilinx ML310 and ML410 . 73 4.3 FPGA Techniques and Tools Used . 78 4.3.1 Size of the Co-Processor Core . 79 4.4 Communication.......................... 82 4.4.1 XESS Board with Parallel Port Communication . 83 4.4.2 ML310 and ML410 with PLB Communication . 84 4.4.3 Internal Interface . 85 4.5 Memory Areas of the Prototypes . 86 4.6 ChapterSummary ........................ 88 5 Performance Increasing Techniques 89 5.1 Identifying the Performance Hindrances . 90 5.2 StackHandling .......................... 92 5.3 PipelineStructure .. .. .. .. .. .. .. 96 vi 5.4 Partial Instruction Folding . 98 5.5 MethodInvocation .. .. .. .. .. .. .. 99 5.5.1 Results ..........................104 5.5.2 Additional Benefits . 107 5.6 ConstantCaches . .. .. .. .. .. .. .. 109 5.7 TimeControl ...........................110 5.8 Additional Registers and Helper Addresses . 111 5.9 ImpactoftheTechniques . 118 5.10 Multicore Approach . 121 5.11 ChapterSummary . 122 6 Performance Evaluation 123 6.1 Overview of the Reference Systems . 123 6.2 Descriptions of the Benchmarks . 125 6.3 Results...............................128 6.4 MemoryAccesses.
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