RICHARD H. MAURER, KEDONG CHAO, C. BRENT BARGERON, RICHARD C. BENSON, and ELBERTNHAN

RELIABILITY OF GALLIUM ARSENIDE DEVICES

Reliability qualification tests for space applications were carried out on several types of gallium arsenide transistors and process control monitors. A variability in the maturity and quality of the GaAs devices was determined. Failure analyses indicated that both subsurface defects and arsenic on device surfaces can lead to long-term burnout.

INTRODUCTION

The use of gallium arsenide (GaAs) transistors and A integrated circuits for space and military applications has Ohmic greatly expanded over the past few years. The main contact reasons for the exploitation of this compound semicon­ ductor are that GaAs devices can operate at higher fre­ quencies and have greater radiation hardness than their silicon counterparts. At this time, however, silicon tech­ nology still has a considerable lead in the area of reli­ Semi-insulating GaAs ability. The basis for the silicon's superior rei iability is inherent and lies in the nature of its oxide, which can be grown under controlled conditions and has better protec­ B Ohmic tive properties. Unfortunately, the oxide of GaAs does contact not exhibit these qualities. The purpose of our reliability studies of commercially available GaAs signal transistors is to assess indepen­ dently their state of maturity for use in spaceborne radio frequency (RF) systems such as X-band transmitters and S-band beacon receivers. Specifically, in this article we report our evalu ations of high-electron-mobility transis­ Epitaxial buffer layer tors (HEMT'S), signal metal-semiconductor field-effect transistors (MESFET'S), power MESFET'S, and a digital Semi-insulating GaAs process control monitoring device. To assist the reader in understanding GaAs technol­ ogy, we will first briefly desclibe the basic field-effect Figure 1. Cross-sectional views showing the evolution of GaAs transistors (FET s) and then outline a few of their failure metal-semiconductor field-effect transistor (MESFET) technology. mechanisms. We will then discuss the results of the A. The traditional MESFET is a planar, direct ion-implanted GaAs device. B. The newly developed MESFET has n+ and n- epitaxial reliability testing and failure analysis. The article con­ layers and a recessed gate structure using a self-aligned process. cludes wi th a summary of our findings.

MESFET STRUCTURE GaAs substrate and the active layer. A recessed gate The traditional MESFET is a planar, direct ion-implant­ structure, which results from localized n+ epitaxial con­ ed GaAs device (Fig. lA). A newly developed MESFET tact layers for both drain and source pads, reduces the has n+ and n - epitaxial layers and a recessed gate struc­ source resistance and improves noise figures. The heavily ture using a self-aligned process (Fig. IB). The new doped n+ epitaxial layers enhance CUlTent transport MESFET contains a buffer layer between a thin active n­ through the metal-semiconductor interface by reducing epitaxial layer and a semi-insulating GaAs substrate. the drain-to-source resistance. The most popular ohmic The thickness of the n - epitaxial layer is one thousand contact to GaAs is Au-GeNi. A Au-Ge mixture is evap­ to a few thousand angstroms, and it has a carrier con­ orated from a eutectic film (88% Au, 12% Ge by weight), 17 3 centration of about 2 X 10 cm- • The thickness of the and a Ni layer is subsequently deposited to improve the highly re istive buffer layer is 3 to 5 #-tm, and it has a melting of the eutectic film and increase the solubility of 14 3 carrier concentration of less than 1 X 10 cm- . The GaAs, thereby maintaining a smooth morphology. The buffer layer confines calTiers to the active region and gate length is less than 1 #-tm for higher gain, lower noise thereby acts as a buffer between the semi-insulating figure, and better frequency response. Most manufactur-

Johns Hopkins A PL Technical Digesl. liollime 13. Number 3 (1992) 407 R. H. Maurer el al. ers of MESFET'S use the self-aligned gate process to con­ tance ohmic contact to the Ni-Au-Ge source and drain trol source-to-gate and drain-to-gate spacing. Aluminum metallizations and prevents the AIGaAs layers from ox­ is the most common gate metal; to achieve higher power idizing. The n-GaAs contact layer, n-AlrGal _,A s graded handling, however, refractory metals such as Ti-Pt are layer, and n-Alo.3 Gao.7As constant-composition layer are being used as additives to AI. The gate metal should have all doped to 2 X lOi S cm- 3 and have a combined total characteristics such as high conductivity, good adhesion, thickness of 400 A. The 50-A undoped Al o.3 Gao.7 As and poor interdiffusion properties with GaAs up to 400°C. spacer layers separate the ionized donor atom in the The MESFET is the most common GaAs transistor tech­ constant composition layer from the two-dimensional nology because of its simple planar structure, ease of electron gas confined at the conduction band di scontinu­ manufacturing, and high yield. Most GaAs foundries use ity at the spacer layer/undoped GaAs interface. The two­ MESFET structures for either digital or analog applications. dimensional electron gas has an electron mobility of 6000 The failure modes observed to date for GaAs transistors cm2/(yo·s) at room temperature; this is the quasi-ballistic have predominantly been wearout mechanisms caused by transport "highway" that is unique to HEMT'S. The un­ metal-GaAs interdiffusion. 1 Dielectric failures have not doped GaAs buffer layer also acts as a barrier to the been observed frequently, and failure of the substrate diffusion of impurities and defects from the semi-insu­ material is not prominent because of the semi-insulating lating GaAs substrate during the molecular beam epitaxy properties of GaAs. In GaAs MESFET'S with Au or Al growth and confines carriers to the channel region. Other metallization, the major modes offailure caused by metal­ features of conventional HEMT'S include a closely spaced GaAs interdiffusion are (1 ) ohmic contact degradation structure between the source and the gate to reduce the caused by interdiffusion to the source or drain of FET resistance of the two-dimensional electron gas layer, re­ structures; (2) Schottky gate degradation caused by inter­ duced gate-fringing capacitance, and a spatial parasitic diffusion to the channel of FET structures;2,3 and (3) elec­ resistance.9 The p+-GaAs layer was absent in devices tromigration, usually with Al metallization, on surfaces. from other manufacturers, and the gate consisted of a A combination of the first two failure modes has been conventional Schottky diode. shown to be responsible for gate-to-drain and gate-to­ When heterojunction structures such as HEMT'S are source shorts in GaAs power MESFET'S.4 Schottky gate evaluated, one must add the following to the previously degradation is sometimes observed as channel compen­ mentioned MESFET failure modes: interdiffusion between sation or the "sinking gate" phenomenons by combining semiconductor layers, which can destroy the stability of electrical measurements with failure analysis. the desired heterostructure. As discussed earlier, the caus­ In addition to the three failure modes just mentioned, es of the reliability problems are the lack of a stable oxide two kinds of catastrophic failure6,7 can occur with power structure for compound semiconductors such as GaAs MESFET'S: (1) instantaneous burnout, which involves the and the presence of possibly unstable heterojunctions in thermal runaway of the buffer or substrate, and (2) long­ GaAs semiconductor structures. (For a more detailed li st term bumout, in which Ga is oxidized and As is reduced, of failure mechanisms of these compound semiconduc­ eventually leading to the conduction of large currents and tors, see Table \.) melting of the device. DEVICE EY ALUATION HEMT STRUCTURE We evaluated MESFET'S, HEMT'S, and digital process A cross section of a typical HEMT grown by molecular control monitors from electrical measurements, thermal beam epitaxy is shown in Figure 2. The top layer of 200 characterization, and the application of environmental A of highly doped 2 X 10 19 cm- 3 p+-GaAs is confined stresses (thermal shock and accelerated aging). To date, to the gate region and serves to raise the surface potential shelf life (no bias), DC, and RF bias aging tests have been of the gate to allow for higher doping levels in the lower performed on GaAs devices and structures. The present n - layers. This increased surface potential can increase conventional approach is to use DC bias conditions for the aspect ratio of the device to avoid short-channel ef­ small-signal devices in which the currents are small and fects.s The n-GaAs contact layer allows for a low-resis- the consequent heating effects are likewise small , where-

Source Gate Drain

p+-GaAs N =2 x 10 19 cm- 3, 200 A A Figure 2. Cross-sectional view of a typi­ n-GaAs cal high-electron-mobility transistor n-Al Ga s x 1_xA 18 3 grown by molecular beam epitaxy. NAis ~~ __...l.-_--1-_ --;;j/;~~~6:'i!--_ (graded) No = 2 x 10 cm- , 400 A the acceptor dopant level, and NDis the donor dopant level. The lengths given in . n-AI03GaO7As angstroms indicate the thicknesses of Undoped Al Ga . As, 50 (spacer) the layers. o.3 O7 A Two-dimensional electron gas Semi-insulating GaAs substrate

408 j ohll s Hopkins APL Technical Digesl. Volume /3. Number 3 (/992) Reliability olGa/lium Arsenide Del'ices

Table 1. Failure mechanisms of GaAs compound semiconductors.

Failure site Acce I eratin g Median life temp. Failure mechanism Acceleration factor conditions at failure site (h) (OC) Field-effect transistors Sinking gatea AE = 2.5 eV 245, 260, 275, 290, 310°C 150 Sinking gateb AE = 1.34 eV HTRB at 225, 250, 260°C RF bias at 200°C Burnout (breakdown)C Unknown (early failure) <150°C, <190°C, <225°C d Au-Ga intermetallic 24,000-hour test T ell = 140, 150°C e Schottky degradation T ch = 58, 190, 225°C d W-Ni gate contam ination 4,000-hour test T ch = 83 °C Interdiffusion a 7 Interconnect AE = 2.24 eV 250, 275, 300°C >8 X 10 150 a Air bridge AE = 0.43 eV 200, 225, 250°C >2 X 105 150 Nichrome thin filma AE = 1.03 eV 125, 175, 200°C 6 X 105 150 Electromigration Ohmica N-factor = 3.5 (203°C) 0.455, 0.91 mA/cm2 Ohmic metale AE = 1.5 eV <180°C, <240°C, <270°C Interconnecta N-factor = 1.5 (300°C) 0.455, 0.91 , 1.365 mA/cm2 >8 X 107 150 Air bridgea N-factor = 4 to 5 (250°C) 1, 2, 4 mA/cm2 >2 X 105 150 Nichrome thin filma N-factor = 3.0 (200°C) 2.5, 5.0, 7.5 mA/cm2 6 X 105 ISO Gate metal voidint AE = 1.5 eV T ch = 150, 190, 225°C Gate metal voidint AE = 1.18 eV T eh = 180, 240, 270°C Integrated circuits Microwave amplifierf AE = 1.75 eV 225, 240°C 8.4 X 106 150 Digital counterg AE = 1.65 eV 260, 275°C 3.5 X 106 150 MMIC switch (sinking gate)h AE = 1.3 eV DC bias at Vds = 8 V, 50% I dss, T ch = 225, 245, 260, 290°C Note: Blank entri es indicate that the data were not avai lable. MMIC = monolithic microwave integrated ci rcuit, AE = activation energy, N-factor = current density exponent, HTRB = high-temperature reverse bias, RF = radio frequency, T ch = channel temperature, Vds = drain-to-source voltage, I dss = drain-to-source saturation current. Table was prepared by W. Roesch of Triquint Semiconductor for the Electronic Industry Association JC- 50.1 committee on GaAs reliability. "Data are from Roesch et aI. , U.S. Conference on Gallium Arsenide Manufacturing Technology, Nashvi lle, Tenn. (8-10 Nov 1988). bData are from Ersland et aI. , IEEE Gallium Arsenide Integrated Circuit Symposium, Nashville, Tenn. (7-9 Nov 1988). CData are from Russell et aI. , "Power GaAs FET RF Life Test Using Temperature-Compen ated Electrical Stressing," in Proc. 1986 iEEE International Reliability Physics Symp. , Anaheim, Calif., pp. 150-156 (1986). dData are from Postal et aI. , "RF Operational Life Test of Power GaAs FET Ampli fiers," in Proc. 1983 IEEE International Reliability Physics Symp., Phoeni x, Ariz., pp. 293-296 (1983). "Data are from Riley et aI. , Gallium Arsenide Reliability Workshop, Portland, Oreg., Paper III.l ( 13 Oct 1987). fpersona l communication from Rubalcava et aI. , TQS (Jun 1988). gPersona1 communication from Ingle et aI., TQS (Apr 1987). hpersonal communication from Ersland et aI., MIA COM (1988). as RF bias conditions are deemed necessary for power contacts to the GaAs. Samples were unbiased during devices to correctly simulate the duty cycle and its con­ environmental stress. Drain-to-source saturation current sequent heating. We judge that storage or shelf tests are (ldsJ, gate-to-source pinch-off voltage (Vgsp), transcon­ of little use since no field is present in the semiconductor ductance (gIll)' and leakage currents were monitored ini­ material. Failure mechanisms such as electromigration tially and after 250, 512, 750, and 1000 cycles of thermal and interdiffusion are generally accelerated by the elec­ shock. Pertinent results were the following: tric field in such devices. 1. After 1000 cycles of thermal shock, the following failure ratios were found with respect to the gate-to­ source leakage current (las > 10 IlA): P35-1140 (0 .3-llm Signal MESFET Evaluation MESFET), 2/4; NE-710 (0 ~3-llm MESFET), 1/8; and HMF- Three types of GaAs MESFET'S were evaluated for ton g­ 0314 (0.5-llm MESFET), 0/4. term reliability. The HMF-0314 device is a signal MESFET 2. All dev ices passed the package hermeticity test with a gate length of 0.5 Ilm; the P35-1140 and NE-710 after completion of thermal shock. Package herm eticity devices are similar transistors, each with a gate length of is checked by a leak test. 0.3 Ilm. 3. After 1000 cycles of thermal shock, the P35-1140 Thermal shock tests of 1000 cycles between temper­ transistors showed a 5% decrease in performance with atures of -65°C and 150°C with fifteen-minute dwell respect to I dss ' The NE-7 IO and HMF-0314 transistors periods were canied out to determine the integrity of the showed no significant degradation.

Johlls Hopkills APL Techllical Digest. Volume 13 . Numher 3 (1992) 409 R. H. Maurer e{ 01.

Before life testing, the devices were characterized over radation of 52 1 for the HMF-0314 MESFET, which is sig­ a -60°C to 1000 e temperature range by measuring the nificant and correlated with the considerable decrease in variation in DC parameters such as Idss , Vgsp, gm, and Id ss for the same device type. The NE-7l0 and P35- J 140 leakage currents. The DC bias conditions for the life test MESFET'S showed no significant degradation in either DC were carefully established to produce junction tempera­ or RF parameters that was caused by the life test. tures of 200°C to 210°C in the transistors while in HEMT Evaluation a constant-temperature oven. Before, during, and after the 1000-hour life test, we measured both DC and RF Accelerated life tests were also performed on three (5 parameters) responses to be able to correlate any deg­ types of GaAs HEMT'S: NE-202, MGF4302A, and radation in these two sets of data due to aging. The FHX06FA. As for the signal MESFET'S, the life tests were forward transmission scattering parameter is 5 , whose carried out in an oven at a temperature of 180°C to 2 1 0 amplitude, when squared, is equal to the maximum avail­ produce a channel temperature of 200 e in the HEMT'S DC DC able gain from an RF device. when bias was applied. The bias consisted of a Figure 3 shows that the HMF-03l4 MESFET was the drain-to-source current (Ids) of about 10 rnA at 3 V, which was carefully controlled by an active feedback loop to only one to suffer significant degradation in Idss over the duration of the test. Figure 4 shows the substantial deg- maintain a constant channel temperature during the test. This bias current is about 33 % of the ldss for each HEMT type. Five sampl es of each type of GaAs HEMT were subjected to the life test: DC measurements were made at ~ 80 ..s 0, 25 , 50, 100, 250, 500, and 1000 hours with an HP (/) (/) 4142B parameter analyzer; RF measurements were made ...... "0 c- 70 at 0,250,500, and 1000 hours with an HP 8510 network ~ analyzer. The findings were the following: 5 (.) NE-202. The mean I dss decreased from 29.6 to 22.9 rnA c 60 0 for the fi ve NE-202 samples as a result of the life test. This .~ decrease represents an average degradation of23% caused co:::J C/) 50 primaril y by a 50% decrease in I dss by one device. The other Q) 2 four devices had a mean decrease in Id ss of just 15 %. No :::J 0 pinch-off voltage failures OCCUlTed for these HEMT'S, and C/) 40 E the magnitude of 5 21 degraded by less than 1 dB across the c frequency range of 2 to 18 GHz (Fig. 5) . .~ 0 30 MGF4302A. These five devices exhibited wide scatter 0 200 400 600 800 1000 in their Idss and transconductance data, even initially. One Aging time (h) device exhibited a large increase in I dss and gm as a result of Figure 3. Drain-to-source saturation current as a functi on of aging the life test, probably a kind of burn-in phenomenon. The time for three different signal metal-semiconductor field-effect other four devices, which showed more stable DC behavior, transistors : HMF-0314 (black), P35-1140 (blue), and NE-71 0 (red). had less than 5 % degradation in the magnitude of 5 21 across the 2- to 18-GHz frequency range after the 1000-hour life test (Fig. 6). Although no catastrophic failures were experienced, two of the devices did not pinch off Ids to 100 itA with V gs p as low as - 5 V at the completion of the life 4 test, thereby violating the V gs p specification. FHX06FA. The performance of these HEMT'S was very unsatisfactory. One device would not pinch off after 25 hours of ex posure; a second failed in a similar manner after OJ 3 ~ 100 hours; and a third device failed after 250 hours. A Q) "0 fourth device showed a 57% negative shift in Vgsp at the .-E c 2 completion of the 1000-hour test. Devices completing the CJ) al life test also exhibited large increases in leakage cUlTents. E C/)N Power MESFET Evaluation A reliability study of FLC053WG (0.75 W) and FLM7785-8C (8 W) MESFET'S was also conducted. Spe­ o cifically, DC bias life tests of FLC053WG and FLM7785- 8C power MESFET'S were carried out, and a life test of an FLM7785-8C device with DC bias and RF drive was per­

_ 1L-__~ __-L __ ~ ____L- __~ __-L __ -J __ ~ formed to detect any RF output power degradation that 2 4 6 8 10 12 14 16 18 might occur. Continuous wave frequency (GHz) The life test for FLC053WG devices was performed Figure 4. Frequency response of the forward transmission scat­ on a temperature-adjustable hot plate in an enclosed tering parameter (S2') magnitude, initially (black) and after 1000 chamber. The test was run at a junction temperature of hours (blue) of the life test, for the HMF-0314 device. about 175°C for each device. The DC bias conditions were

410 JoiJns Hopkins A PL Technical Digesl. Volume 13, Numher 3 (1992) Reliability of Gallium Arsenide Devices

ated mounting hardware. The DC bias conditions were the same as for the FLC053WG devices, and the junction temperature was kept at 175°C. co Two samples were tested. After 1000 hours of aging, ::s the first sample experienced changes of 3.05%, 1.44%, (l) -0 0.476%, and 26% in the leiss , V gs p' gm' and S 21 parameters, -~ C 0) respectively. The changes in the same four parameters co E for the second sample were -11.9%, - 2.4%, 1.9%, and C/)N 0.15%, where the minus signs indicate a decrease. 5 The purpose of the RF output power degradation test was to determine whether the FLM7785-8C power MES ­ FET being used in a three-stage amplifier, which consists 4L---~---L--~----L-__-L __ ~ __~L-~ of one FLC053WG, one FLC253MH-8 (a 1.5 -W MES­ 2 4 6 8 10 12 14 16 18 FET), and one FLM7785-8C in cascade, is susceptible to Continuous wave frequency (GHz) a phenomenon called "power slump." Power slump is a Figure 5. Frequency response of the forward transmission scat­ condition in which a power MESFET exhibits a gradual tering parameter (52' ) magnitude, initi all y (b lack) and after 1000 decrease in output power over a period of time when hours (b lue) of the life test, for the NE-202 device. driven into compression by a large microwave signal. (Compression is the state in which the output power of 11 the device no longer increases linearly with increasing input power because of nonlinearities of the MESFET.) 10 Power slump is believed to be caused by voltage break­ downs that occur when the microwave signal amplitude co 9 ::s is at its positive or negative extreme. 10 At the moment a (l) -0 8 voltage breakdown occurs, a short current pulse exists. .~ c This repeated voltage breakdown current is what causes 0) co 7 the observed output power degradation. The power E slump susceptibility is dependent on the amplitude of the C/)N 6 input RF drive signal. The output-power life test of the FLM7785-8C power 5 MESFET was conducted with DC bias and RF drive. The 4 test was set up in accordance with the block diagram 2 4 6 8 10 12 14 16 18 shown in Figure 7. The DC bias conditions for the driving Continuous wave frequency (GHz) three-stage amplifier were Vgs ::: -0.8 V, and Vel s ::: 9 V. Figure 6. Frequency response of the forward transmission scat­ The microwave generator was set at a frequency of 8.475 tering parameter (52' ) magnitude, in itiall y (black) and after 1000 GHz and at a power level that enabled the amplifier to hou rs (blue) of the life test, for the MGF4302A device. operate at about the I-dB compression point. The DC bias conditions for the test device were Vgs ::: -1 V, and as follows: l ei s ::: 60% of leiss, and Vel s ::: 10 V. The Vels of Vels ::: 9 V; the operating junction temperature was esti­ 10 V was derated from the absolute maximum of 15 V mated to be 85°C. since the FLC053WG devices previously proved to be After more than 1000 hours of the life test, the MESFET incapable of surviving more than 200 hours ofthe life test remained operational with no apparent slump in the RF at the maximum Vel s bias. output power and no significant degradation of DC or RF The results of the life test for the FLC053WG devices parameters. showed that after 1000 hours of aging, the mean Iel ss Evaluation of the Digital Process Control Monitor decreased from an initial value of 271.9 rnA to 263.3 rnA, a change of about 3%. One of the FET'S remained un­ In developing a beacon receiver, one approach imple­ changed, whereas the rest varied from 2% to 6%. No mented a custom-designed, digital, GaAs integrated cir­ pinch-off voltage failures occurred. The gate-to-source cuit consisting of a phase accumulator, high-speed read­ only memory, and a digital-to-analog converter. This leakage currents stayed quite constant. The 521 parameter (measured only for one MESFET) changed by 5.7% at a custom integrated circuit is functionally known as a direct test frequency of 8.475 GHz. digital synthesizer. A digital GaAs foundry may be cho­ Subsequent to the 1000-hour life test, step stressing sen to fabricate this device because of the low-power was performed by incrementally increasing lei s to deter­ characteristics of its direct coupled FET logic process. I I mine whether the devices could tolerate higher levels. At The foundry process uses self-aligned enhancement 80% of Iel ss with Vel s derated to the original 10 V, three and depletion (E/D) MESFET'S with fo ur types of metals for of the five transistors ceased to function after less than interconnection. This self-aligned process fabricates the forty-eight hours. n+ ohmic contact region using the gate as a mask; there­ The test setup for the DC bias life test of the FLM7785- fore, the drain and source are aligned with the gate. The 8C devices consisted of a temperature-adjustable hot process control monitor includes E/D FET'S with various plate, power supplies, temperature monitors, and associ- gate lengths and widths, contact metals, gate metal, metal

.fohns Hopkil1s APL Technical Digest. Volume 13. Number 3 (1992) 411 R. H. Mallrer e! 0/.

Microwave source

Gate Drain power supply power supply

Figure 7. Test setup used in evaluating the susceptibility of the FLM77S5-SC power MESFET (metal-semiconductor field-effect transistor) to power slump.

resistors, and so on. Our study focused on the active components in these process control monitors. - The E/D FET'S were selected because their gate widths 1400 and lengths were close to the design requirements. For ~ example, one inverter implementation uses a depletion :? FET (OFET) as an active load and an enhancement FET -.5 1200 - (f) (EFET) as a level shifter. The drive capabi liti es of these ...:0 (f) E/D FET'S can be boosted by careful sizi ng of the gate c- lengths and widths. We have investigated the uniformity ~ ~ 1000 0 of the threshold voltage (Vth ) and Ids for matched FET c 0 pairs, the variation of Vth and Ids for perpendicularly -~ ali gned FET'S, the transistor sizing effects on V and I ds, ::::J th co 800 and the thermal characterization of V . f/) th Q) The test results were compared with the appropriate ~ ::::J 0 design rules to observe the variance of the device pa­ f/) rameters. A lOOO-hour life test was performed where data S 600 C were taken ini tially and after 100, 300, 500, and 1000 'co hours to estimate the long-term shift in the device param­ 0 eters. 400 Ten packaged process control monitors (forty E/D FET'S in all) were used for testing, and fo ur packaged devices were used as controls. Since typical FET'S have a power 200 f::======] dissipation of less than 1 mW, the junction temperature o 200 400 600 SOO 1oo n of the die was estimated to be the same as the base plate Aging time (h) temperature, 125°C. Threshold voltage measurements Figure 8. Degradation of four different enhancement field-effect were made on all transistors over the temperature range transistors over the 1 OOO-hour life test. from - 30°C to +70 °C. The following observations were made: 1. Layouts of process control monitors are extremely compact, and the accessibility to the bond pads is poor. 5. Vth varies by about -l.2 to -1.3 mY/DC. This 2. The adjacent FET'S (also known as "matched FET 'S") change in Vth was found to remain constant over the entire indicated excell ent Vth uniformity and verified the repeat­ temperature range (-30°C to 70°C), and it is consistent ability of our experimental setup. with the manufacturer-reported value of -1.0 mY/DC .1 2 3. The perpendicul ar E/D FET parameters were the 6. Ids scaled linearly with the gate width for the same same to within 10% to 20% of the adjacent FET'S. gate length. Thi s finding agreed with the theoretical 4. The DFET'S stabili zed before burn-in, and the EFET'S result that Ids is proportional to the ratio of the gate width stabil ized after 100 hours of burn-in (Figs. 8 and 9). to the gate length. 13

412 Joli ns Hopkins APL Techl/ical Digest. Volume J3, Number 3 (1992) Reliability ofGa/lium Arsenide Devices

310 ,------,------,------,------,------,

300

290

..c ~~ 280 (]) CJ) o~ > t5 270 .J:: (fJ .c(]) f-

250

240 L-----~------~------~------~----~ o 200 400 600 800 1000 Aging time (h)

Figure 9. Threshold voltages of four different enhancement field­ effect transistors as a function of time. The curves are color-coded to show correspondence to the four devices in Figure 8.

FAILURE ANALYSIS The HEMT and power MESFET devices were analyzed for cause of failure. The analysis was performed with a scan­ ning electron microscope (SEM) equipped with an ion pump and electrical feed-throughs so that transistors could be observed in an active state and in a clean en­ vironment if the device was still working. The SEM in­ cluded an X-ray detector for microanalysis. The SEM images were made by exploiting two distinct signals. The more common method of collecting the secondary elec­ trons emitted from the sample surface was employed to image all examined devices. When an active device was in the microscope, the source current from the transistor itself was fed to an ancillary preamplifier and used di­ rectly to make the photographs. As discussed later, this process produces information and details not available in the secondary electron mode. X-ray microanalysis was useful for determining the local compositions of the va­ riety of structures or unusual areas on a device under scrutiny. HEMT Failure Analysis Both failed and control HEMT devices were subjected to failure analysis. Transistors of this sort from Fujitsu, Mit­ Figure 10. Photographs of a Fujitsu device that underwent a 1000-hour life test. The secondary electron image (top) reveals subishi, and NEe corporations were examined. A control only a darkened area (arrow) at a point of gate-to-source current device from each maker was examined for comparison with leakage seen in the source current image (bottom). the failed transistors. The control devices had only been characterized electrically and were not subjected to aging. In general, HEMT'S that had fa iled parametrically were examined, although we also occasionally looked at cata­ Figure 10 presents photographs of a Fujitsu FHX06FA strophic failures. The aged devices were subjected to a HEMT that had undergone 1000 hours of aging. In the junction temperature of 200°C for 1000 hours. That inves­ secondary electron image, one observes a barely notice­ 14 tigation was described in detail in the literature. ,IS able darkened area along the gate metallization of the

.fohns Hopkins APL Techllical Digest, Volume 13 . Number 3 (1992) 413 R. H Maurer et al. transistor. In the source current image mode, a bright spot occurs, indicating a subsurface defect resulting in cunent leakage from the gate to the source. A similar pair of images is shown in Figure 11. Here, however, the secondary electron image gives no hint at all of trouble. The source cunent image reveals a dark spot, however, indicating a point of gate-to-drain current leakage. Sometimes a surface defect was obvious, such as the one shown in the top of Figure 12, where an eruption along the gate metallization is clearly visible on another Fujitsu device. The localized eruption is associated with an expanded area of gate-to-source cunent leakage, as demonstrated in the source cunent image in the bottom of Figure 12. For the Fujitsu HEMT'S, we observed that transistors with large initial leakage cunents due to defect areas along the gate eventually developed into areas of increased cunent leakage that conelated with an inability to electrically pinch off the transistor. The control MGF4302A device from Mitsubishi had an intriguing area in the central gate region that caused the HEMT to stop conducting when a 20-ke V electron beam penetrated the area and the g'lte potential was 0.05 V more positive than the pinch-off voltage. This switching effect did not happen with 10-keV beam en­ ergy, indicating that the anomaly responsible for the effect was deeper than 500 nm , as determined by Monte Carlo calculations of electron beam penetration. This depth conesponds to a defect in the 2000-nm undoped GaAs buffer, making it appear as if cunent is leaking through the buffer. This defect did not appear to affect the electlical characteristics of the HEMT. Investigation of an NE-202 control HEMT did not reveal anything unusual, and the transistor seemed to behave as designed. Analysis of an NE-202 transistor that experi­ enced a catastrophic pinch-off voltage failure during the life test revealed two extraneous pieces of material along the edge of the gate. This material appeared to have resulted from a processing problem during manufacture. A source cunent image of the same region revealed a gate-to-source current leakage area just above one of the extraneous pieces of material. Another NE-202 transistor had a 50% decrease in / dss during the life test; that is, it suffered a parametric failure after 1000 hours of aging. The analysis indicated an anomaly in a region along the gate for electrical conditions under which the transistor should have been turned off. The transistor suffering the catastrophic failure had leakage cun'ents 10 times larger than those of the transistor that failed parametrically. Other investigators have reported similar failure mech­ 16 anisms for GaAs HEMT'S. Buot et a1. proposed a mech­ anism leading to subsurface burnout in GaAs HEMT'S in Figure 11. Secondary electron image (top) and source current which a highly-positive-temperature coefficient region is image (bottom) of a gate-to-drain leakage currentdefect (darkened heated so that thermal runaway occurs in the presence of area along gate metallization) in another area of the Fujitsu device an electric field; this region bridges two metallic fila­ shown in Figure 10. The secondary electron image has no distin­ ments with different potentials that have been formed by guishing characteristic. interdiffusion of metallization with the GaAs and AI­ GaAs semiconductor layers. Anderson et al. 17 pointed out that compound semiconductors such as GaAs typically the subsurface defects causing failure in the HEMT'S were have 1000 times more flaws or lattice dislocations than either latent defects present originally in the GaAs ma­ silicon has. This fact alone enhances migration and in­ terial or created during the aging test by the thermal terdiffusion due to weak bonding. Thus, we conclude that runaway/bridging phenomenon, or a combination of both.

414 Johl/s Hopkins APL Techl/ical Digest, Volume 13, Number 3 (1992 ) Reliabiliry ()fGallium Arsenide Devices

Figure 13. Metallization of a power MESFET (metal-semiconductor fie ld-effect transistor) after failure (5-kV acceleration of electrons, 20° off vertical , 300x magnification).

transistors had an extensive network offilaments growing on top of the residual Au metallization, as shown in Figure 14. X-ray microanalysis of the filaments on the Au revealed the spectrum shown in Figure 15; a substan­ tial amount of As is seen, but no trace of Ga is present. The other two failed MESFET'S had As associated with the Au but, again, no Ga. This failure is consistent with the long-term burnout mechanism described by Wemple et al. 6 that was referred to earlier in this article.

SUMMARY As a result of our space qualification testing and as­ sociated failure analyses, we have found that the signal GaAs MESFET'S are reliable enough for space applica­ tions; digital GaAs process control monitor performance indicates that digital GaAs devices can also be used for space applications with some burn-in to ensure stabiliza­ tion; power GaAs MESFET'S require substantial derating (25%-35%) of specified maximum parameters to be con­ sidered for long-life space use; and GaAs HEMT'S are presently not mature enough for space systems. If not derated, the power GaAs MESFET'S exhibit a long­ term burnout mechanism detectable by the As meshwork Figure 12. The secondary electron image (top) shows a large blown-out area (arrow) on the left side of the gate metallization. The observed on the surface of the transistor during failure source current image (bottom) shows leakage over an expanded analyses-a phenomenon observed by others. region associated with this defect. The phenomenological model that emerges from the HEMT failure analysis is that small defects, some of them in subsurface regions and indicated by high leakage Power MESFET Failure Analysis currents on unstressed control devices, may cause local­ The lids were removed from five FLC053WG power ized overheating. The localized hot spots eventually erupt MESFET'S, and the devices were examined with the SEM. during DC biased accelerated life testing, creating large Three of the devices ceased to function and had under­ defect areas observed at the surface of the HEMT'S in the gone burnout failure, as shown in Figure 13. One of the gate region. The observation of these large defect regions

Johlls Hopkills APL Techllical Digesl. \lolllllle 13. Numher 3 (1992) 415 R. H . Maurer ef al.

is correlated with the loss of gate control and the inability to pinch off the HEMT' S. Our life test experiments indicate that ini tial gate-to-source and gate-to-drain leakage cur­ rents shoul d be less than 1 /l A for successfu l resul ts. Manufactu rers' specifications for these parameters cur­ rently range from 10 to 50 /lA , where VgS ranges from - 2 to - 3 V. ~

REFERENCES I Christou, A., Tseng, W. , Peckerar, M., Anderson, W. T. , McCarthy. D. M., et aI. , "Failure Mechanism Stu dy of GaA s MODFET Devices and Integrated Circuits," in Pmc. 1985 IEEE II/ I. Reliahililv Ph."sics SYl1lp ., O rl ando, Fla. , pp. 54-59 (1985). 2Li li enti al-Weber, Z., Gronsky, R. , and Washburn , J., "Schottky and Ohmi c Au Cont ac ts on GaAs: Mi croscopic and Electrical In vesti gations," J . Vac. Sci. Tech I/ o/. B 4, 9 12-9 18 (Ju l/A ug 1986). 3 Donze ll i, G. and Paccane ll a, A. , "Degradati on Mechani sm of Ti/Au and Ti/ Pd/Au Gate Metall izati ons in GaAs MESFETs," IEEE Trans. Eleclron Del'ices ED·J4, 957-960 (May 1987) 4 Anderson, W. T. , Buot. F. A .. and Chri stou, A., " High Power Pul se Reliability of GaAs Power FETs." in Proc. 1986 IEEE 1111. ReliabililY Physics Symp. , Anaheim , Cal if. , pp. 144-149 ( 1986). SCanali, C , Castaldo, F. , Fa ntini , F. , Ogli ari. D. , Umena, L. , et aI. , "Gate Metall iza ti on 'Sin kin g' int o the Ac ti ve Chann el in Ti/W/Au Metall ized Power MES FETs," IEEE Eleclro ll Del'ice LeI!. EDL-7. 185- 187 ( 1986). 6Wemple, S. H. , iehous, W, C , Fukui. H., Irvin , 1. C , Cox, H, M., et aI. , " Long Term and Instantaneous Burnout in GaAs power FET's: Mechanisms and Soluti ons," IEEE Tral/ s. Eleclroll DeI'ices ED-28, 834-840 (l ui 198 1). 7 Polli no, E .. Microeleclrollic Reliahilily: IlIlegril.\' . Assessl1Iel/ l, all d Assur- Figure 14. Meshwork growth on metallization of a power MESFET ali ce , Vo l. II I, Artec h House, orwood, Mass, ( 1989), (metal-semiconductor field-effect transistor) (5-kV acceleration of 8 Awano, Y. , Ko sugi, M. , Kosemura, K., Mi mura, T. , and Abe, M. , "Short electrons , 45° off vertical , 2000 x magnification ). Channel Efrects in Subquarte r-Mi crometer-Gate HEMTs: Simu lati on and Ex periment," IEEE Trans, Eleclroll DeI'ices 36,2260-2266 (Oct 1989). 9 Joshin , K" Mimura, T. , Niori , M. , Yamashi ta , Y., Kose mura, K. , et aI. , "Noise Performance of Microwave HEMT," in Pmc. IEEE 1111 . MIT-S Micl'OH'are 2000'---1.---r-1--r-1 --'-1 --'-1--'-1 --'---'---'---' SVl1lp .. Boston, Mass ., pp. 563-565 ( 1983), Au IOFrensley, W. R. , " Power-Lim it ing Breakdown Effec ts in GaAs MESFET's," I EEE Trans. Elecrron Deriee.\' ED-2R, 962-970 (Aug 198 1). II Thomas, H., ed. , Gallium Arsenide jin Del'ices alld IlIl egra/ed Circll i/s, Peter 1600 Peregrin us Ltd. , Lo ndon, pp. 326-339 ( 1986) (f) C 12 Long, S. I. , and But ner, S. E., eel s., Chap. I in GaA s Digilal IC Design , ::::l McG raw-Hill , ew York ( 1990). 8 1200 13Shur, M., ed., GaAs Del'ices alld Circll ils, Pl enuJl1 Pu bli shing Corp., ew o York, pp. 449-488 ( 1989). 0> 14 Maurer, R. H., Chao, K., Nhan, E. Benson, R. C , and Bargeron, C B. , ~ 800 " Reliability St udy of Ga lliulll Arsenide Transistors," in Pl'Oc. 40lh EieCll'Ollic ::::l As , Componeills alld Teclinology COIlt:, Las Vegas, Nev., pp. 670-676 ( 1990), Z ]) Maurer, R. H., Bargero n, C B., Benson, R. C , Chao, K. , Nhan , E. , and Wi ckenden, D. K. , "Failure Analys is of Aged GaAs HEMTs," in Proc. 199 1 Au 1111. Reliahilil" Plivsics Symp., Las Vegas, Nev" pp. 2 14-223 ( 199 1). 16 Buot, F. A. , Anderson, W. T., Christou, A., and Si eger, K, J., "Theoreti cal and A Ex perimental Study of Subsurface Burnout and ES D in GaAs FETs and 4 5 6 7 8 9 10 HEMTs," in Proc. 1987 IEEE 1111. ReliahililY Phvsics Symp ., San Diego, Accele ration voltage of the electrons (keV) Calif. , pp . 18 1- 190 ( 1987). 17 An cie rson, W. T.. Chri s(ou, A., Buot, F. A., Archer, J., Bechtel, G., et aI. , " Relia bility of Di sc rete MODFETs: Life Testing, Rad iation Effects, and Figure 15. Chem ical composition of metallization of power MESFET ESD," in PI'OC'. 1988 IEEE 1111 . ReliahililY Phvsics Svmp., Mon terey, Calif. , (metal-semiconductor field-effect transistor) shown in Figure 14. pp. 96- 10 1 ( 1988).

4 16 Jolil/s Hopkills APL Tecli ll ical Digesl. Vo lume 13. Numher 3 (1 992) Reliahilitv of Callium Arsenide Del'ices

TH E AUTHORS

RICHARD H. MAURER received C. BRE T BARGERON earned a a Ph.D. in theoretical pa rti cle phys­ Ph. D. degree in phys ics at the ics from the Univers ity of Pitts­ Uni versi ty of Illi nois in 197 1 and burgh in 1970. He spent three years joined APL th at year as a member as a postdoctoral fe ll ow in cosmic of the Research Center. Since join­ ray physics at the Bartol Research ing APL, Dr. Bargeron has been Founda ti on in Swarthmore, Penn­ in vo lved in problems in solid ·ta te sy lvan ia. Dr. Maurer joined APL in phys ics, light scatt eri ng, chem ical 198 1 and is a member of the lasers, art erial geometry, corneal Principa l Professional Staff and the damage from in frared radia ti on, Space Department 's Reli abil ity mineral deposits in pathological Group. Hi s pu blicati ons incl ude ti ss ues, quali ty control and fa ilure articl es on anti proton producti on, analys is of microelectroni c compo­ extensive air showers, total dose nent s, elec tron phys ics, and surface effec ts on digital logic devices and sc ience. quartz crys tal resonators, pelma­ nent radi ati on damage to silicon and galli um arseni de solar cells, single-event effec ts in very large scale integrated dev ices, safety aspects of lithium batteri es, spacecraft elec tron ics packaging, and re li ability studies of gallium arsenide transistors.

KEDO G CHAO was born in RICHARD C. BE SON received a Taipei, Taiwan, in 1955. He re­ B.S. in physical chem ist ry from ceived a bachelor's degree in elec­ Michigan State Un iversi ty in 1966 trical engineering from the Univer­ and a Ph.D. in physical chem istry sity of Colorado at Bou lder in from the Un iversi ty of Ill inois in 1986. Before joining APL that year, 1972. Si nce joining APL in 1972, he had he ld va ri ous posi ti ons in the he has been a member of the Test Eq uipmen t Development Milton S. Eisenhower Res arch Group of Storage Technology Cor­ Center and is cu rren tl y supe rvisor poration since 1977. As an associ­ of the Ma terials Science Group. He ate member of the Satellite Reli ­ is involved in research on the prop­ ab ility Group at APL, Mr. Chao was erties of materials used in mi cro­ responsi bl e fo r reestablishing the electroni cs and the appli cation of digital test fac ility . Hi s interests opt ical techni ques to sUlface sci­ include reliability and quality as­ ence. Dr. Benson has also con­ surance iss ues for integrated cir­ ducted research in Raman scatter­ cuits and multichip modules. Mr. ing, optical swi tc hing, laser- in­ Chao is an active member of the IEEE Computer Society and a member duced chemistry, chemi cal lasers, energy transfer, chemi luminescence, of the standard committee pa rticipa ting in boundary scan architecture. flu orescence, and microwave spectroscopy. He is a member of IEEE, He also was th e techni cal program chair of the 199 1 lEE YLST Test the American Physical Society, the Ameri can Vacuum Soc iety, and the Sympos ium. Mr. Chao has authored papers on space qualification Materials Research Society. testi ng of GaAs transistor, integrated circuits, boards, and modul es.

ELBERT NHAN received a B.S .E.E. from the Virgi ni a Tech in 1989 and an M.S.E.E. from The John s Hopkins Uni versity in 1992. Mr. Nhan has been a member of the Associate Professional Staff in the Satelli te Reli abi li ty Gro up of APL's Space Department since 1989. In that pos ition, he has been involved in the electri cal and total dose testing and evalu ati on of lin ­ ear integrated circui ts used in space hardware fo r vari ous Space De­ partment programs. Mr. Nhan is also responsible for electrical test­ ing of microwave active and pas­ sive components. He is a co-au th or of several articles on the reliability of gallium arsenide transistors.

Jolills Hopkills APL Teclillical Digest. Voillme /3. Numher 3 ( / 992) 4 17