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MAYD Exhibit 5 Slipsheet Case 5:07-cv-04330-RMW Document 304-4 Filed 09/03/2008 Page 1 of 35 EXHIBIT 4 Case 5:07-cv-04330-RMW Document 304-4 Filed 09/03/2008 Page 2 of 35 111111111111111111111111111111111111111111111111111111111111111111111111111 US006859902Bl (12) United States Patent (10) Patent No.: US 6,859,902 Bl Dalal et al. (45) Date of Patent: Feb. 22,2005 (54) METHOD AND APPARATUS FOR HIGH 6,532,561 B1 * 3/2003 Turnquist et at. 714/738 SPEED IC TEST INTERFACE 6,557,128 B1 * 4/2003 Turnquist 714/724 6,557,133 B1 * 4/2003 Gomes 714/738 (75) Inventors: Wajih Dalal, Santa Clara, CA (US); Masashi Shimanuuchi, Lyons (FR); * cited by examiner Robert J. Glenn, San Jose, CA (US); Burnell G. West, Fremont, CA (US) Primary Examiner-Albert Decady AssL5tant Examiner-Mujtaba Chaudry (73) Assignee: Credence Systems Corporation, (74) Attorney, Agent, or Firm-Wagner, Murabito & Hao, Milpitas, CA (US) LLP (57) ABSTRACT (* ) Notice: Subject to any disclaimer, the term ofthis patent is extended or adjusted under 35 A testing method and circuit used to test high-speed com­ U.S.c. 154(b) by 402 days. munication devices on Automatic Test Equipment-ATE. The method and circuit provide a solution to testing very (21) Appl. No.: 09/679,042 high speed (2.5 Gbps and above) integrated circuits. The circuit fans out the data streams from the output of the (22) Filed: Oct. 2, 2000 Device Under Test (DUl) to multiple tester channels which (51) Int. CI.7 G01R 31/28 under-sample the streams. The testing method and circuit (52) U.S. CI 714/726; 714/738 also allow for the injection of jitter into to the DUT at the (58) Field of Search 714/738, 724, output of the DUT. The skipping of data bits inherent in 714/726, ~~_733, 727, 731; 365/230; multi-pass testing is avoided by duplicating the tester resources to achieve effective real-time capture (saving test 370/225 time and improving Bit Error Rate). Moreover the circuit (56) References Cited synchronizes different DUTs with the timing of ATE hard­ ware independent of DUT output data. Also, a calibration U.S. PATENT DOCUMENTS method is used compensate for differing trace lengths and propagation delay characteristics of test circuit components. 4,984,161 A * 1/1991 Hayashi 6,327,678 B1 * 12/2001 Nagai 714/700 6,446,228 B1 * 9/2002 Kobayashi 714/724 7 Claims, 4 DraWing Sheets ~10 Test Load Board L \\ 13 OUT 12 J - Fan Oul Latches r···--··! 1)\ l~b CLKC // 15 16a< 11 - > 9:1.'t: • a - ' .17 Oat \ CLKCL Digital ... I-- > 16b< ¢il 1: PEC5 91> ' i"'17b Oat CLK.CL .. > r-- 16e< 9:1 ....., > ::1: 17e Datl I CLK.CLIt w:-- '-- J- > 16d< 9:' 1: 17d Data.~ V L.~ .... _J 18c 18d "- I' / High Speed ~asouree "- ) 14 Case 5:07-cv-04330-RMW Document 304-4 Filed 09/03/2008 Page 3 of 35 Cj • r:.I'J. ~10 • ~ ~ t""'t'- ~ Test Load Board t""'t'-= L 13 OUT 12 Latches ~ Fan Out ["""'-1 ('ll ?' N 11 15 ~±t~=J:!r=::C:-::LK~.C~L ~N N Digital 0 0 PEeS 01 ....---I----r-rn Oat CLK.CL ~=_+.i:::J---=-..;--l..---":::~ .~,1~7c~++-D-at_t+~==:;:;:J Cf). ('ll=- t=t! ('ll \i ( ,........ 0..... L- "- - • ~ High Speed Data Source ~ 00 ~~ fU~D ~ co I - Ol ) \e \0 14 Q " N ....~ Case 5:07-cv-04330-RMW Document 304-4 Filed 09/03/2008 Page 4 of 35 .e r----- - - - - - - -- - .rJ'J. I 12 ~ 26a ~ 27a ~ I t"'!'- I A_ Aft ~ I =t"'!'- I II >-~~ TESTER ELEMENT 125b 28b - - I 15 ~ ?' N ~N oN o VI 1J1 ('ll=­ .....('ll N o.... 27b ~ TESTER ELEMENT ,--- ~ en ~~ I co Fig. 2 til L \0 \0 ~ N ~ l-"- Case 5:07-cv-04330-RMW Document 304-4 Filed 09/03/2008 Page 5 of 35 u.s. Patent Feb. 22,2005 Sheet 3 of 4 US 6,859,902 BI Pertod = 2.50s 312.5ps OUT Serial OutputStream Channel 1 elk Channel 1 Strobe1 1----11--------------­ Channel n Strobe 1---------------------1 Fig. 3 Case 5:07-cv-04330-RMW Document 304-4 Filed 09/03/2008 Page 6 of 35 .e .r:F1 ~ ~ t'"'!'­ ("'0 =t'"'!'- R3~ 3.2Gbps A~ CMOS I -- I \ I ~ ~ 0'" N N '43 N RF ) 0 Relays ~~~ Differential }7 l 0 ~-- '''- nr"'r'" 01 '" PE:l rJl ~=" .....~ -I::>. , 0 400 MHz I• .... 400 MHz -I::>. 1 I PEGS VlIlvlvllUc;u ) Receiver e Fig. 4 00 0\ 00 Ol '0 \.0 Q N ee I-' Case 5:07-cv-04330-RMW Document 304-4 Filed 09/03/2008 Page 7 of 35 US 6,859,902 Bl 1 2 METHOD AND APPARATUS FOR HIGH data-in and data-out path. In addition, parametric measure­ SPEED IC TEST INTERFACE ments on the serial input such as Minimum Input Voltage cannot be performed unless the loop is opened, and a direct voltage amplitude control is applied to the serial input. FIELD OF THE INVENTION Lastly, output timing parameters of the OUT cannot be This disclosure relates to testing techniques and circuits tested unless the loop is opened. for testing high-speed communication devices onAutomatic Another solution to this problem involves integration of Test Equipment (ATE). external instruments to expand the bandwidth of the Al'E equipment. External instruments can be high bandwidth RELAl'ED ART 10 digitizing scopes, or jitter measurement boxes. The interface The challenge in testing high-speed electronic circuit may be through a GPIB (General Purpose Interface Bus) interfaces has been present for several years. In most cases protocol. The advantage of using external equipment is the in the past the data rates were ten times the standard rate of ability to expand the test equipment performance without the available Al'E equipment. Some approaches have used substantial upgrades. It also allows for a simple correlation multiplexing to provide a high speed data sources to Devices 15 between the lab bench characterization environment and the Under Test (OUTs) typically receiving data input at high Al'E environment. The drawbacks of this method are: (1) it speeds. See, for example, "Multiplexing Test System Chan­ requires a complex interface in order to program GPIB nels for data rates Above 1 Gbps" by David Keezer-Univ. drivers and, (2) the test time is lengthened because the of South Florida, 1990 International Test Conference, Paper typical GPIB interface is very slow and adds to the testing 18.3. 20 time substantially. Although the GPIB system drivers are typically available, it takes special effort to perform the link Other data handling solutions previously contemplated between the ATE software interface and the newly integrated are tailored toward SONET and Datacom Ics such as that instrument. This may require developing a special graphical presented in the paper "Frequency enhancement of digital user interface (GUI) with special driver commands linking VLSI systems," by Leslie Ackner & Mark Barber-Al'&T 25 to the scope instrument Bell Labs, Allentown Pa., 1990 International Test Conference, Paper 22.1. At the DUT output where the DUT SUMMARY output signals are tested and compared to expected values, use of a high bandwidth front end latch is introduced. This The present disclosure is directed to a testing method and latch captures the OUT high data rates through multi-pass 30 circuits to test high speed communication devices on oth­ testing. Multi-pass testing involves sending a particular erwise conventional (lower speed) Automatic Test Equip­ high-frequency bit stream through test circuitry multiple ment (Al'E), e,g" testing very high speed (2.5 Gbps and times and capturing each successive bit during each "pass," higher operating speed) integrated circuits operating at or single time that the entire bit stream travels through the speeds higher than conventional testing equipment. The circuitry. 35 circuit fans out the data stream from the output pins or ports In communication devices and applications for high speed of the Device Under Test (DUT) to multiple ATE tester networking devices called serializers and de-serializers channels. The testing method and design also allow for the (SERDES), under-sampling can be harmful in the sense that injection of jitter into the output of the DUT for testing it masks test failures. A key test is called the Bit Error Rate purposes. Further, the present invention avoids skipping data Test (BERl), referring to the number of bits that are trans- 40 bits through multi-pass testing (thus saving test time and Bit mitted incorrectly through the communications channel. Error Rate) by duplicating the tester resources to achieve This BERT number is measured in Parts Per Million (PPM). effective real-time capture. Moreover the present method This number refers to one bit Error for 1020 bits transmitted. synchronizes different data communication OUTs to the Under-sampling could potentially mask such errors if it timing of the Al'E hardware. Moreover, there is disclosed a occurs outside of the sampling window. Another technique 45 calibration method to compensate for differing trace lengths addresses the problem from the Design-For-Testability and propagation delay characteristics of test circuitry. standpoint. BRIEF DESCRIPTION OF THE DRAWINGS Other alternative approaches have been applied to test the OUT. For example, one approach is commonly referred to as FIG. 1 shows a high-level view of the present test fixture. the "Loop-back" technique. This method is applicable for 50 FIG. 2 shows a detailed schematic of the tester circuit. SERDES applications. In some electronic devices, a circuit FIG. 3 shows a timing diagram of how tester strobe implementing the loop-back is on-chip, This loop-back channels strobe OUT serial output change.
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