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Cygnus: GPU Meets FPGA for HPC

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Cygnus: GPU Meets FPGA for HPC Cygnus: GPU meets FPGA for HPC Taisuke Boku Director, Center for Computational Sciences University of Tsukuba in collaboration with R. Kobayashi, N. Fujita, Y. Yamaguchi and M. Umemura at CCS, U. Tsukuba 1 2020/01/29 LSPANC2020@Kobe Center for Computational Sciences, Univ. of Tsukuba Agenda n Introduction n Today’s accelerated supercomputing n Multi-Hybrid accelerated supercomputing n Cygnus supercomputer in U. Tsukuba n How to use and program Cygnus n Summary 2 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba History of PAX (PACS) series at U. Tsukuba n 1977: research started by T. Hoshino and T. Kawai n 1978: PACS-9 (with 9 nodes) completed n 1996: CP-PACS, the first vendor-made supercomputer at CCS, ranked as #1 in TOP500 1996 2006 2012~2013 2014 1978 1980 1989 6th gen: CP-PACS 9th gen: COMA 2nd gen. PACS-32 7th gen: PACS-CS 8th gen: GPU cluster HA-PACS 1st gen: PACS-9 5th gen, QCDPAX Ranked #1 in TOP500 Year Name Performance 1978 PACS-9 7 KFLOPS 1980 PACS-32 500 KFLOPS n co-design by computer scientists 1983 PAX-128 4 MFLOPS and computational scientists 1984 PAX-32J 3 MFLOPS toward “practically high speed 1989 QCDPAX 14 GFLOPS computer” 1996 CP-PACS 614 GFLOPS 2006 PACS-CS 14.3 TFLOPS n Application-driven development 2012~13 HA-PACS 1.166 PFLOPS n Sustainable development 2014 COMA (PACS-IX) 1.001 PFLOPS experience 2019 Cygnus (PACS-X) 2.5 PFLOPS LSPANC2020@Kobe 3 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba Accelerators in HPC n Traditionally... n Cell Broadband Engine, ClearSpeed, GRAPE. ... n then GPU (most popular) n Is GPU perfect ? n good for many applications (replacing vector machines) n depending on very wide and regular parallelism n large scale SIMD (STMD) mechanism in a chip NVIDIA Tesla V100 (Volta) n high bandwidth memory (HBM, HBM2) and local memory with PCIe interafce n insufficient for cases with... n not enough parallelism n not regular computation (warp splitting) n frequent inter-node communication (kernel switch, go back to CPU) 4 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba GPU performance: obtained by large scale SIMD type parallelism instruction instruction op op …. op op op op …. op op ….. data data data data data data data data GPU performance: branch condition degrades performance instruction instruction op op …. op op op op …. op op ….. data data data data data data data data if (a[i] < x) b[i] = a[i]; else b[i] = 0.0; GPU performance: branch condition degrades performance instruction instruction op op …. op op op op …. op op ….. data data data data data data data data if (a[i] < x) b[i] = a[i]; else b[i] = 0.0; GPU performance: branch condition degrades performance instruction instruction op op …. op op op op …. op op ….. data data data data data data data data if (a[i] < x) b[i] = a[i]; else b[i] = 0.0; GPU performance: low parallelism instruction instruction op op …. op op op op …. op op ….. data data data data data data data data for( i = 0; i < 2; i++) …. GPU performance: frequent communication instruction instruction op op …. op op op op …. op op ….. data data data data data data data data (in host code) MPI_xxx(); GPU_kernel1(); MPI_yyy(); GPU_kernel2(); …. FPGA (Field Programmable Gate Array) n Goodness of recent FPGA for HPC n True codesigning with applications (essential) n Programmability improvement: OpenCL, other high level languages n High performance interconnect: 100Gb n Precision control is possible n Relatively low power n Problems n Programmability: OpenCL is not enough, not efficient n Low standard FLOPS: still cannot catch up to GPU -> “never try what GPU works well on” Nallatech 520N with Intel Stratix10 FPGA equipped with 4x 100Gbps optical n Memory bandwidth: 1-gen older than high end CPU/GPU interconnection interfaces -> be improved by HBM (Stratix10) 11 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba What is FPGA ? n FPGA – Field Programmable Gate Array n Reconfigurable logic circuit based on user description (low or high level) where all described logic elements are implemented to the circuit with network, gate and flip-flop n Low level language has been used so far, recently HLS (High Level Synthetic) is available such as C, C++, OpenCL • all “n” elements of computation is pipelined • circuit frequency is based on the complexity and length of each element path 12 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba AiS: conceptual model of Accelerator in Switch invoke GPU/FPGA kernsls data transfer via PCIe (invoked from FPGA) • FPGA can work both for computation and communication in unified manner • GPU/CPU can request collective or specialized application-specific communication communication to FPGA Interconnection Network 13 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba Cygnus Overlook (CCS, U. Tsukuba, April 2019) 14 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba Single node configuration (Albireo) of Cygnus cluster SINGLE Network switch Network switch NODE (100Gbps x2) (100Gbps x2) (with FPGA) • Each node is equipped with both IB EDR and FPGA-direct network CPU HCA HCA CPU HCA HCA • Some nodes are equipped with both FPGAs and GPUs, PCIe network (switch) PCIe network (switch) and other nodes are with GPUs only G G FPGA G G FPGA P P P P U U U U Inter-FPGA Inter-FPGA direct network direct network (100Gbps x4) (100Gbps x4) 15 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba Two types of interconnection network Inter-FPGA direct network InfiniBand HDR100/200 network for parallel processing (only for Albireo nodes) communication and shared file system access from all nodes IB HDR100/200 Network (100Gbps x4/node) FPGA FPGA FPGA … … FPGA FPGA FPGA comp. comp. node node comp. … comp. comp. comp. … FPGA FPGA FPGA node node node node Inter-FPGA torus network Deneb nodes Albireo nodes 64 of FPGAs on Albireo nodes (2 For all computation nodes (Albireo and Deneb) are connected by FPGAS/node) are connected by 8x8 full-bisection Fat Tree network with 4 channels of InfiniBand 2D torus network without switch HDR100 (combined to HDR200 switch) for parallel processing communication such as MPI, and also used to access to Lustre 16 shared file system. LSPANC2020@Kobe 2020/01/29 G G F F G G P P P P P P U U G G U U A A IB HDR100 x4 ⇨ HDR200 x2 CPU CPU 100Gbps x4 FPGA optical network IB HDR200 switch (for full-bisection Fat-Tree) 17 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba Specification of Cygnus Item Specification Peak performance 2.4 PFLOPS DP (GPU: 2.24 PFLOPS, CPU: 0.16 PFLOPS + FPGA: 0.64 SP FLOPS) # of nodes 80 (32 Albireo nodes, 48 Deneb nodes) => 320x V100 + 64x Stratix10 CPU / node Intel Xeon Gold x2 sockets GPU / node NVIDIA Tesla V100 x4 (PCIe) FPGA / node Nallatech 520N with Intel Stratix10 x2 (each with 100Gbps x4 links) NVMe Intel NVMe 1.6TB, driven by NVMe-oF Target Offload Global File System DDN Lustre, RAID6, 2.5 PB Interconnection Network Mellanox InfiniBand HDR100 x4 = 400Gbps/node (SW=HDR200) Total Network B/W 4 TB/s Programming Language CPU: C, C++, Fortran, OpenMP GPU: OpenACC, CUDA FPGA: OpenCL, Verilog HDL System Integrator NEC 18 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba How to open such a complicated system to application users ? n OpenCL environment is available n ex) Intel FPGA SDK for OpenCL n basic computation can be written in OpenCL without Verilog HDL n Current FPGA board is not ready for OpenCL on interconnect access n BSP (Board Supporting Package) is not complete for interconnect ➝ we developed for OpenCL access n GPU/FPGA communication is very slow via CPU memory n Our goal n enabling OpenCL description by users including inter-FPGA communication n providing basic set of HPC applications such as collective communication, basic linear library n providing 40G~100G Ethernet access with external switches for large scale systems 19 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba CIRCUS n FPGA is possible to combine computation and communication in a single framework of pipelined data stream n loop computation is pipelined according to the index n all the computation part is implemented on logic elements except buffering on memory n possible to access IP by chip provides (ex. Intel) for optical link driving n making all to be programmable on OpenCL n scientific users never write Verilog HDL -> perhaps OK with OpenCL n key issue for practical HPC cluster: OpenCL-enabled features such ash n FPGA communication link n GPU/FPGA DMA CIRCUS: Communication Integrated Reconfigurable CompUting System 20 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba Optical link router in CIRCUS Router written in Verilog HDL and packet queue and switching in CIRCUS implemented in BSP router 21 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ. of Tsukuba How to use n simple data send/receive feature on OpenCL code n OpenCL kernel and CIRCUS router is connected by Intel io-channel __kernel void sender(__global float* restrict x, int n){ __kernel void reiver(__global float* restrict x, int n){ for(int i=0; i<n; i++){ for(int i=0; i<n; i++){ float v=x[i]; float v=read_channel_intel(simple_in); write_channel_intel(simple_out, v); x[i]=v; } } } } sender/receiver code on OpenCL to call CIRCUS communication 22 LSPANC2020@Kobe 2020/01/29 Center for Computational Sciences, Univ.
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