Pass the test with SMT! In this issue, we explore the latest and greatest test and inspection processes related to PCB assembly. Our contributors from Agilent, Teradyne, ASSET Intertech and Cincinnati Sub Zero focus on ICT, HALT, HASS, and much more.

14 Brittle Failure in Pb-free BGA 42 Board Design Moves Beyond Solder Joints Reach of In-Circuit Testers by Julie Silk by Adam Ley

30 The Evolution of ICT: What’s 66 Improving Reliability Through Driving Today’s Innovations? HALT and HASS Testing by Alan J. Albee by Mark R. Chrusciel

4 SMT Magazine • September 2013

september 2013 Engineering volume 28 solutions number 9 for pcb www.smtmagazine.com manufacturing

Contents

Articles Columns 48 Development of a Methodology to 8 China Stumbles Determine Risk of Counterfeit Use, by Ray Rasmussen Part 1 by iNEMI Counterfeit Components Project Team: Harrison Miles and Mark Schaffer 12 Tin Whiskers: Phenomena and Observations by Dr. Jennie S. Hwang

76 A Study in PCB Failure Analysis: the Intermittent Connection 60 Ensuring Supply by Derek Snider Chain Reliability and Integrity by Richard Ayes 84 Doing More Than One Thing at a Time by Eric Klaver

Video Interview 87 A Look at 90 Step Stencils, Part 2: In-Circuit Test Applications and Solutions by Rachel Short

94 Deciding by the Numbers News highlights by Karla Osorno 74 Mil/Aero

82 Supplier/New Product Shorts 11 EYESHOTS: The Future of 88 Market Robotic Technology

98 SMTonline 39 Creating a 3D Image Through a Single Lens

58 Key Surface Properties of Extras Complex Oxide Films 100 Events Calendar 73 “Groovy” Hologram Creates 101 Advertiser Index & Masthead Strange State of Light

6 SMT Magazine • September 2013 column the way i see it China Stumbles by Ray Rasmussen publisher, I-Connect007

The need to see China fail verges on jingoism. As mentioned in the blog, it’s hard to know Americans distrust the Chinese model, find that what’s really going on in China. Nobody be- its business practices verge on the immoral and lieves the government’s official data, but even illegal, that its reporting and accounting standards the official reports out of China confirm a sig- are subpar at best and that its system is one of nificant slowdown in economic growth. The crony capitalism run by crony communists. On official line is now growth of 7.5%, which is a Wall Street, the presumption usually seems to significant change from the 10% average rate of be that any Chinese company is a ponzi scheme growth the country has experienced over the masquerading as a viable business. In various last two decades. With growth and exports way conversations and debates, I have rarely heard down, a housing bubble looming, international China’s economic model mentioned without pressure on currency exchange rates, rising wag- disdain. Take, as just one example, Gordon Chang es and costs, along with environmental pres- in Forbes: “Beijing’s technocrats can postpone a sures, the country is in a deep mess. Of course reckoning, but they have not repealed the laws of the official spin makes it sound like things are economics. There will be a crash.” under control. But that may not be the worst of it. A July 29 article on CNBC.com muses that The above statement is from a blog by Zach- there is actually no growth, or negative growth, ary Karabell, president of River Twice Research and that the 7.5% Chinese government official and River Twice Capital, a regular commentator number is nonsense. on CNBC, and a contributing editor for News- Robert Barbera, co-director of Johns Hop- week/Daily Beast. kins Center for Financial Economics, had the

8 SMT Magazine • September 2013 the way i see it china stumbles continues following to say about China’s economy, as he the planet. It’s an integral partner in the global makes his case that things are much worse than economic system, which makes them a “too they appear: big to fail” partner. We (the West) have creat- “If you take the top 10 trading partners with ed a monster. We allowed China to play in our China and you add up their exports to China, sandbox while making up its own rules along you’ve got data that the Chinese government the way; shame on us for not demanding bet- doesn’t get to put their hands on,” he said. “If ter controls and transparency. Having said that, you look at that data, what you’ve actually got we have trouble running our own economies, is about minus 4%, year-over-year.” demanding our own transparency and enforc- It would seem that China’s in a tough spot. ing our own rules so we really can’t have much Quite honestly, a big part of me is happy to to say about China and the way the Chinese see economic difficulties in the PRC. run things. At this point, our job is It’s payback. And, now that I to help them even more to ensure looked up the word, it’s jingois- they don’t collapse and drag the tic as well. China’s been riding rest of us down with them. Keep high for way too long, build- China’s been riding this in mind: The West sells a ing their economy on the high for “way too long, lot of equipment and systems backs of many small business- building their economy into the PRC. A collapse or sig- es here in the states, Europe, on the backs of many nificant slowdown in the Chi- Japan and elsewhere. Tens of nese economy will have a dra- thousands of businesses have small businesses here in matic effect on our industries. had to close their doors after the states, Europe, Japan The good news is that we sell Chinese competitors crushed and elsewhere. Tens of to the entire world, so prob- them with artificially low- lems in China won’t kill our priced products. The Chinese thousands of businesses industries, but a China melt- government’s artificial eco- have had to close their down (which many claim is nomic environment was so en- doors after Chinese already underway) will ripple ticing that investment flooded around the planet, weakening into the country as companies competitors crushed the fragile, global recovery. were compelled to move their them with artificially I feel for China. Not the factories to far-off China just low-priced products. government, but the people. to survive. I think I know why We all may want the Chinese the Chinese did it, but it wasn’t government to take a few lumps fair. Thousands of small business for their dastardly deeds over the people lost everything. Of course, last decade or two, but they do have our government officials allowed all this to hap- some ground to make up after their more than pen so they’re at fault, too. Enough said. Back to” 50 years of communism. When we have prob- the meltdown. lems in the West, people struggle financially, and we might see a few demonstrations and Too Big to Fail such, but with China, if they let things get out I’ve always liked this aphorism: If you of hand, hundreds of millions of lives will be at owe the bank $20,000 (or any relatively small stake. Their issues are potentially catastrophic. amount), you have a problem. If you owe the A structural collapse in China will cost millions bank $20 million, they have a problem. The sad of lives and set things back in that part of the part is that in this case, regarding China’s dif- world 10–20 years, which will affect all of us. ficulties, we, the West, have a problem. Here’s another statement from Zachary China’s rapid ascension to become the sec- Karabell’s blog: ond largest economy has put us all in jeopardy. “The consequences of a Chinese collapse, The Chinese economy is integrated economi- however, would be severe for the United States cally into just about every other country on and for the world. There could be no major

10 SMT Magazine • September 2013 the way i see it

china stumbles continues

Chinese contraction without a concomitant More Signs China’s Economy Is in Trouble contraction in the United States.” Will China’s economy crash? You should read the blog entry The U.S. China’s environment: an economic death can’t afford a Chinese economic collapse. Basi- sentence cally, he says that we may not like the idea of Will China’s Slowdown Hurt the U.S. Econ- helping China out of this mess, but we have to. omy? SMT It’s now in our best interest. It’s been my experience over the years that everything eventually comes back into balance. Ray Rasmussen is the pub- China will find its rightful place in the world lisher and chief editor for I- economy; it will come into balance. It would Connect007 Publications. He seem as if that process is fully underway. has worked in the industry since If you want to read more about the difficul- 1978 and is the former publisher ties facing China, I’ve added a few links to some and chief editor of CircuiTree interesting articles. Enjoy! Magazine. To read past columns, China’s Economy stumbles in May, growth or to contact Rasmussen, click here. seen sliding in Q2

EYESHOTS: The Future of mal biology. A multi-disciplinary team involving experts in robotics, neuroscience, engineering, Robotic Technology and psychology built computer models based on neural coordination in monkeys. Replicating human behaviour in robots has The key was recognising that human eyes long been a central objective of scientists work- move so quickly that the images produced are in ing in the field of information and communica- fact blurred, and the brain pieces together these tion technologies (ICT). blurred fragments to present a more coherent However, a major obstacle towards accom- image of our surroundings. plishing this has been controlling the interaction Using this neural information, the project between movement and vision. built a unique computer model that combined Tackling this issue was the main aim of an visual images with movements of both eyes and EU-funded project by the Universita Degli Studi arms, similar to what occurs in the human cere- de Genova in Italy, “Heteroge- bral cortex. neous 3D perception Across Vi- The project, completed in sual Fragments (EYESHOTS).” 2011, was built on the premise By simulating human learning that being fully aware of the vi- mechanisms, the project suc- sual space around you can only cessfully built a prototype robot be achieved through actively ex- capable of achieving awareness ploring it—by looking around, of its surroundings and using its reaching out and grabbing memory to reach smoothly for things. objects. Through the application of The implications of this neuroscience, the EYESHOTS breakthrough range from po- project successfully identified a tential improvements in robotic means of giving robots a sense mechanics to achieve better diagnoses and reha- of sight similar to human vision. This represents bilitation techniques for degenerative disorders an important milestone in creating a humanoid such as Parkinson’s disease. robot that can interact with its environment and The project first examined human and ani- perform tasks without supervision.

September 2013 • SMT Magazine 11 column smt perspectives & prospects Tin Whiskers: Phenomena and Observations by Dr. Jennie S. Hwang CEO, H-Technologies Group

The first in this series on tin whiskers,Tin kers. However, whiskers can also form in a wide Whiskers – Clarity First (SMT Magazine, May range of shapes and sizes, such as fibrous fila- 2013), has set the stage for subsequent topics in ment-like spiral, nodule, column and mound. this series, including this month’s focus, along Tin whiskers are often single crystals and elec- with these upcoming titles: Tin Whiskers—Po- trically conductive. They are normally brittle in tential Impact and Concerns; Tin Whiskers— nature but can be rendered ductile when very Contributing Factors; Tin Whiskers—Plausible long and thin. Theory; Tin Whiskers—Impact of Testing Con- The whiskers, having a crystalline struc- ditions; and lastly, Tin Whiskers—Preventive ture, “sometimes” grow up to a few mm long, and Mitigating Measures. but usually less than 50 µm with a few microns The metal whisker phenomenon was dis- in diameter. They “sometimes” grow from sur- covered in the late 1940s. Telephone companies faces where tin (especially electroplated tin) is reported that telephone line failures caused by used as a final finish. In this context, “some- electric short were traced to those fibrous hairy times” is a tricky word, but bears substantive whiskers. These whiskers were found to have significance, meaning it does not always follow grown from the tin plating on capacitor plates, a consistent pattern phenomenally and is seem- which perhaps was one of the first formal re- ingly elusive. ports on tin whiskers. Whiskers may grow, but they may also be self- Tin whisker reflects its coined name. It has annihilating as the electric current can fuse the long been recognized to be associated with elec- whisker if the current is sufficient. The annihila- troplated tin coating and most likely occurs tion ability varies with the whisker’s size in length with pure tin. Its appearance resembles whis- and diameter (e.g., typically more than 50 mil-

12 SMT Magazine • September 2013 smt perspectives & prospects

tin whiskers: phenomena and observations continues liamps is often required). This self-annihilating Still another experiment exhibited that whis- occurrence further contributes to the observed ker formation involved a “shelf” time. However, inconsistent or mythical nature of the events. the shelf time varies without a straightforward What are the driving forces that initiate the correlation with temperature, humidity and formation of whiskers? Can these driving forc- other environmental conditions. Data showed es be controlled practically and economically? that a moderately warm temperature served as These are million-dollar questions and deserve the “green house” that nurtured whiskering, yet a careful treatment. the temperature above 150°C inhibited whisker Before we delve into these critical questions, formation. let’s look at various findings. One experiment Furthermore, highly disparate whisker indicated that whiskers can be eliminated by growth rates have been reported, ranging from controlling the plating process in an equiva- 0.03 to 9 mm/year. And whiskers can grow even lent way to controlling stresses in materials. in a vacuum environment. The very sharp decrease in internal stress of tin So what are the driving forces and root electrodeposits was observed after plating as causes? quickly as within minutes. It is interesting to At first glance, observations and data ob- note that this fast stress release occurs regard- tained over the decades are versatile and dispa- less of whether initial stress in the deposit is rate. But as an aggregate, two points are clear: compressive or tensile. In either compressive or The driving forces are stress-related, and the tensile case, the value of stress drops to a very internal stress (compressive or tensile) plays low number, but it remains as the same type as an important role to both whisker formation the initial stress form (i.e., high initial tensile and growth. Various tests were performed un- stress reduces to much lower stress value, but der temperature cycling and electric field. The remains tensile, and high compressive stress re- lack of harmonious testing results regarding mains compressive). the effects of temperature cycling and electric It has been observed that the inclusion of or- field on whisker growth suggests the intricate ganic elements in the tin structure promote tin nature of the internal stresses engaged in the growth. Organic inclusion or the level of inclu- process. sion is in turn affected by the plating chemistry. Despite the fact that the test results are at And the bright tin has exhibited to be most sus- variation with the observations, the internal ceptible to whisker formation. Bright tin plat- stress is deemed primarily responsible for the ing chemistry is prone to creating an environ- metal whisker formation and growth. As such, ment that creates greater organic inclusion and the factors that can contribute to internal stress higher stress level in tin crystal structure. at the tin plating and the conditions that im- When comparing between Cu substrate part additional residual stress to the plating lay- and Ni substrate, Ni substrate tends to retard er during and after plating deposition are the whisker formation. This phenomenon related right places to be deliberated. SMT to inter-diffusion rate and intermetallic forma- tion correlates well with the relative diffusion Dr. Jennie Hwang is CEO of rates between Cu and Sn vs. Ni and Sn. Cu has H-Technology Group and a a higher diffusion rate into tin than the tin into pioneer and long-standing con- Cu. As a result, tin lattice is distorted and the tributor to SMT manufacturing tin lattice spacing is altered, which generates since its inception. She is the stresses to the tin plating layer. author of 350+ publications and Another observation showed that the exter- several textbooks, and an inter- nal forces exerted to tin plating, such as bend- national speaker and author on trade, busi- ing, stretching, torque, scratches, and nicks ness, education, and social issues. To read past could provide additional driving forces at the columns or contact Dr. Hwang, click here, or local regions that exacerbate whisker growth in phone (216) 577-3284. that stressed region.

September 2013 • SMT Magazine 13 feature

Brittle Failure in Pb-free BGA Solder Joints by Julie Silk BGA components during the first reflow cycle. Agilent Technologies Following the second reflow operation, some solder joint opens were detected on the BGA component which had been subjected to the SUMMARY: The increasing complexity of elec- atypical second reflow exposure. Metallograph- tronic assemblies, coupled with the transition to ic cross-sectional analysis indicated that the higher-temperature Pb-free soldering, has given rise open solder joints initially were well-formed to another case of brittle interfacial failures induced but the failure resulted from a brittle interfacial by double reflow. This article describes and charac- fracture at the package side of the solder joints. terizes electrically intermittent, brittle interfacial sol- The failure mechanism and possible root cause der joint failures in a Pb-free BGA subjected to two is discussed in terms of the combined impact of reflow cycles. stress induced by component and board warp- age and the lower inherent strength of the sol- Abstract der joint near the melting and solidification Assembly defects can effectively shorten re- temperatures. liability lifetimes in addition to lowering manu- facturing yields or creating premature service Introduction failures. This article describes and characterizes The electronics industry continues to iden- an unusual open circuit failure mechanism in tify and uncover potential performance and Pb-free ball grid array (BGA) solder joints. The reliability risks associated with the transition failure occurred during Pb-free solder assembly to Pb-free design and manufacturing. This is a of a 31 mm, 1.27 mm pitch, perimeter array, particular concern for complex product designs SAC305 (Sn3.0Ag0.5Cu) BGA. Due to design requiring high reliability and extended service constraints, it was necessary to assemble some life. The continued integration of printed cir-

14 SMT Magazine • September 2013 feature brittle failure in pb-free bga solder joints continues cuit board assemblies (PCBA) using more com- This article describes and characterizes plex packages, smaller solder joints, diminish- electrically intermittent, brittle interfacial sol- ing pitch and complex components mounted der joint failures in a Pb-free BGA subjected to on both sides of the PCBA has resulted in in- two reflow cycles. The failed BGA is a 1.27 mm creasing yield and reliability challenges. Among pitch, perimeter array with a body size of 31 those issues is the emergence of solder defects mm and SAC305 (Sn3.0Ag0.5Cu) solder balls. that appear to be related to higher assembly Due to the presence of several surface mounted temperatures due to the use of Pb-free solders. daughter card modules on the non-BGA side of These assembly defects can effectively short- the board, the BGA-side of the printed circuit en reliability lifetimes in addition to lowering assembly was soldered first. In effect, this con- manufacturing yields or creating premature ser- straint put the BGA components atypically on vice failures. the bottom-side during the second reflow. The In the mid-1990s, there were published re- solder joint failures were characterized with me- ports of brittle interface failures of surface mount tallographic cross-sectional analysis using opti- solder joints that had been subjected to a second cal microscopy and scanning electron micros- soldering operation. The first reported case oc- copy. The failure mechanism and possible root curred subsequent to a wave soldering operation1 cause are discussed in terms of the combined but there was another case reported subsequent impact of stress induced by component and to a second surface mount reflow operation2. Be- board warpage and the lower inherent strength cause brittle interfacial solder joint failures were of the solder joint near the melting and solidi- observed during a second reflow soldering oper- fication temperatures. The primary objective ation they were called “double reflow” failures. of this work is to document this new case of There have been no additional published cases double reflow failure to enable a heightened of double reflow failures since those early occur- awareness of the failure mode. These assembly rences. However, the increasing complexity of defects are difficult to detect and shorten reli- electronic assemblies coupled with the transi- ability lifetimes in addition to lowering manu- tion to higher temperature Pb-free soldering has facturing yields and creating premature service given rise to another case of brittle interfacial failures. This also emphasizes the importance failures induced by double reflow. of reviewing and checking the assembly qual-

Figure 1: PCBA BGA component descriptions, locations and reflow process.

16 SMT Magazine • September 2013 feature

brittle failure in pb-free bga solder joints continues ity and reliability of assemblies before shipping no indications of solder joint electrical opens product. on any of the other components on the PCBA. A preliminary failure analysis of Compo- Assembly and Manufacturing Details nent A at the factory suggested poor adhesion Figure 1 shows the layout of the printed of the ball to the substrate, with possible inner circuit board assembly (PCBA) that contained row solder ball separation at the component the soldering defects. Table 1 provides detailed side. The root cause was suggested as solder ball component descriptions for all the area array “de-wetting,” rather than solder joint fracture. devices assembled onto the PCBA. All the BGA Additional failed PCBAs were analyzed using components with the exception of Component transmission X-ray, dye and pry testing, and K were subjected to two reflow cycles. Due to metallographic cross sectioning. Warpage mea- the properties of the PCB, soldering was done surements of the component and PCBA were using two vapor phase reflow cycles, instead of done using thermal shadow Moiré3. Additional the more typical hot air convection reflow cy- metallographic analyses were conducted to de- cles. Following the second reflow, the assembly termine the failure mode. exhibited parametric failures at test. The para- metric failures were traced to the plastic ball Failure Analysis: grid array component (PBGA) labeled Compo- Background and Methodology nent A and designated by the red box in Fig- Solder joint quality inspections inherently ure 1. Component A, which is a perimeter array are difficult to perform on BGA components BGA, 31 mm2, 304 I/O solder balls of 1.27 mm and the detection and characterization of inter- pitch and 0.76 mm diameter, exhibited inter- mittent defects using nondestructive test (NDT) mittent solder joint electrical opens. There were methods is even more problematical. Correlat-

Table 1: Detailed BGA component descriptions for PCBA shown in Figure 1.

September 2013 • SMT Magazine 17 feature brittle failure in pb-free bga solder joints continues ing electrical parametric test data to failed in- terconnection locations likewise can be difficult with complicated product designs. These fac- tors make physical failure analysis challenging, particularly when the analysis is restricted to small sample sizes or unique product samples. The protocol used in this analysis was to per- form all the typical NDT inspections regardless of the expected outcomes prior to initiating de- structive analysis. There are a number of distinct BGA solder assembly defects that can appear symptomati- cally as intermittent electrical failures. Intermit- tent failure modes occur at either the package or board side of solder joints and they include dif- Figure 2: Optical photomacrograph of a failed ferent types of brittle interfacial fractures, varia- solder ball surface after dye and pry (DnP) testing. tions of head-on-pillow (HoP), non-wet opens, This surface has fractured between the solder ball inadequate solderability (poor joint formation), and BGA package pad (at the component side). microvoid-assisted fractures, and de-wetting. The red color on the surface is from the dye intru- All of these failure modes are caused by some sion that occurs prior to the mechanical prying. type of physical or metallurgical anomaly in the soldering process or soldered structure that in- teracts with a sufficient applied stress to cause defect initiation and ultimately failure of the penetration was observed at the component interconnection. side of all failed solder balls. A typical image of The preliminary electrical test data at the a DnP surface is shown in Figure 2. It was also contract manufacturer site indicted Compo- noted that incomplete dye penetration was ob- nent A as the single failed device on the PCBA. served at some locations. This is indicative of The test data indicated the possibility of mul- either incomplete initial solder joint formation tiple failure locations along the inner rows of or subsequent cracking through only a fraction the BGA. However, definitive identification of of the intended attachment area. failed sites could not be made solely on the ba- Figure 3 shows the a composite map of fail- sis of the electrical test data. ure locations taken from three different Com- ponent A samples overlaid on a low magnifi- Defect Detection cation transmission X-ray micrograph of the Because the suspect failure locations were package ball pattern. The pattern of indicted not in the outer rows, defect detection by vi- sites is asymmetric within the package array and sual and low magnification optical inspections is concentrated in proximity to the inner row of was unsuccessful. Transmission X-ray inspec- perimeter ball array. This inner row failure sig- tion also was unable to detect or image failed nature is atypical for many of the intermittent solder joints. This is expected since conven- failure modes discussed in the previous section. tional transmission X-ray cannot resolve fine Those types of failures tend to manifest in the cracking or thin planar defects that are noth- outer rows at the corner and near-corner loca- ing more than air gaps in the soldered struc- tions that are known to be the highest stress- ture. Consequently, destructive analyses were strain locations in BGA packages. However, initiated starting with the “dye and pry” (DnP) exceptions to this trend can be found in PBGA method. The primary objective of the DnP was packages that exhibit certain specific warpage to determine if the solder joint had failed at the signatures. It is common for warpage stresses to package or PCB side of the joint. Dye intrusion be high at the corner sites, but they also can occurred at multiple solder joint sites and dye be high in the die shadow region due to the

18 SMT Magazine • September 2013 feature brittle failure in pb-free bga solder joints continues high CTE mismatch between the pack- age laminate and the silicon die. Asym- metric failure patterns (Figure 3) are not common but when they occur they are believed to result from mechanically or thermally unbalanced structures in ei- ther the PCB or the package that affect CTE and thermal transfer. This map is a composite of failures for Component A taken from three dif- ferent PCBAs. Additional optical and SEM mi- crographs of failed solder joints at the component side are shown in Figures 4 and 5. These failures initially were diag- nosed as ball de-wet or ball drop, point- ing to the assembly process as the root cause.

Destructive Cross-Sectional Analysis Destructive cross-sectional metallo- graphic analysis was performed to pro- vide more detailed and conclusive failure mode data. The analysis was conducted Figure 3: Failure location map from dye and pry test data on Component A from a PCBA sample overlaid on a transmission X-ray image of BGA Compo- that contained suspected solder joint nent A.

Figure 4: Optical photomacrographs of various fracture surfaces after DnP testing.

20 SMT Magazine • September 2013 feature

brittle failure in pb-free bga solder joints continues

opens. The component was cross sectioned with row-by-row analysis and optical photomicro- graphs were obtained for multiple solder balls in each row. The photo- micrographs in Figure 6 show cross sections of multiple solder balls across row 20 in Com- ponent A. Row 20 is one of the inner rows of the “picture frame” of the BGA package pin dia- gram. The solder joint at pin location T20 does not appear to be formed properly and this is confirmed in the higher magnification image in Figure 5: SEM micrographs of various fracture surfaces after DnP testing. Figure 7.

Figure 6: Multiple metallographic cross sections of solder balls in row 20 of Component A.

September 2013 • SMT Magazine 21 feature brittle failure in pb-free bga solder joints continues

The initial indication from the high mag- nification photomicrograph in Figure 7 is that the T20 ball was never soldered to the BGA pad. At this low magnification, the solder ball ap- pears to be de-wetted from the pad. However, an even higher magnification photomicrograph presented in Figure 8 shows that the T20 sol- der joint actually separated from the BGA pad at the interface between the Ni-Sn intermetal- lic compound (IMC) and the bulk solder. The presence of an IMC layer and a relatively small amount of solder on the PBGA pad confirm the solder ball had been previously attached to the pad. The spherical curved surface of the bulk solder at the perimeter of the solder ball also Figure 7: A higher magnification photomicro- indicates melting. By all indications, the solder- graph (initial magnification 500X) showing a ing reaction was successful initially and the sol- defect that appears to be de-wetting at package der joint was formed properly. In contrast, the location T20 in Component A. The ball seems to top of the solder ball is flat and parallel to the be detached from the package pad. component pad indicating that a brittle solder

Figure 8: Higher magnification photomicrographs (initial magnification 1000X) adjacent to the T20 BGA pad area showing evidence of a prior successful soldering reaction on the BGA pad with subse- quent fracture at the interface between the IMC layer and the bulk solder.

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FUTUREofTHIN.com NEXT GENERATION HDI 949.587.3232 feature brittle failure in pb-free bga solder joints continues joint fracture occurred. This failure signature aration surfaces (interfaces) must be analyzed is consistent with that reported in the double carefully. In addition to the total separation reflow references1, 2 and it is suggested that a shown in the T20 solder joint, the three adja- similar failure mechanism can account for the cent balls P20, R20 and U20 shown in Figure 9 T20 solder joint failure. As the solder joint tem- exhibit similar but partial separation of the sol- perature increased and approached the melting der ball from the Ni-Sn IMC. At first glance, the temperature during the second reflow, mechan- separations marked by the dashed yellow lines ical stress in the PCBA structure was sufficient in Figure 9 look like the solder joint de-wetting to induce a brittle fracture at the IMC interface failures. However the separated areas marked by just prior to reaching the melting temperature. the dashed red lines in Figure 9, show clear in- The source of the stress could be a combination dications of cracking or fracturing rather than of CTE mismatch in the package as well as PCB de-wetting. and component warpage. The subsequent melt- It is assumed that once Component A was ing of the solder ball moments later in the re- attached to the PCBA during the first reflow flow process accounts for curved surface of the process there was a good physical and metal- solder ball and de-wetted appearance at lower lurgical connection of solder balls to the PCB magnification. and package bond pads. During the subsequent To draw a distinction between the de-wet second side reflow operation, the solder joints and brittle fracture modes, the solder joint sep- previously formed on Component A are sub-

Figure 9: Magnified cross section, 1000X, of PCBA, Component A, solder balls P-20, R-20, and U-20.

24 SMT Magazine • September 2013 feature

brittle failure in pb-free bga solder joints continues jected to an increasing thermal stress signa- be fracturing during the reflow ramp down. It ture. It is reasonable to expect the mechanical is important to recognize that stress cannot be strength of those solder joint interconnections transferred to the IMC interface as the solder to decrease as the temperature increases. Con- ball remains molten. Therefore, the solder joint currently, stress and strain are induced in the fractures would have to occur at some time solder joints due to the mismatch in after the onset of solder solidifica- coefficient of thermal expansion tion. Unfortunately, the actual (CTE) between the compos- solidification temperature is ite structures of Component The differential melting difficult to estimate given the A and the PCB laminate. The degree of undercooling in Sn- may generate“ additional 4, 5 stress in the joints could be ex- based Pb-free solders . As in acerbated by any warpage in local stresses that could the first scenario, temperature either the component or the add to the any global gradients will exist across the PCB. If these stresses exceed stresses generated by component. However during the tensile strength of the sol- cooling the joints in the outer der joint, fracture will occur differences in component rows of the perimeter array along the weakest interface. At and PCB CTE and warp- are expected to solidify be- higher temperatures near-re- age. Once the balls on the fore those in the inner rows. flow, the weakest link typically perimeter of the package This differential solidifica- is the IMC/solder interface as tion could also generate local indicated in Figure 8. Based on melt, all the stress in the stresses that could add to the those cross sections, it is rea- package is transferred stresses generated by differ- sonable to conclude that frac- to inner unmelted balls, ences in component and PCB ture results from the increas- which could result in CTE and warpage. ing stress on the component fracture at those sites. The first scenario, fracture solder joints during the second during the reflow ramp up reflow process due to a combi- prior to solder melting, seems nation of CTE mismatch and the more plausible because it is easier component and PCB warpage. to envision stress being transferred to There are two possible scenarios to consid- and concentrated at the inner, unmelted joints. er. In the first scenario, the solder joint could” Clearly, the stress distribution and the relation- be fracturing during the reflow ramp up. This ship between peak stress, temperature, and sol- could be happening at any point before the sol- der solidification must be complex so fracture der begins to melt. Stress of course cannot be during cooling may be possible. transferred to the IMC interface once the sol- Subtle differences in local solidification and der has melted. Although vapor phase reflow is stress could account for the observed inner row rapid and provides more uniform heating than failures and the variations in the extent of the forced convection IR reflow, temperature gradi- cracking from site to site along the inner row. ents will exist across components. Solder joints The asymmetric failure pattern could be caused in the outer rows of the perimeter array are ex- by thermo-mechanical imbalances in the pack- pected to reach the solder melting point a fi- age and PCB. The fact that fractures occur only nite time before the inner rows. The differential at the package side of the joints is most likely melting may generate additional local stresses related to the fact that a solder joint formed on that could add to the any global stresses gener- a non-solder mask defined Cu pad (as on the ated by differences in component and PCB CTE PCB) is more resistant to tensile and shear load- and warpage. Once the balls on the perimeter ing than a solder joint formed on a solder mask of the package melt, all the stress in the package defined Ni plated pad (as on the package). is transferred to inner unmelted balls, which It is inexplicable that only a single BGA could result in fracture at those sites. component on the entire PCBA is affected by In the second scenario, the solder joint could the double reflow failure mechanism. It can be

September 2013 • SMT Magazine 25 feature brittle failure in pb-free bga solder joints continues

Table 2: Thermal shadow Moiré measurements showing maximum warpage across the overmolded region of BGA Component A and the bottom side of the PCBA opposite Component A.

speculated that this particular BGA component an entire assembled PCBA. A thermal shadow has sufficient dynamic warpage or a uniquely Moiré system was used to characterize warpage vulnerable warpage signature with tempera- over a temperature range intended to simulate ture that precipitates the failures. Cross-section- a solder reflow profile. Shadow Moiré uses geo- al analysis of several other BGA components metric interference between a reference grating showed no evidence of brittle fracture. It is pos- and its shadow on a sample to measure relative sible that brittle fracture occurs to a lesser extent vertical displacement at each pixel position in in some of the other BGA components but it was the resultant interference pattern image. The never found to manifest as a failure nor detected thermal chamber is designed to enable mea- in the failure analysis done on these parts. surements to be made during both heating and cooling cycles. Shadow Moiré Dynamic Warpage Dynamic warpage measurements were made Measurements on Component A and on the bottom side of the Dynamic warpage was measured on an un- PCBA. Table 2 presents the warpage data as a attached (stand-alone) Component A and on function of temperature from room tempera-

Figure 10: A warpage displacement map across Figure 11: A warpage displacement map for the the overmolded area of Component A measured PCB footprint matching Component A. The mea- during temperature ramp up at 220°C. surements were made during temperature ramp up at 220°C.

26 SMT Magazine • September 2013 feature

brittle failure in pb-free bga solder joints continues ture to reflow at 245°C and back down to 90°C. warpage can appear with deviations in warpage These data show a maximum displacement (∆) as small as a few mils8. In the case of BGA dou- of >4 mils as the package ramps up to the solder ble reflow, the magnitude of the warpage and melting point (220°C) and as the package be- induced thermal stress may not be the primary gins to ramp down to solder solidification. Ex- consideration. The more important factor may amples of three-dimensional warpage maps are be the strength of the solder interconnection at shown in Figures 10 and 11. Figure 10 shows higher temperatures close to the melting and the warpage map for the overmolded region of solidification points of the solder. Consequent- the package. This is the region of the package ly, it is conceivable that a small stress applied to that contained the failures (Figure 3). This mea- the solder joint at high temperature when the surement was made during temperature ramp joint has its lowest strength could cause a brittle up at 220°C. The maximum displacement over interfacial fracture. this surface is approximately -2.0 mils with out-of-plane bending in opposite corners (red Corrective Action regions). Figure 11 shows a comparable warp- The obvious path for elimination of the fail- age map for the PCBA in the region of ures in this design was to subject the the Component A footprint. The BGA-side of the PCBA to only a maximum displacement of the single reflow pass. This correc- PCB is +2.2 mils over this sur- tive action was implemented face. Therefore, the maximum The root cause analysis successfully. The soldering of net displacement (warpage) of and subsequent“ successful the heavy daughter card mod- Component A relative to the ules on the non-BGA side of PCB is 4.2 mils. corrective action indicate the board was achieved by The thermal shadow Moiré that in order to prevent modifying other aspects of data in Table 2 indicate a net double reflow defects, the assembly process. displacement or warpage of The root cause analysis Component A relative to the BGA components should and subsequent successful PCB of approximately 4 mils not be subjected to corrective action indicate that during heating in advance of in order to prevent double melting or during cooling be- multiple reflow passes. reflow defects, BGA compo- fore solidification takes place These double reflow nents should not be subject- (shaded Max. ∆ cells in Table defects could be another ed to multiple reflow passes. 2). It must be acknowledged These double reflow defects that there are uncertainties manifestation of warpage- could be another manifesta- in interpreting these displace- related assembly defects tion of warpage-related assem- ment measurements. First, that are increasing bly defects that are increasing these measurements may not across the industry. A risk as- reflect the component and across the industry. sessment is recommended PCBA behavior accurately as it whenever double reflow as- would occur during an actual fac- sembly of BGA components is tory reflow cycle. More importantly, proposed. The assessment should the amount of warpage needed to induce solder include evaluation of dynamic warpage data for joint fracture is unknown. A similar amount of” the BGA components used in the design. warpage can create other serious BGA defects In the current analysis, using vapor phase such as head-on-pillow (HoP), but HoP is a com- reflow may actually have mitigated the ef- pletely different failure mode6, 7. fects of warpage. If the more conventional IR In most applications, 4 mils of warpage convection reflow had been used, it may have would be considered acceptable because defects exacerbated the component and PCB warpage like HoP and dropped ball would not occur. On and increased the severity of the double reflow the other hand, solder assembly defects due to defects.

September 2013 • SMT Magazine 27 feature brittle failure in pb-free bga solder joints continues

Conclusions References A comprehensive failure analysis was per- 1. C. Hallmark, K. Lawson, and C. Tulkoff, formed on a complex electronic printed circuit “Double Reflow: Degrading Fine Pitch Joints in board assembly (PCBA) that exhibited intermit- the Wave Solder Process,” Proceedings of Nep- tent open circuit electrical failures following con, February, 695-705, 1994. Pb-free solder assembly. The following observa- 2. G. M. Wenger, D. A. Machusak, R. E. tions and conclusions are drawn from the re- Woods, G. P. Tashjian, and T. M. Hallworth, sults of the failure analysis. “Double Reflow: The Stress Fracture Reliability Problem of the ’90s,” Proceedings of SMI Con- • The root cause of the intermittent open ference, 640-645, 1995. circuit failures was brittle solder joint fractures 3. JESD22-B112, “High Temperature Package at the interface between the Ni-Sn (nickel-tin) Warpage Measurement Methodology,” JEDEC intermetallic compound (IMC) and the bulk Solid State Technology Association, 2005. solder at the package side of the solder joint. 4. Sung K. Kang, Moon Gi Cho, Paul Lauro, The solder joint fractures could not be detected and Da-Yuan Shih, “Critical Factors Affecting until destructive cross-sectional analysis was the Undercooling of Pb-free, Flip-Chip Solder performed. Bumps and In-situ Observation of Solidifica- tion Process,” Proceedings of 57th ECTC, 1597- • The fractures developed in a Pb-free pe- 1603, Reno, NV, 2007. rimeter plastic ball grid array (PBGA) following 5. R. Kinyanjui, L. P. Lehman, L. Zavalaji, exposure to a second reflow cycle. The failure and E. Cotts, “Effect of sample size on the so- signature is characteristic of the so-called dou- lidification temperature and microstructure of ble reflow failure mechanism that has been re- SnAgCu near eutectic alloys,” J. Mater. Res., ported very sparingly in the literature over the Vol. 20, No. 11, 2914-2918, 2005. years. This may be the first reported example of 6. Dudi Amir, Raiyo Aspandiar, Scott this failure mechanism in a Pb-free solder as- Buttars, Wei Wei Chin, and Paramjeet Gill, sembly. “Head – and – Pillow SMT Failure Modes,” Proceedings SMTAI, 409-421, San Diego, CA, • The most likely scenario for describing the 2009. failure sequence is that the solder joints fracture 7. Russell Nowland, Richard Coyle, Peter just prior to solder melting during the 2nd re- Read, and George Wenger, “Telecommuni- flow. In this scenario, the solder joint strength cations Case Studies Address Head-In-Pillow is at a minimum prior to melting and brittle (HnP) Defects and Mitigation through Assem- solder joint fractures are induced by a complex bly Process Modifications and Control,” Pro- combination of CTE and warpage stress on the ceedings of IPC APEX 2010, S15-01, Las Vegas, solder joint during its exposure to the second NV, 2010. reflow cycle. Thermal gradients across the BGA 8. Li Li, Ken Hubbard and Jie Xue, “Improv- package during heating may contribute to the ing Board Assembly Yield through PBGA Warp- stress. age Reduction,” Proceedings ECTC 2009, 949- 953, San Diego, CA, 2009. • The brittle fractures were eliminated by process changes that allowed the BGA-popu- lated side of the PCBA to be exposed to only a Julie Silk is the Environmental single reflow cycle. Compliance Program Manager for the Electronic Measurements Acknowledgements Group of Agilent Technologies. The authors would like to thank Neil Hub- She has worked for Hewlett- ble of Akrometrix for the thermal shadow Moi- Packard and Agilent Technolo- ré measurements and helpful technical discus- gies for over 30 years. sions. SMT

28 SMT Magazine • September 2013 feature

The Evolution of ICT: What’s Driving Today’s Innovations? by Alan J. Albee ultra-low voltage components, the variable test Teradyne Inc. requirements of different product applications, the varying test philosophies of different market SUMMARY: ICT systems have evolved greatly segments and different manufacturing regions, since their introduction three decades ago. In fact, and the demanding throughput requirements the newest ICT systems might be termed “electri- of high-volume production facilities. cal test controllers” because some now support in- This article highlights how in-circuit test circuit, boundary scan, PLD programming, cluster systems have evolved in recent years to include and functional testing techniques. innovations and advancements to address these challenges and trends. Topics covered include Abstract boundary scan and functional test integration Many manufacturers employ one or more strategies, advancements in vectorless test tech- in-circuit test (ICT) systems in their PCB manu- niques, incorporation of limited access electri- facturing facilities to help them detect manu- cal test techniques, test strategy analysis tools, facturing process and component defects. These high-accuracy pin drivers and sensors, concur- bed-of-nails electrical test systems are highly rent test throughput improvement options, valued for providing the qualities of simple pro- scalable test performance capability architec- gram generation, high fault coverage, fast test ture, and program development accelerators. throughput, low false fail rates, and exceptional This paper describes how these new ICT diagnostic accuracy as compared to other avail- advancements contribute to lowering overall able test and inspection techniques. manufacturing test costs by improving the fault Advancements in PCB technologies, along coverage, reliability, and throughput of in-cir- with changing test philosophies and manufac- cuit production tests. turing business models in recent years have cre- ated new and diverse requirements for manu- Introduction facturers of in-circuit test systems. Particular When in-circuit test systems were first in- challenges that ICT manufacturers have had to troduced in the late 1970s, the world was a dif- address include the erosion of test point access ferent place. PCB assemblies used through-hole in certain product sectors, the progression of technologies, spacing between pins was typi-

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Legendary manufacturing, service and engineering. www.dragoncircuits.com | [email protected] | 972.790.7610 feature the evolution of ict: what’s driving today’s innovations? continues cally 100 mils, components were only placed gate faults from internal nets to externally on a single side, the largest components rarely observable test points. Finally, in-circuit test had more than 14 pins, the prevalent voltages systems provided faster test throughput and used to power the boards were 5, 12, and 15 exceptional diagnostic accuracy that were not volts, manufacturing occurred in the highly possible with functional tests. All these benefits industrialized regions where the products were resulted in fast adoption of ICT systems, and consumed, and manufacturing test consisted they quickly eclipsed complex functional test primarily of the execution of complex and time systems and became the test system of choice consuming functional tests. for most high-volume manufacturers. The introduction of in-circuit test systems In-circuit test systems have had to evolve revolutionized the PCB manufacturing process throughout the years to keep up with the de- by changing the test paradigm from testing the mands of ever-changing PCB technologies, the functionality of the board to test- advance of global manufacturing ca- ing the functionality of the parts pabilities, and the diversity of test- along with the integrity of the ing philosophies for different assembly process. In-circuit test The real breakthrough product and market segments. systems accomplished this by with in-circuit“ testing was using a bed-of-nails test fixture Addressing Erosion of to make electrical contact to the benefits it provided Test Point Access every net on the PCB allowing compared to traditional The cornerstone of tradi- each component to be indi- functional tests. Test tional in-circuit testing has vidually stimulated and mea- generation was greatly been the ability to gain elec- sured. With such electrical test trical test access to all of the access and innovative guard- simplified because test nets on the PCB using electri- ing and voltage forcing tech- developers no longer cal test probes. In-circuit test niques—which allowed each had to understand the providers use comprehensive component to be tested indi- CAD analysis and probe place- vidually without the influence functionality of the ment solutions to analyze cir- of its surrounding parts—ICT board, and they could cuit board designs and gener- systems could quickly detect automatically generate ate wiring instructions that shorted and open pins, miss- fixture fabricators use to as- ing components, incorrect an- programs in days, semble bed-of-nails in-circuit alog component values and tol- not weeks. test fixtures. erances, and faulty digital com- It is becoming increasingly ponent logic. The theory behind more challenging to find probe in-circuit testing is that manufactur- placement solutions that provide full ers can be confident that the board will operate electrical test access to all the nets on the PCB. correctly if they verify that all the components” This is because shrinking packaging technolo- are operating correctly and have been properly gies, greater IC integration and functionality, assembled. higher pin counts, faster I/O speeds and reduced The real breakthrough with in-circuit test- product footprints have led to ultra-miniatur- ing was the benefits it provided compared to ization. To support this trend, manufacturers traditional functional tests. Test generation was are designing increasingly complex HDI boards greatly simplified because test developers no that make use of blind and buried vias, smaller longer had to understand the functionality of tracks with tighter spacing and with less cop- the board, and they could automatically gener- per available on the board surface for electrical ate programs in days, not weeks. The quality of test access. This trend is more pronounced for the test coverage also improved with ICT, be- high-volume consumer products which place a cause direct access to every net eliminated the premium on small size, fast performance, and functional test complexity of trying to propa- low power consumption.

32 SMT Magazine • September 2013 feature

the evolution of ict: what’s driving today’s innovations? continues

One way that designers and fixture fabrica- Micro-access technologies allow manufactures tors have addressed these challenges is through to get electrical test access to test points that are the use of more advanced probe technologies. as small as the signal traces themselves; howev- Traditional ICT probe technology which con- er, their use is only viable on signal traces that sists of a small probe contacting a larger test pad can be accessed from the top or bottom layer of target on the unit under test (UUT) is restricted the UUT and the micro-access test points must to a target diameter of .024 inches with center be spaced appropriately to avoid conflict with spacing of .0395 inches between probes. New the large head probes that are used in the test highly accurate probe fixturing technologies fixture. developed by the fixture fabricators are avail- Despite the advances in ICT fixturing tech- able that make it possible to design ICT fixtures nology, manufacturers sometimes find it chal- that can reliably contact test points as small as lenging to get complete physical test access to .012 inches with pitch of .020 inches1. the boards they are testing. The effectiveness To provide access to even smaller test points, of ICT diminishes as physical test access is lost, manufacturers can use micro-access test tech- so some ICT test systems have evolved to aug- nologies. Instead of using a small point test ment physical test access with virtual test ac- probe in the fixture to contact a large test pad cess techniques. Table 2 shows the reduced ac- on the board, micro-access test technologies use cess tools that are available on some ICT test a large head test probe in the fixture to contact a platforms. small test point on the board. Micro-access test The tools highlighted in Table 2 extend the technique concepts have been around since the capabilities of the ICT system allowing manu- 1990s, and Table 1 describes the general con- facturers to still maintain high fault coverage cepts behind five different implementations. even on boards that do not have full physical

Table 1: Micro-access comparison matrix.

September 2013 • SMT Magazine 33 feature the evolution of ict: what’s driving today’s innovations? continues

Table 2: Limited access tools augment ICT. test access. It must be noted, however, that the requires. The amount of power a transistor re- tradeoff for using these tools is often an increase quires is calculated using the formula in programming complexity, less accurate di- Power = Frequency x Capacitance x Voltage2. agnostics at the repair station and longer test execution times. Given these tradeoffs, it is in Designers have discovered that the most ef- the best interest of designers and manufacturers fective way to reduce the power requirements whenever it is possible to provide physical test for their products and satisfy the reduced pow- access to every pin they can. er consumption and environmental concerns of their customers is to lower the voltages at Addressing Ultra Low Voltage Technologies which they operate. As a result, many boards As Moore’s Law predicted, the number of now contain devices that operate with a com- transistors in integrated circuit packages has bination of low voltage logic levels of 1.8V and approximately doubled every two years over below. The challenge for many in-circuit test the last two decades. The greater the number systems is that their pin electronics were origi- of transistors in a package the more power it nally designed when 5V was the predominant

34 SMT Magazine • September 2013 feature the evolution of ict: what’s driving today’s innovations? continues logic technology and many of them do not The factors that drive these expectations in- have the required accuracy to test these ultra- clude: low voltage components accurately, reliably, and safely. • PCB complexity—simple or complex Some in-circuit test systems have evolved to board; low or high pin count; full or limited test address this low voltage testing challenge by up- access? dating their digital pin electronics with dramati- • Product cost—low margin consumer prod- cally improved drive and sense accuracy (as low uct; high cost server, communication, or mili- as 15mV). Other capabilities added to ensure safe tary/aerospace board? and reliable testing include real-time backdrive • Reliability and regulatory obligations— current measurement and control features (to what safety standards are required for automo- prevent devices from being harmed by electrical tive, medical, and industrial equipment? over-stress conditions); automatic driver verifi- • Manufacturing strategy—outsourced vs. cation (to guarantee that drivers reach their pro- internal manufacturing, multi-site manufactur- grammed logic levels); dual-level sensor thresh- ing, frequent manufacturing location changes. olds (to ensure device output drivers are within • Product volume and mix—high mix/ published specifications); and programmable low volume, dedicated high-volume produc- per-pin logic levels (to support devices that re- tion lines, automated vs. operator-driven quire multiple independent logic levels)10. operation. In-circuit test systems equipped with these • Manufacturing skill levels—experienced advanced digital test capabilities can confi- vs. inexperienced developers and operators, dently perform powered-up digital testing of trained vs. untrained personnel. the latest low voltage technologies. However, if manufacturers are using in-circuit test equip- All these factors combine to place conflict- ment that do not have these advanced ing demands on ICT systems. Low- digital test capabilities they may margin manufacturers demand not be able to reliably or safely low-cost ICT. Manufacturers of test low voltage components, Untrained operators high-reliability, highly complex or they be forced to resort to demand simple operation; products demand high fault unpowered vectorless test “ coverage and high pin-count strategies of their low voltage highly skilled test capacity. Untrained operators digital parts which are slow- engineers demand demand simple operation; er, more expensive, and less powerful programming highly skilled test engineers comprehensive11. demand powerful program- capabilities. High-volume ming capabilities. High-volume Addressing Diverse manufacturers demand manufacturers demand ever Test Requirements ever higher test higher test throughputs, while In addition to evolving to manufacturers using outsourc- meet the technology require- throughputs, while ing business models demand ments previously described, manufacturers using equipment compatibility. To manufacturers of ICT systems outsourcing business further complicate matters for have had to evolve to meet ICT vendors, different market the shifting testing philoso- models demand segments and geographic re- phies and business economic equipment compatibility. gions implement different test drivers of their customers. ICT philosophies. vendors have struggled to satisfy Historically, ICT vendors have the demands of manufacturers who addressed these conflicting demands specify different requirements for their ICT sys- with different classes of ICT systems. Manufac- tems and who have different expectations as to” turing defect analyzers offered low price and what they need the system to do. simple test operation, but provided limited

36 SMT Magazine • September 2013 feature

the evolution of ict: what’s driving today’s innovations? continues test capabilities and low fault coverage. High- Some ICT vendors have evolved their tes- performance in-circuit testers offered extended ters into highly scalable systems that satisfy di- test capabilities and high fault coverage, but verse test requirements in a single compatible were expensive and complex to program. In the platform. These systems can support multiple middle were a variety of standard in-circuit test pin board types, independent hardware op- systems that offered more performance than an tions and software plug-ins that can be used to MDA class system at a lower price than high- expand the capabilities of the tester. Figure 1 performance class ICT systems. shows how this approach can be used by manu- Given the different classes of test systems, facturers who can buy only the test capability many manufacturers now have production they need and grow or reduce test capabilities floors with multiple incompatible classes of without changing the tester. The benefits in- ICT systems, often from different ICT vendors. clude lower training and programming costs There can be a hidden cost to this multi-system because operators only have to learn one test test strategy because it increases system train- system and develop one test program, higher ing and service costs, increases program main- equipment utilization rates because a single test tenance costs, and reduces flexibility in test system can be used for multiple test applica- equipment utilization. tions and higher equipment value because the If a manufacturer decides to only use an tester can be configured as an MDA+ system MDA class tester, then they may not be able to all the way to a high-performance digital ICT adequately test complex PCB assemblies due to system. To facilitate test program compatibility its limited capabilities. On the other hand, if a and equipment utilization, the test executive on manufacturer decides on a high-performance these ICT systems will adapt to run only those ICT platform solution, it can be overkill for tests in the program that can be supported with simple PCB assemblies where the high-per- the given hardware and software configuration formance ICT features are not always needed of the target tester. No more need to create cus- and the program development requires higher tom test programs designed for the configura- skilled operators. tion of each tester on your production floor!

Figure 1: Scalable ICT platform satisfies diverse manufacturing requirements.

September 2013 • SMT Magazine 37 feature the evolution of ict: what’s driving today’s innovations? continues

High-Volume Manufacturing Requirements using dual-well fixtures so there is no delay be- High-speed assembly equipment continues tween testing boards, however the highest vol- to improve resulting in ever faster beat rates on ume can be achieved by eliminating the test the production line. The beat rate for today’s operator and placing the ICT system in an au- high-volume production lines is often less than tomated line. Some ICT vendors sell their ICT 30 seconds. In-circuit testers can become the subsystems as standard 19” rack mount compo- bottleneck in the production line when their nents so that they can be easily integrated into test times exceed the beat rate of the assembly the automated handler solution that is preferred equipment and place a limit on the number of by the manufacturer. boards that can manufactured per hour. Finally, some manufacturers provide test When this happens manufacturers can throughput analysis and optimization software choose to add additional test equipment to in- that can modify test parameters to ensure that crease their test capacity or they can the test program is optimized for the reduce test times by eliminating fastest test throughput. This soft- tests until the test time is below ware reduces test times by an av- the target beat rate. Neither of Some ICT systems have erage of 15% and identifies test these options is considered inefficiencies in the program ideal as adding additional evolved“ to support that could be corrected to fur- test equipment is expensive, concurrent testing ther reduce test times. requires extra test fixtures, and is not always possible be- of more than one Conclusion cause production facilities of- component at a time. ICT systems have evolved ten have limited floor space. This is accomplished by to address the technology and Eliminating tests requires ex- business challenges of mod- tra program maintenance and duplicating instrumenta- ern PCB manufacturing, with reduces the amount of defects tion in the test system capabilities advancing greatly that can be detected by the since ICT’s introduction. Re- ICT system. so that the test executive duced access test techniques, A better approach is to in- can test multiple compo- integration of boundary scan crease the execution speed of nents in parallel (typically and embedded testability the tester until it no longer is tools, advanced pin electron- the bottleneck on the produc- on boards manufactured ics capable of testing low volt- tion line. Some ICT systems as part of a panel). age technologies, concurrent have evolved to support con- test capabilities, functional current testing of more than one test capabilities, and scalable component at a time. This is ac- test system configurations have all complished by duplicating instrumentation in combined to extend the life of ICT systems and the test system so that the test executive can” make them one of the tools that is still most test multiple components in parallel (typically valued by high-volume PCBA manufacturers. on boards manufactured as part of a panel). Considering how the in-circuit tester has How concurrent test is implemented differs for evolved and all of the electrical test capabilities different ICT vendors and the amount of con- that do not require actual physical test access, it currency depends on many factors, but ICT sys- may be time for the industry to stop categoriz- tems with concurrent test features can generally ing these test systems as in-circuit testers. It may test 1.5–2 times faster than a standard ICT tes- be more appropriate to start categorizing these ter. versatile test systems as “electrical test control- In addition to increasing the test execution lers” because the most capable ones can support speed, high-volume manufacturers also try to in-circuit, boundary scan, PLD programming, reduce or eliminate the board handling times. cluster and functional testing techniques all in This can be done on non-automated lines by a single consolidated test platform. SMT

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the evolution of ict: what’s driving today’s innovations? continues

References 8. Michael J. Smith, “Integrated Electrical 1. Gary St. Onge, “Zoom Fixtures for ATE,” Test Within the Production Line,” IPC/APEX IPC/APEX Conference, April 2010. Conference, Feb. 2012. 2. David Boswell, “Surface Mount & Mixed 9. Robinson/Verma, “Optimizing Test Strat- Technology PCB Design Guidelines,” Technical egies During PCB Design For Boards with Lim- Reference Publications Limited, 1990, pg. 28. ited ICT Access,” Proceedings of the Telecom 3. Vaucher, C, “Analog/Digital Testing of Hardware Solutions Conference, May 2002. Loaded Boards Without Dedicated Test Points,” 10. Alan J. Albee, “Issues & Challenges of Proceedings of the International Test Confer- Testing Modern Low Voltage Devices on Con- ence, IEEE 1996, pp. 325-332. ventional In-Circuit Testers,” IPC APEX EXPO, 4. Ray P. Prasad, “Surface Mount Technolo- 2004. gy – Principles and Practice,” Chapman & Hall, 11. Albee/Smith, “Vector vs. Vectorless ICT 1997, sec. 332. Techniques,” Evaluation Engineering, March 5. Doraiswamy/Grealish, “Implementation 2011. of Solder-bead Probing in High Volume Man- ufacturing,” Proceedings of the International This paper was originally presented at IPC Test Conference, IEEE 2006, Paper 5.4. APEX EXPO 2013. 6. Anthony J Suto, “Micro Access Technolo- gies on PCB Assemblies,” SMT Magazine, August 2011. 7. Anthony J Suto, “Virtual Access Tech- nique Augments Test Coverage on Limited Ac- Alan J. Albee is product cess PCB Assemblies,” IPC/APEX Conference, manager at Teradyne. Feb. 2012.

Creating a 3D Image or another, but unless you also move your head from side to side, it’s difficult to gain much sense Through a Single Lens of objects’ relative distances,” Crozier says. “If your viewpoint is fixed in one position, as a mi- Researchers at the Harvard School of Engi- croscope would be, it’s a challenging problem.” neering and Applied Sciences (SEAS) have devel- Crozier and graduate student Antony Orth es- oped a way for photographers and microscopists sentially compute how the image would look if it to create a 3D image through a single lens, with- were taken from a different angle by relying on out moving the camera. the clues encoded within the rays of light enter- Published in the journal Optics Letters, this ing the camera. improbable-sounding technology relies only “Arriving at each pixel, the light’s coming at on computation and mathematics—no unusual a certain angle, and contains important informa- hardware or fancy lenses. The effect is the equiva- tion. Cameras with all kinds of new hardware, lent of seeing a stereo image with microlens arrays and absorbing one eye closed. masks can record the direction of Principal investigator Kenneth the light, and that allows you to B. Crozier, John L. Loeb Associate do some very interesting things, Professor of the Natural Sciences, such as take a picture and focus explains. it later, or change the perspective “If you close one eye, depth view. We asked, can we get that perception becomes difficult. functionality with a regular cam- Your eye can focus on one thing era, without extra hardware?”

September 2013 • SMT Magazine 39 SMTAI Conference and Exhibition in Ft. Worth, October 13–16 The SMTAI Conference and Exhibition in On Tuesday, Keynote Speaker Bob D. Du- Ft. Worth, Texas beginning Sunday, October 13 Laney, Lockheed Martin, USAF Major Gen- promises the latest information for attendees eral (Ret), officially opens the event, which is who would like to reduce defects and control followed by technical sessions, free spot- processes. This international technical confer- light sessions, free lunch, poster session and ence will offer tutorials, tech sessions, spotlight certification seminars all day Tuesday and sessions, technical committee meetings, and Wednesday. more. The Electronics Exhibition, featuring more The event kicks off on Sunday with tutorial than 150 exhibiting companies, will be open sessions in the morning and after- Tuesday and Wednesday, October 15 noon, and is followed on Monday and 16, from 9 a.m. to 5 p.m. For with more tutorial sessions, AIMS/ a complete listing of exhibitors, Harsh Environment Symposium, click here. and Evolving Technologies To register for the event, summit. click here.

40 SMT Magazine • September 2013 SUBSCRIBE

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GOOD FOR THE INDUSTRY www.iconnect007.com feature Board Design Moves Beyond Reach of In-Circuit Testers by Adam Ley ASSET InterTech

SUMMARY: Although intrusive test technolo- gies on the manufacturing floor such as ICT have been effective in the past, recent advancements in basic electronic technologies are disrupting legacy test methods. Now, non-intrusive board testing is replacing the intrusive types, such as in-circuit testing.

In just the last five years, the advancements in microprocessors, communications chips, memory and other base technologies have been phenomenal. Circuit board design and assem- bly techniques have changed accordingly to Specifically, today’s sophisticated board accommodate the many breakthroughs in base design techniques do not provide physical ac- technologies. Consequently, these new design cess for probes, which is a requirement of ICT. and assembly techniques are wreaking havoc What’s more, system and board designers don’t on the test coverage previously provided by in- want to provide ICT access. At best, designing in trusive test technologies like ICT. tests pads to give probe access to a circuit board Fortunately, non-intrusive board test (NBT) could slow system performance to unacceptably has emerged as a more cost-effective test meth- low levels; at worst, the system’s ability to func- odology for the manufacturing floor. Certainly, tion as specified could be placed in jeopardy. ICT and other intrusive test technologies, such From a business perspective, ICT systems as manufacturing defect analyzers (MDA) and are expensive to procure, maintain and operate. flying probe testers (FPT), will continue to have Complex bed-of-nail test fixtures are time-con- their place, but they soon could be relegated to suming to produce and costly. Many new prod- special case testing or for testing rudimentary uct introductions have been delayed because circuit board designs. NBT offers better test cov- engineers had no other choice but to wait weeks erage and a lower cost structure. at a time for ICT test fixtures to be produced

42 SMT Magazine • September 2013 feature board design moves beyond reach of in-circuit testers continues for each re-spin of a board design. The alterna- ter spacing) to .3 mm. This seemingly small shift tive is NBT, a suite of technologies that provide has a significant effect on probe access. With a comparable or better test coverage at less cost .4 mm ball pitch, there is enough room for a and are software-driven, not hardware-intense. via—those vertical interconnects that span mul- tiple layers on boards—to be routed through the Shrinking ICT Test Coverage circuit board and connected to the chip by way ICT test coverage is shrinking for a variety of a high-density interconnect (HDI). But fine of technical reasons. pitch .3 mm BGAs do not allow enough room on the board for a via except directly into a ball Circuit Density or pad on the device (Figure 1). To accommo- Increasing chip and board densities have lim- date smaller device geometries and greater cir- ited the physical space available for test probes. cuit densities, new circuit board manufacturing For example, the geometry of chips in ball grid methods like microvias for HDI and others have array (BGA) packaging has shrunk considerably, been adopted. These board design and assembly dropping from .4 mm ball pitch (center-to-cen- methods have made physical access for ICT even

Figure 1: Circuit density and its effects on probe placement.

44 SMT Magazine • September 2013 feature

board design moves beyond reach of in-circuit testers continues more difficult to come by since the surface features, if any, are much too small to access by test probes.

Probe-Induced Strain When an ICT bed-of-nails fixture places a probe on a cir- cuit board, strain is exerted on the board. This strain, or “flexure,” can create defects in solder joints (Figure 2). In fact, this ICT-induced strain can be much greater than any force placed on a board when it’s installed and in operation in the field. It is ironic that Figure 2: Flexure, the strain resulting from the force of ICT probes, ICT, which is attempting to can actually cause the structural failures they are trying to detect. find defects, can actually pro- duce the defects it is trying to detect.

Circuit Speed Double Data Rate memory (DDR) The speed at which signals travel across DDR1 400 MT/s traces on circuit boards is constantly increasing DDR2 1.066 GT/s to keep up with the increasing performance of DDR3 2.133 GT/s chips and to support the huge data throughput DDR4 4.266 GT/s rates that are typical of today’s networked sys- Peripheral Component Interface Express (PCIe) tems (Table 1). As the speed of a bus approaches 5 gi- PCIe 1 2.5 GT/s gatransfers per second (GT/s), the traces on a PCIe 2 5 GT/s board become very sensitive to capacitive cou- PCIe 3 8 GT/s pling, electromagnetic interference (EMI) and PCIe 4 (2014/2015) 16 GT/s electromagnetic compliance (EMC) concerns. Universal Serial Bus (USB) In fact, placing any sort of test pad on one of USB 1.1 - Low-Speed 1.5 MT/s these high-speed buses could disrupt bus sig- USB 1.1 - Full-Speed 12 MT/s naling to the point where system performance is jeopardized. Bringing an internal route to USB 2 (Hi-Speed) 480 MT/s a surface layer to connect to a test pad would USB 3 (SuperSpeed) 5 GT/s create an un-terminated stub on the route, in- Serial Advanced Technology Attachment (SATA) ducing signal reflections and ringing, and pos- SATA 1 1.5 GT/s sibly reducing bus speeds. For these and other SATA 2 3 GT/s reasons, many reference designs provided and SATA 3 6 GT/s recommended by the suppliers of high-speed chips such as Intel and others strictly prohibit Direct Media Interface (DMI) the placement of test pads on high-speed buses. DMI 1 (2004) 2.5 GT/s Fewer test pads mean less test coverage for ICT. DMI 2 (2011) 5 GT/s In addition, many board designs limit or to- tally restrict routes on the surface layer (Figure Table 1: Escalating speeds on several popular 3). Sometimes a circuit board’s surface will func- high-speed buses.

September 2013 • SMT Magazine 45 feature board design moves beyond reach of in-circuit testers continues tion as a power or ground plane to better cope with EMI issues. For example, the top and bot- tom layers of a board may be coated with metal to better control EMI. EMI concerns have also limited the adoption of the bead probe meth- od of ICT. In order to deploy bead probe on an ICT system, the routes must be exposed on the surface layer. Unfortunately, surface routes will radiate significant EMI, which has become in- creasingly unacceptable. In addition, vias are frequently back-drilled as a way of proper termination to ensure sig- nal integrity. A via routed from a chip on one Figure 4: Via stubs. The image illustrates a blind surface to a test pad on the opposite side of a via (A), a buried via (B) and a via that has been board would be an un-terminated stub, which back-drilled (C) to reduce EMI issues. would cause signal reflections and ringing on the trace. Back-drilling eliminates the stub and also the possibility that a test pad for ICT test- ing could be placed on the via. Non-Intrusive Board Test (NBT) Blind and buried vias are often designed As a software-based methodology, NBT is into circuit boards to limit the number of board not subject to the limitations of probe-based test layers. Both types eliminate the possibility of technologies like ICT. A simple connector on a test pads on the via. A blind via is routed from printed circuit board typically links the board to one surface layer to an internal layer. A buried an NBT test station, which is usually a PC or lap- via interconnects nodes on internal layers and top. Frequently, NBT test technologies connect never comes to a surface layer (Figure 4). This to the board through a JTAG port (IEEE 1149.1 internal routing may reduce the number of lay- Boundary-Scan Standard’s Test Access Port). In ers, but it also eliminates external physical ac- addition, NBT will utilize embedded instrumen- cess to the nodes. Blind and buried vias can se- tation intellectual property (IP) in chips and on verely reduce the test coverage provided by ICT circuit boards. Several complementary debug, testers. validation and test technologies can comprise an NBT test strategy. The typical test technolo- gies that can be included in an NBT test strat- egy are high-speed I/O validation using instru- ments embedded in chips, boundary-scan test (BST) for structural testing, processor-controlled test (PCT) for structural and functional testing, FPGA-controlled test (FCT) for a variety of test functionality and others. NBT applies test vectors that are internal to the board and offers extensive diagnostics to pinpoint faults. Because it is a software-driven test strategy, an NBT test station can run sev- eral complementary test technologies and, in this way, obtain improved coverage for all three of the critical types of testing: structural, func- Figure 3: Electromagnetic interference (EMI). tional and performance. Moreover, implement- Many circuit board designs today place the traces ing NBT’s multiple test technologies on one test on internal layers to reduce EMI emanating from platform simplifies NBT’s deployment on the surface layer traces and test pads. manufacturing floor.

46 SMT Magazine • September 2013 feature

board design moves beyond reach of in-circuit testers continues

The test technologies that can be con- Test re-use over a system’s entire life cycle figured in an NBT test system are capable of is another benefit of BST found in NBT test sta- testing a larger fault spectrum than ICT. For tions. The non-intrusive debug, validation and example, ICT only tests boards at the speed test technologies incorporated in NBT systems of the ICT tester, not the speed of the board can be deployed throughout a product’s life or the chips on the board. In contrast, NBT’s cycle, beginning in design for prototype board signal integrity tools for high-speed buses are bring-up, followed by volume manufacturing, at-speed tools that can validate operational and eventually migrated to repair and trouble- performance. Some NBT systems feature a bit shooting operations. Software-driven tests de- error rate testing (BERT) tool that can uncover veloped early during the design stage can be re- which lanes on a high-speed serial interface used until product obsolescence, reducing the are malfunctioning. NBT margining tools can total cost-of-test significantly. Costly ICT testers plot eye diagrams to determine the signal in- only make economic sense in high-volume/ tegrity on the bus. Another at-speed NBT tool, low-mix manufacturing environments, but PCT, accesses the board through the proces- their eroding test coverage is making ICT less sor’s debug port to perform debug, device ini- cost-effective in all applications. tialization, at-speed functional test with struc- tural diagnostics and other test functionalities. Conclusions FCT temporarily inserts test instruments into Although intrusive test technologies such an on-board FPGA and applies test vectors at- as ICT have been effective in the past on the speed. The nature of any particular FCT test manufacturing floor, recent advancements in suite will depend on the instruments inserted basic electronic technologies are disrupting into the FPGA and this will be determined by legacy test methods. Fortunately for electron- the objectives of the test strategy for the par- ics manufacturers, non-intrusive software- ticular circuit board. based test technologies have emerged over the last 10 years. By capitalizing on the strength of Oil and Water? software—its low procurement and operational Some ICT suppliers have tried to incorpo- costs relative to hardware-intense test systems rate NBT techniques into their testers, but this like ICT, as well as its flexibility, adaptability is like trying to mix oil and water. It doesn’t and agility—NBT technologies offer an array of work very well. For example, an ICT system is significant solutions today and will continue not an effective platform for boundary-scan to do so as electronic technology advances in test (BST). Running BST on an ICT tester shack- future. SMT les BST with the limitations of ICT. Standalone NBT systems with BST avoid this problem. References Consider that most ICT testers have a maxi- A number of white papers and eBooks ex- mum test clock (TCK) of 1 or 2 MHz, which is plaining non-intrusive test technologies can be far too slow for testing high-speed memories found here. like DDR2/3. In addition, most installed ICT testers do not currently support the boundary- scan standard for high-speed AC-coupled nets, Adam Ley is chief technologist IEEE 1149.6. This rules out testing high-speed for non-intrusive board test buses like PCI Express, XAUI and SATA on an and JTAG for ASSET InterTech. ICT tester. In addition, BST on ICT will require For the decade prior to ASSET, isolation of the main probes in the test fixture he held several positions with to reduce noise from the probes and to make Texas Instruments, including the test repeatable and deterministic. Often, application support for TI’s this results in dual-stage ICT fixtures, which boundary-scan logic products and for test drive up the cost of test significantly as well as and characterization of new logic families. the complexity of test operations.

September 2013 • SMT Magazine 47 article

Development of a Methodology to Determine Risk of Counterfeit Use, Part 1 by iNEMI Counterfeit Components The independent distributor level has typi- Project Team: cally been seen as the weak link in the supply Harrison Miles, Corelis,Inc. chain where counterfeits are most likely to be Mark Schaffer, iNEMI introduced. With the emergence of new legis- lation and through the efforts of different in- ABSTRACT dustry entities, new standards and guidelines Counterfeit components have become a are now available for suppliers to establish and multi-million dollar, yet undesirable, part of maintain product traceability and to establish the electronics industry. The profitability of receiving inspection and detection protocols. the counterfeit industry rests in large part on There is no substitute for a healthy supply chain, its ability to recognize supply constraints and and distributors play an essential role in the dy- quickly respond, effectively taking advantage of namics of the system. At the same time, there a complex and vulnerable supply chain. Factors is an increased awareness of the need for proper such as product obsolescence, long life cycles, management of electronic waste. Regardless of economic downturn and recovery, local disrup- the nature of the counterfeits, whether cloned, tions in manufacturing due to natural disasters, skimmed, or re-branded, counterfeits are dan- and lack of proper IP legislation all represent gerous and too expensive to be ignored. opportunities for the counterfeit component The work presented here by the iNEMI industry to flourish. Electronic counterfeits af- Counterfeit Components Project takes a com- fect every segment of the market, including prehensive view of the problem by surveying consumer goods, networking and communica- the possible points of entry in the supply chain tions, medical, automotive, and aerospace and and assessing the impact of counterfeit compo- defense. In manufacturing, the use of undetect- nents on the industry at various points of use. ed counterfeits can lead to increased scrap rates, We then propose a risk assessment calculator early field failures, and increased rework rates; that can be used to quantify the risks of procur- while this presents a major problem impact- ing counterfeit parts. This calculator is aimed at ing profitability, the use of counterfeit compo- all segments of the supply chain and will be of nents in high reliability applications can have interest to component manufacturers, product far more serious consequences with severe or designers, distributors, loss estimators, industry lethal outcomes. groups and end users.

48 SMT Magazine • September 2013 article development of a methodology to determine risk of counterfeit use, part 1 continues

Introduction Counterfeit Device Categories The existence of counterfeit electronic com- Counterfeit components can be produced, ponents, materials and assemblies (hereafter sourced, and distributed in many different referred to simply as counterfeit components) ways. The identity of these non-standard parts is not a new phenomenon[1,2]. However, global is usually very well concealed in the present trade of counterfeit components has recent- supply chain. Types of counterfeit components ly increased markedly. There are four distinct can be divided into the following categories. categories of electronic products in which counterfeit components are most frequently Cloning found: The complete manufacture of a reverse en- gineered device to have the same form, fit, and • Manufacturing shortfall and product function as the original. Devices are produced shortages on low end equipment and will not meet the • High value products original reliability requirements. Devices are • Obsolete, discontinued, and legacy branded and sold as original component manu- devices facturer (OCM) parts. • Field installable options or upgrades Product “skimming,” subcontractors, The Semiconductor Industries Association or second source supplier Anti-Counterfeiting Task Force[3] has defined Manufacturers may over-produce or claim a counterfeiting as: lower production yield. These extra devices can then be introduced into the market through • Substitution or the use of unauthorized the broker chains. copies of a device or product • The use of inferior materials or a Disposal of scrap and rejects modification of performance without Devices rejected during manufacturing are notice sent to recyclers to salvage precious metals. Re- • The sale of a substandard component cyclers may certify destruction without scrap- or product in place of an original ping devices and subsequently sell it back into OCM device or OEM product the supply chain.

The following definition was adopted Devices used as qualification samples from “Defense Industrial Base Assessment: OCMs and OEMs used large quantities of Counterfeit Electronics”; US Dept of Com- devices to qualify/certify form, fit and function merce—Office of Technology Evaluation; Janu- of devices. Accelerated life testing is used to ary 2010[4]. evaluate the functionality and reliability at end A counterfeit is an electronic part that is not of life. Pilfered devices stored for future evalua- genuine because it: tions can be sold into the supply chain as virgin product. When scrapped, many units may still • Is an unauthorized copy function making this material a prime target for • Does not conform to original diversion frauds. manufacturer’s design, model, and/or performance standards Reclamation and reuse of components • Is not produced by the original Large quantities of electronic equipment con- manufacturer or is produced by taining working devices are scrapped. Valuable unauthorized contractors components can be recovered for reuse; however, • Is an off-specification, defective, or used uncontrolled removal can damage and/or com- product sold as “new” or working promise the original electrical performance, reli- • Has incorrect or false markings and/or ability and operational life. These compromised documentation parts can then be sold into the supply chain.

50 SMT Magazine • September 2013 article

development of a methodology to determine risk of counterfeit use, part 1 continues

Re-branding and Large Business Systems sector, in particu- Some products have high-performance re- lar, the FSI (financial services institutions) and quirements and must undergo more extensive pharmaceuticals own a lot of embedded servers testing during manufacture (for example, de- supporting mission critical activities that could vices that must operate at extreme tempera- pose serious economic and health risks. The lat- ture ranges, such as automotive, aerospace and ter may have greater implications and impact military applications, or high speed versions of on a global crisis via malware. memory modules and processors). Devices with lower specifications that were never tested to Situation Analysis the more stringent specifications are acquired iNEMI segregates the electronics industry at a lower cost, re-marked, and resold at the into the following product sectors: higher price. • Aerospace and defense False claims of conformity to industry • Automotive certifications (e.g., RoHS) • Medical Paperwork is provided stating devices are • High-end systems (including data compliant and old (non-compliant) devices are communication, networking, voice substituted. communication and large business systems) Devices containing embedded • Office systems malicious malware • Consumer and portable Programmable devices are reprogrammed to cause latent damage to products. This prob- All of these product sectors are at risk to lem is most critical in the aerospace, defense, introduction of counterfeit components; how- and medical sectors in which counterfeits ever, each has its own set of requirements for could render systems inoperative, compromis- commonly used components. It is not clear ing the safety and security of users. The Office that there is a “one size fits all” solution to the

Industry Sectors Product Service Time Aerospace & Defense Avionics (Civil) 10–20 years Avionics (Military) 10–30 years Automotive Cars and Trucks 10–15 years (warranty) Medical External Equipment 5–10 years Internal Equipment 7 years High-End Systems Infrastructure Equipment 10–30 years Data Center Equipment 7–10 years High End Servers 7–10 years Industrial Controls 7–15 years Office Systems Desktop Computers 24–60 months Consumer & Portable Appliances 7–15 years Cell Phones 18–36 months Laptop Computers 24–36 months

Table 1: Industry Sector Product Service Time.

September 2013 • SMT Magazine 51 article development of a methodology to determine risk of counterfeit use, part 1 continues counterfeit components problem due to the gration of the communication and computing variations in requirements among sectors. technologies in commercial business systems. The products represented include mainframe Aerospace and defense and high-performance computers, the data These products require flawless performance centers and server farms that house the com- on demand, in a multitude of rugged environ- puters, and communications equipment such ments, and must sustain this performance over as switches and routers and enterprise service long periods of continuous service. Due to the provider equipment. long service life, systems rely on legacy devices to maintain and expand existing systems. De- Office systems fense and aerospace systems require extensive These include desktop PCs and other gen- testing to meet performance requirements and eral office equipment (printers, copiers). This designs are modified (ruggedized) to meet the sector is cost-sensitive and requires the latest thermal, vibration, humidity, salt, fog, and oth- cost effective technologies. The main vulner- er environmental and reliability requirements abilities relative to counterfeit components are associated with DoD platforms. Both need to cloning, product “skimming,” reclamation, and have a proven supply chain to ensure devices rebranding. meet security requirements. Consumer and portable Automotive electronics These products are increasing in complex- These applications involve temperature ex- ity; however the main drivers are the reduc- tremes that require improved process controls tion in cost and increase in functionality while on the devices. Controllers communicate with looking at ways of continuously shrinking the sensors and drive relays, injectors, motors, system footprint. The sector has the shortest lamps and solenoids. The engine controller is product life, and the main vulnerabilities are currently the most complex product for harsh- similar to the office and large business systems, environment automotive electronics. There is i.e., cloning, product “skimming”, reclamation, also the need for large traces required by high and rebranding. current and power circuitry. Long life, high reli- ability devices are needed as product warranties Possible Strategies extend to as long as 10 years. Dealing with the different counterfeit de- vice categories will require the use of a variety Medical products of strategies. There are different strategies for These include large infrastructure equip- each category that are most likely to be success- ment, small stationary equipment, and im- ful: plantable devices. High reliability is required for life-critical applications such as electronic Cloning implants, medical imaging systems, and resus- Legacy and high value components are sus- citation systems. Many of the large systems use pected to be the most dominant. Device serial- legacy devices and need a reliable supply of re- ization may prove to have a beneficial impact placement parts. on this category of counterfeits.

High-end systems Product “skimming,” subcontractors, These include three major categories: high- or second source suppliers performance computing, data centers and com- Place better controls on the documentation munications. The networking and comput- with violators identified and prevented from ing hardware has been gaining more common conducting further business. components as the communications becomes an integral part of enterprise computing and as Disposal of scrap and rejects technology advancements enable tighter inte- Establish better controls on scrap processing

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Candor Industries, Inc. www.candorind.com 416 736 6306 article development of a methodology to determine risk of counterfeit use, part 1 continues and handling. Systems designed to more effec- Task 2: Review and tabulate successes that tively monitor and audit the waste stream may have worked in the past (best known methods/ be needed. best known practices). Task 3: Develop a methodology to evaluate Devices used as qualification samples or assess the risk of counterfeit use. This form of counterfeit may not be preva- In addition to the tasks specifically identi- lent enough to warrant developing solutions; fied in the project statement of work, the team however, this needs to be verified by an investi- also: gation into the extent of this source of counter- feit components. • Focused on those attributes that are of most value to the supply chain and participat- ing project members, and that are applicable to Reclamation and reuse of components multiple spaces across the supply chain. Some OCMs and OEMs have legitimate op- • Identified and developed methodologies erations to reclaim and reuse components us- with associated metrics to assess the overall ing strict procedures to ensure that quality and extent of the counterfeit problem in the elec- reliability have not been compromised. Verifi- tronics industry. The outputs will enable iNEMI cation procedures for legitimate devices need to members to assess the risk of counterfeit use in be established. their respective industries, the risk of untrusted sources of supply in that industry and under- Rebranding stand the total cost of ownership associated Inspection, inspection, inspection (me- with those risks. chanical, electrical, etc.) as well as lot testing. Note: The methodologies and strategies ap- ply to all phases of the manufacturing cycle and False claims of conformity to industry supply chain. Not only do counterfeit compo- certifications (e.g., RoHS) nents have a serious impact on the OCM, but Incoming inspection should be required, impact all downstream users from the legiti- since counterfeiters are providing false docu- mate component brokers to the OEMs that in- mentation. Traceability and serialization may tegrate these components to the end user. Met- help to reduce this category of counterfeit de- rics to assess the overall extent of the problem vices. and anti-counterfeiting will be identified for all phases. Devices containing embedded The team began by identifying the key sec- malicious malware tors of the electronics supply chain (Figure 1). This problem is most critical in the aero- space and defense and medical sectors in which • Wafer manufacturers counterfeits could render systems inoperative, • Chip manufacturers compromising the safety and security of users. • Board manufacturers The use of all possible approaches to counter- • System manufacturers feit reduction is warranted for this sector. • After-market sales and refurb support • Disposal/Recycle Initial Work The first phase of iNEMI’s Counterfeit Com- The electronics supply chain was then ponents Project is broken into several high- broken into a series of manufacturing “cluster level tasks. The first three tasks (on which this maps” to help visualize how materials, parts, paper is based) were: assemblies, and waste move, and identify the key players in each manufacturing sector Task 1: Identify and summarize any related (Figure 2). research or development within the industry Figure 2 highlights two principle flows be- and academic communities. tween the major electronic manufacturing

54 SMT Magazine • September 2013 article

development of a methodology to determine risk of counterfeit use, part 1 continues

Figure 1: Electronic manufacturing workflow diagram[5].

Figure 2: Board manufacturer cluster.

workflow blocks: the “authentic” and “coun- in place to prevent corruption of their supply terfeit” material flow paths. The authentic ma- stream. These measures generally provide a terial flow pathways indicate peer-to-peer con- high confidence in the supply chain and fea- nections where the board manufacturer has ture traceability of the pedigree of electronic established strong agreements and has policies components.

September 2013 • SMT Magazine 55 article development of a methodology to determine risk of counterfeit use, part 1 continues

The counterfeit material flow pathways 2.2) Inputs highlight potential opportunities for breaching The profile of the supplier and the history of into the supply chain and corrupting traceabil- that supplier in terms of counterfeit incidents, ity and pedigree of the electronic components. the clarity of the supply line, and the anti-coun- The risk of infiltration using one of these path- terfeit controls used by the supplier are key fac- ways increases when product shortages occur. tors in determining the risk of counterfeit use. Risks can also increase as new participants en- For example the inputs risk is highest where ter the networks to service growing demand. the supplier is a broker with no controls who For example, as green manufacturing increases has previously supplied confirmed counterfeit demand for recycling, new players rushing to product and cannot confirm the origin of the capture market share may overlook security product in question. Conversely, the inputs risk protocols. Also consider how criminals are well is lowest when the product is coming directly versed at pretending to be new participants. from the OCM, there are strong counterfeit With the completion of the cluster maps for mitigation procedures in place, and there is no the electronics supply chain, the team was able known history of counterfeit supply. to begin work on the task of developing a meth- odology for assessing the risk of counterfeit use. 2.3) Process The processes required to produce the prod- Developing a Risk Assessment Calculator uct, the ease of counterfeit detection of that product and the counterfeit controls used in 1. Premise of the Spreadsheet/ the original product are also key factors in de- Assumptions termining the risk of counterfeit use. Where a Examining the cluster maps for the differ- product requires a large capital investment is ent segments of the electronics supply chain, easy to authenticate and uses a high level of the team decided that the risk of counterfeit use counterfeit controls, the process risk of counter- was based on four key elements: feit use is low. On the other hand, where there is little or no investment required to make the • The profile of the product in question product, validation is difficult, and there are no • The inputs or characteristics of the sup- special counterfeit controls in place, the process plier and supply line risk of counterfeit use is highest. • The processes used on the product to deter counterfeit use 2.4) Outputs • The outputs or channel characteristics The key factors in the case of the outputs The team’s goal was to provide a quantita- risk are the sales channel used, the handling tive methodology on risk assessment built on of excess inventory, prototypes, reworks and these four key elements that any company scrap and the customer profile. The outputs risk could use to rate their product. is at its highest when the sales channel is un- known; when there is no control or traceabil- 2. Structure of the Spreadsheet/ ity on excess inventory, prototypes, reworks or Rating Scale scrap; and where the end customer is unknown. 2.1) Product profile In contrast, where the end customer is well The profile of the product in terms of de- known, the sales channel is well defined and mand for that product and where it is on the the excess/prototypes/reworks and scrap are life cycle are key determinants in the risk of well controlled, the outputs risk is lowest. counterfeit use. The higher the demand for a product, the more attractive it becomes for 3) Examples of Calculation counterfeiting. If a product is in high demand Rating each of the four key risk elements and also the original supply is near end of life, above, the methodology gives an overall score then the product profile risk of counterfeit is for the product in question. FLASH is a well- highest. known target for counterfeiters, making it

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development of a methodology to determine risk of counterfeit use, part 1 continues

Figure 3: Methodology to evaluate risk of counterfeit use.

a good test of the methods developed here. form of levels of risk of counterfeit use. For Based on the values used by the team for each example, an overall rating of 1 ~ 500 means of the factors, the overall rating is very high the risk of counterfeit use is very low and no indicating that our methodology gives the risk additional actions are recommended. A rating of counterfeit use as very high. In contrast the of 5000 ~ 10,000 means the risk is very high rating for a typical ASIC device is very low, i.e., and immediate action needs to be taken in the the risk of counterfeit use is low. These results high-risk areas. serve to validate this method or risk assess- When materials are purchased through the ment. distribution channel, there are ways to mini- At this stage, the methodology is useful for mize exposure to suspect, fraudulent, or coun- comparative purposes only. The team would terfeit parts passing undetected through the like to encourage iNEMI members to test the distributor to you. SAE International Standard methodology and provide feedback to the AS5553A[6] identifies a series of controls and cer- team. The wide range of data collected would tifications to ensure detection and prevention enable the team to provide guidelines in the of counterfeit components. You can select a dis-

September 2013 • SMT Magazine 57 article development of a methodology to determine risk of counterfeit use, part 1 continues tributor that has been audited by a third-party business, in particular when there are unknown certification body and is compliant with: providers in the chain. SMT

a) AS6081 (Counterfeit Electronics Parts; Click here to read Part 2 of this article in the Avoidance Protocol, Distributors)[7] I-Connect007 Daily Newsletter. b) AS6301 (AS6081 Verification Criteria) c) ISO/IEC 17025 certified for counterfeit References testing 1. Bill Crowley, “Automated Counterfeit Electronic Component Warning System and For distributors to be compliant with these Counterfeit Examples”, SMTA/CALCE Counter- standards, all materials must be inspected, test- feit Symposium, June 2012 ed, and certified as non-counterfeit materials 2. Philip DiVita et al, “Avoiding Counterfeit before they can resell the parts. This level of Parts When Addressing Component Obsoles- testing will add additional cost to the materials, cence”, SMTA/CALCE Counterfeit Symposium, but the risk will be significantly mitigated. The June 2012 level of testing and controls required from the 3. www.semiconductors.org distributor selected can be balanced in terms of 4. www.bis.doc.gov the cost vs. risk avoidance benefit for your busi- 5. 2010 iNEMI Roadmap ness needs. 6. SAE International For suppliers outside the authorized distri- 7. Anne Poncheri, “AS6081-Fraudulent/ bution channel, there are qualitative means to Counterfeit Electonic Parts; Avoidance, Detec- better assure end customers that your organi- tion, Mitigation and Disposition-Distributor,” zation is providing genuine materials. Chief SMTA/CALCE Counterfeit Symposium, June among these is to always know your source of 2012 supply which can be achieved by tracking and recording problems to provide a historical re- Harrison Miles is director of busi- cord of past transactions. This is particularly ness development at Corelis, Inc. important for high-volume suppliers. He may be reached at harrison. In addition, understanding parts and as- [email protected]. sociated package types is a must. This affords the purchaser the ability to recognize the most blatant attempts at counterfeiting. This may Mark Schaffer is project manager lead to a limiting of drop shipping parts from at iNEMI. He may be reached at their original source to an end customer with [email protected]. no handling by the intermediary party. There is an associated cost impact to inspect parts; however, it may be a necessary cost of doing

unaffected by reduced levels of oxygen during fabri- Key Surface Properties cation—with implications for the design of functional of Complex Oxide Films complex oxides used in a variety of consumer prod- ucts, said Zheng Gai, a member of DOE’s Center for Better batteries, catalysts, electronic informa- Nanoscale Materials Sciences at ORNL. tion storage and processing devices are among the “With these materials being a promising alterna- benefits of a discovery made by Oak Ridge National tive to silicon or graphene in electronic devices, the Laboratory scientists. ever-decreasing size of such components makes their The findings, published in Nanoscale, showed surface properties increasingly important to under- that key surface properties of complex oxide films are stand and control,” Gai said.

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Ensuring Supply Chain Reliability and Integrity by Richard Ayes SMT: IPC-A-610 and IPC-J-STD-001 are I-Connect007 widely believed to ensure high reliability of electronic assemblies. Certain EMS providers It’s become standard procedure for com- comment that they drive up costs and make panies to claim a worldwide reach. But with products less reliable. What is your opinion? operations in Canada, Silicon Valley, China, Hong Kong and Mexico, EMS provider SMTC Brian Morrison: We believe that IPC- Corp. is truly a global enterprise. In an inter- A-610 and IPC-J-STD-001 provide the nec- view with SMT Editor Richard Ayes, Corporate essary guidelines to achieve highly reliable Value Engineering Manager Brian Morrison electronic assemblies based on the underly- and Vice President of Account Management ing theory that all products are designed to Frank Gerber discuss SMTC’s strategies to en- achieve target conditions. Not all designs are sure that the devices that enter their supply created equal and there are always excep- chain meet the high-reliability standards in tions, but these exceptions can almost always electronics assemblies. They also highlight be associated with an underlying DFX issue how the company adapts to the changes amid or critical design criteria that create a non- the ever-evolving requirements in the differ- ideal condition. These situations commonly ent sectors that they serve, as well as the differ- drive up rework to attempt to achieve target ent security issues that a major EMS provider conditions and as a result lower reliability. like SMTC must address. Any high-reliability product starts with a

60 SMT Magazine • September 2013 article ensuring supply chain reliability and integrity continues design taking into consideration both per- receiving inspection that incorporates mate- formance and manufacturability. More and rial traceability and ties liability to the supplier, more companies now are seeing the value in enabling material to be contained and purged engaging with their EMS partner in review- effectively and quickly. Through this stringent ing and providing feedback to ensure DFX sourcing practice, to date, SMTC has never re- is a key part in achieving IPC standards and ceived counterfeit material. high reliability. SMT: Certification can cover a wide range SMT: What precautions ensure the integrity of issues including incoming components and and authenticity of bought-in components? Do materials, operator training, manufacturing your customers specify what sources you must processes, compliance with legislation, confor- use, or leave that responsibility with you? mity with product specification, and many oth- ers. How does an organisation as geographi- Morrison: SMTC only purchases from the cally diverse as SMTC deal with certification? Is customer approved manufacturing list (AML) it handled locally or globally? through either direct or distribution and re- quire all of our suppliers to follow SMTC glob- Morrison: SMTC recognizes that training is al procurement policies. In cases of material a critical part of our overall strategic business shortages, SMTC will purchase only from our plan to meet and exceed the expectations of approved brokers. In order to be considered an our customers, by producing products with SMTC approved broker, the broker must sign up outstanding quality and reliability. At SMTC, for 100% liability against counterfeit material we embrace the importance of international and a minimum liability of $3 million, cover- standards certification including ISO and IPC ing all aspects of material cost (both direct and and ensure all sites are certified to these stan- indirect). SMTC’s sourcing of components is dards. SMTC utilizes a Global Copy Exact Phi- a global activity managed through our global losophy to operate our facilities in a standard- procurement, ensuring all sites are executing to ized way, utilizing a best practice approach that the same copy-exact policies and procedures so provides flexibility to manufacture products that integrity is maintained. locally or globally and enables seamless global To complement our procurement policies, product transitions. All sites follow similar ap- SMTC receives product change notices (PCN) proved processes, equipment, materials and for all approved AML including counterfeit/ documented procedures per ISO 9001 and ISO failure notices to alert and action potential 13485 international quality standards or regu- material issues. Upon receipt of incoming ma- latory requirements where applicable. Any terial, all manufacturing sites employ a robust changes to procedures are processed and ap- proved globally through a corporate ISO team and distributed to sites for certification. Being a global company, it is the responsibility of each site to translate the documents, software, formats and other activity to the language used at each site in order to facilitate under- standing and certification. New pro- cesses, equipment and materials can be evaluated at individual sites, and if the new method is deemed “best prac- tice,” then it is incorporated at each site over time, allowing time for im- plementation and certification.

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ensuring supply chain reliability and integrity continues

SMT: It is clear that SMTC goes to great ment plays a key role on managing expectations lengths to understand the dynamics of key mar- of the customer and ensuring that our strategic ket areas. Your website lists industrial, comput- plan. On a quarterly, basis we engage with our ing, communication, consumer, medical and re- customers on a business review to ensure both newable energy. How do you adapt to the chang- sides are meeting expectations and there is a es that influence your customers’ businesses? clear plan to address changes to that plan.

Frank Gerber: SMTC has an account manage- SMT: What are the main security issues that ment organization that gets deeply involved with a major EMS provider like SMTC must address? our customers. The account manager is a senior level individual that builds relationships across Gerber: An EMS provider must address a the key functional areas within the customer number of different security issues for our cus- and gains an in depth knowledge of the custom- tomers. Probably, the biggest security concern ers’ business. They facilitate relationships and of an OEM customer is financial. The customer exchanges at the executive level of both compa- wants to know that the EMS provider is finan- nies. Our key strengths are in our ability to not cially sound and has a strong balance sheet so only meet the needs of our customers by being they are assured that the EMS can make the in- an exceptional manufacturing partner, but by vestments required, buy the inventory and pay vertically integrating our services to help better the suppliers to fulfill the demand. Our custom- understand our customer’s business model and ers also have a significant concern regarding the adapt to their changing needs. Program manage- control of our customer intellectual property as

September 2013 • SMT Magazine 63 article ensuring supply chain reliability and integrity continues we live in a competitive market and they trust the partners, customer design teams and other security of their designs and products to SMTC. manufacturing entities. In general, design and SMTC follows stringent SOX (Sarbanes-Oxley manufacturing parties will have their own set Act) compliancy protocol with limited and con- of goals, and development is typically isolated trolled access to the outside, and does not allow from one another. Design rules and require- direct network access to any internal systems to ments can vary significantly and commonly ensure the security of information is maintained. cause conflict, which can drive up costs or re- Sharing of information with suppliers is quire expensive re-design costs. To combat this something that cannot be avoided, and we issue, best practices typically involve early de- have maintained a supplier management pro- sign involvement with all parties to truly ensure gram that starts with a Non-disclosure Agree- all requirements are taken into consideration— ment outlining SMTC policies on sharing of where 80% of the product cost is defined. In re- confidential information. Suppliers are closely ality, this can be difficult and can add lead time monitored and approved through global pro- to launch products, which increases in com- curement to ensure only suppliers that have plexity with the number of parties involved. been selected can be used. Engaging with one integrated supplier that can In certain applications, very high security take a product through all stages of the design is required for payment systems, which require with an integrated DFX review process provides key injection. In those circumstances, SMTC the platform for innovators to advance ahead works closely with our customers and security of their competition and significantly decreases representatives to ensure we comply with all time to market. SMT regulatory requirements and will provide dedi- cated locked control rooms and select autho- ABOUT THE INTERVIEWEES rized personal access only to ensure the highest As Corporate Value En- level of security. gineering Manager, Brian Morrison B.A.Sc., P.Eng, is SMT: What specific value-added service on responsible for working col- a specific end-application or market sets SMTC laboratively with customers and Idneo Technologies apart from its compe- to reduce cost and improve tition? performance in order to protect and enhance overall Morrison: Our partnership with Idneo pro- product value through the vides our customers a unique, integrated and NCI/NPI process. Morrison leads the Technical seamless new product introduction experience Services Group that provides a broad range of from concept to full production not commonly design services, capabilities and partnerships available from a tier-2 EMS. Through our Tech- covering all aspect of design from layout, DFX, nical Services Group and Transition Manage- development through to production release ment, a customer can engage with SMTC on a and continuous improvement. design concept and achieve earlier design en- As Vice President, Ac- gagement from both design and manufacturing count Management of to ensure the design not only meets the require- SMTC, Frank Gerber is re- ments of the customer, but is designed to meet sponsible for establishing, both Idneo and SMTC DFX requirements, for a maintaining and growing seamless introduction into production. relationships with our cus- tomer base on a global ba- SMT: Any final comments? sis. Prior to joining SMTC, Gerber held various techni- Brian Morrison: Commonly, EMS engage- cal, business management and customer rela- ments can be disconnected and can involve tionship management positions with IBM, Ce- multiple parties including third-party design lestica, C&D Technologies and Murata.

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Strengthening & Advancing Electronics Manufacturing Globally SAVE THE DATE! Upcoming IPC Professional Development Events August 27–29, 2013 SAVE THE DATE IPC APEX India™ Bangalore, India IPC Technology Market Research Conference & IPC Management Meetings September 10–12, 2013 September 24–26, 2013 • Allerton Hotel • Chicago, IL IPC Conference on Component Technology: Closing the Gap in the Chip to PCB Process Sponsored by Amkor Technology, Inc. Chandler, AZ The Next Generation: Creating the Electronics Industry September 24–26, 2013 of the Future IPC Technology Market Research Conference & Management Meetings Chicago, IL October 12–17, 2013 IPC Fall Standards Development Committee Meetings The IPC Technology Market Research Conference (TMRC) & IPC Co-located with SMTA International Management Meetings are the only events of their kind in the Fort Worth, TX electronics industry that provide a high-level perspective on October 16, 2013 technology, market trends and management issues for senior-level IPC Conference on Assembly and Reliability decision-makers. Geared for the executive, these events will give Bangkok, Thailand you a unique view of the industry so you can take action. It’s the one venue where you can: October 23 • Discover how key technology drivers will impact your industry Conflict Minerals Conference: What an EU Company Needs segment. to Know Brussels, Belgium • Get a preview of emerging market trends … and what they will mean for your business. November 12–13, 2013 7th International Symposium on Tin Whiskers • Hear from leading technologists on new advancements and Hosted by IPC and CALCE; Sponsored by Lockheed Martin their impact on industry needs. Costa Mesa, CA • Meet with other decision-makers from the supply chain and November 13–14, 2013 work on solutions to industry challenges. IPC Conference on Solder and Reliability: Materials, • Network with potential customers and suppliers who can Processes and Test provide the answers you need. Costa Mesa, CA No other event will provide you with this type of information or allow December 4–6, 2013 you such access to other industry executives. HKPCA International Printed Circuit and Management Meetings — September 24 IPC APEX South China Fair TMRC — September 25–26 Shenzhen, China For more information, visit www.ipc.org/tmrc-mm or contact Susan Filz, IPC director of industry programs. More Information www.ipc.org/events

Questions? Contact IPC registration staff at +1 847-597-2861 or [email protected]. feature

Improving Reliability Through HALT and HASS Testing by Mark R. Chrusciel Highly accelerated life test (HALT) is a Cincinnati Sub Zero method aimed at discovering and then im- proving weak links in the product during the design phase. Highly accelerated stress screen SUMMARY: HALT and HASS technology use (HASS) is a means for finding and fixing pro- a combination of accelerated stresses to expose cess flaws during production. Both techniques product flaws early in the design and manufactur- employ stresses far beyond the normal operat- ing stages (often at board level), improving prod- ing condition. The process uses discovery test- uct reliability and customer confidence. This article ing in which problems are found by testing will discuss why companies are succeeding with to failure using accelerated stress conditions. HALT and HASS. HALT is a discovery test as opposed to a com- pliance test. The goal is to find problems, re- HALT and HASS are used to uncover many move them, and improve the product making of the weak links inherent to the design and it more robust. fabrication process of a new product, as well The acronym HALT was coined by Dr. Gregg as during the production phase to find manu- Hobbs in 1988 after he used the term “design facturing defects that could cause product fail- ruggedization” for 18 years. In these tests, every ures in the field. The types of HALT and HASS stimulus of potential value is used to identify chambers available in the market, along with weak links in the design and fabrication pro- the equipment capabilities, will be reviewed. cesses during a product’s design phase. These We will also explore how they used for detec- stimuli may include vibration, thermal cycling, tion of flaws in design, making the product burn-in, voltage, humidity, and whatever else more rugged and reliable. These capabilities will expose relevant weaknesses (including are essential to precipitation and detection of stresses that will not occur in the real world if product defects. they generate real-world failure modes). The

66 SMT Magazine • September 2013 feature improving reliability through halt and hass testing continues stresses are not meant to simulate the field en- vironments, but to find the weak links in the design and processes using only a few units and in a very short period of time. The stresses are stepped up to well beyond the expected field environment in order to obtain time compres- sion in identifying design weaknesses. HALT has, on many occasions, provided substantial MTBF gains, from 5 to 1,000 times. Even when used without production screening, HALT has reduced time to market substantially and also reduced the total development costs. HASS uses accelerated stresses (beyond product specifications and as determined ap- propriate by earlier HALT testing) to detect product defects in manufacturing production Figure 1: Defect by test type. (Courtesy of Chuck screens. The accelerated stresses of the HASS Laurenson, Parker Hannifin.) program shorten the time to failure of defec- tive units and therefore shorten the corrective action time and the number of units built with during the design phase. This is a discovery test similar flaws. Many issues caused by process whose goal is to identify problems. changes after HALT screening were previously Figure 1 shows where design flaws were dis- seen only as early life failures in the field. With covered during the HALT process and why all- an appropriate HASS implementation, these de- axis vibration is important. fects can now be detected and corrected prior Therefore, 74% of the flaws would have to shipment. been missed without simultaneous, all-axis vi- HASS is generally not recommended unless bration. By stressing the product beyond its a comprehensive HALT has been performed, design specification, operational and destruct since without HALT, fundamental design limi- limits can be determined, and decisions can be tations and flaws will restrict stress levels that made regarding how to increase these margins. can be applied in the HASS process. HASS can Each weak link provides an opportunity to im- generate significant savings in screening costs prove the design or the processes, which will as less equipment (shakers, chambers, monitor- lead to reduced design time, increased reliabil- ing systems, power and liquid nitrogen) is nec- ity, and decreased costs. Used properly, HALT essary due to time compression in the screening compresses this design cycle while providing a process. As with HALT, HASS is discovery test- significantly more reliable and mature product ing as compared to compliance testing. at introduction. Studies have shown that a six- month advantage in product introduction can The HALT Process result in a lifetime profit increase of up to 50% In HALT, every stimulus of potential value for the market mover1. (temperature, all-axis vibration, humidity, UV, radiation, etc.) can be used under accelerated Basic Steps in the HALT/HASS Process test conditions during the development phase The term precipitation means the chang- of a product to find the weak links in the design ing of a defect which is latent or undetectable and fabrication processes. Accelerated stresses into one that is patent or detectable. A poor sol- in combination (e.g., high-temperature ramp der joint is such an example. When latent, it rates and all-axis vibration levels together) are is probably not detectable electrically unless it necessary to compress or minimize the time to is extremely poor. The process of precipitation failure. Again this method is aimed at discover- will transpose the flaw to one that is detectable, ing and then improving weak links in a product that is, cracked. The stresses used for the trans-

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improving reliability through halt and hass testing continues formation may be vibration, combined with failure will not occur again. This step is abso- thermal cycling and perhaps electrical over- lutely essential for success. In fact, corrective stress. Precipitation is usually accomplished in action is the main purpose of performing HALT HALT or in a precipitation screen. or HASS. One of the major mistakes in the in- Detection means to determine that a fault dustry is that manufacturers “do HALT” and exists. After precipitation by any means, the de- discover weaknesses and then dismiss them as fect may become patent, that is, detectable. Just due to overstress conditions. It is true that the because it is patent does not mean that it will failures occurred sooner than they would in the actually be detected, as it must first be put into field due to the overstress conditions, but they a detectable state. Assuming that we actually would have eventually occurred in the field at put the fault into a detectable state and that the lower stress levels. built-in test or external test setup can detect the Corrective action must be verified to deter- fault, we can then proceed to the most difficult mine that the product is really fixed and that the step: failure analysis. flaw that caused the problem is no longer pres- Failure analysis allows us to determine why ent. The fix could be ineffective or there could the failure occurred. In the case of the solder be other problems causing the anomaly that are joint, we need to determine why the joint failed. not yet fixed. Additionally, another fault could If conducting HALT, the failed joint could be be induced by operations on the product, and due to a design flaw, that is, an extreme stress at this necessitates a repeat of the conditions that the joint due to vibration or possibly due to a prompted the fault to be evident. One method poor match of thermal expansion coefficients. of testing a fix during the HALT stage is to per- With HASS, the design is assumed to be satis- form HALT again and determine if the product factory (which may not be true if changes have is at least as robust as it was before. It should be occurred) and, in that case, the solder joint was somewhat better. If in the HASS stage, perform- probably defective. The manner in which it ing HASS again on the product is in order. If was defective and why it was defective must be the flaw is correctly fixed, then the same failure determined in sufficient detail to perform the should not occur again. next step: corrective action. The last step of the six is to put the lesson Corrective action means to change the de- learned into a database for later use. Companies sign or processes as appropriate so that the that practice correct HALT and utilize a well- kept database soon become very adept at de- signing and building very robust products with the commensurate high reliability1. Figures 2 and 3 compare HALT and HASS chambers.

Figure 2: HALT/HASS chamber. Figure 3: HALT testing.

September 2013 • SMT Magazine 69 feature improving reliability through halt and hass testing continues

There are many factors that need to be con- know if too much nitrogen escapes into the lab. sidered when evaluating a HALT chamber pur- An ideal situation is to run your DUT on chase. One of the most obvious criteria is to se- a chamber before you make a purchase deci- lect a chamber big enough to handle the size sion. Many chamber manufacturers will have of your DUT. Other factors to consider are the a chamber available for your use, and I would high and low vibration limits of the chamber suggest that you take them up on their offer. and the characterization of the table (how well This will also give you an opportunity to deter- the vibration is distributed). A safety door inter- mine what fixtures are necessary. The manufac- lock system should be in place to prevent the turers can also guide you through the first steps door from being open when liquid nitrogen is in setting up your HALT test. flowing into the chamber. It would also be use- Using fixturing that does not transmit the ful to have multiple cable ports for connections stress to the product under test can be a prob- to your DUT, and front and rear doors on the lem because sufficient levels of stress never larger units. You will also want to check out the reach the product. Three examples are: nitrogen and compressed air usage along with their sound levels. 1. Using a vibration fixture that will not Liquid nitrogen is the predominant cool- transmit the frequencies associated with critical ing media used in HALT testing, so you need to modes of vibration of the product under test or consider how many tests you will be running isolates the mid and high ranges. per day, per month, to determine the amount 2. Using a thermal fixture that does not of liquid nitrogen required (you do not want to transmit the conditioned air to the product run out during a test). You may then contact a such that the product can be rapidly changed gas supplier and decide on the most cost-effec- in temperature over a broad range. tive solution. If you currently have a source of 3. Using electrical overstress and having liquid nitrogen in your facility, you will need to some circuitry such as the lightning arrestor cir- plan the chamber’s location. Running the vac- cuitry bleed off the high voltage before it gets to uum-jacketed connection lines from the source the internal circuits. to the chamber is very expensive (approximate- ly $200/running foot). It is also a good idea to If the stress does not reach the product, then put an oxygen sensor in your lab, to let you nothing has been accomplished2.

Figure 4: Operating and destruct limits.

70 SMT Magazine • September 2013 feature improving reliability through halt and hass testing continues

The Basic Steps of HALT You may also uncover some intermittent Determination of operational and destruct failures that the traditional HALT method may limits for temperature and vibration is an im- not uncover. Experience has shown that mod- portant part of HALT. Some companies (such as ulated six-axis vibration combined with slow aerospace firms) do not test to destruction due temperature changes exposes many flaws that to the high costs of test units. Some engineers could not be found otherwise. Modern HALT incorrectly think that HALT consists only of de- and HASS equipment will easily do the modu- termining operational and destruct limits. How- lation, and it increases detection efficiency by a ever, operation margins are important indicators factor of ten or more in many cases. It has been of product robustness, and therefore reliability. repeatedly demonstrated that patent defects Figure 4 shows the operating and destruct levels could not be found until the modulated excita- relative to the product specification. tion was done. Many times, 100% of the pat- Usually the starting point for HALT testing is ent defects cannot be found without it. This is to begin with each stress applied separately, first especially true for cracked plated through-hole in a step-like fashion and then in combination. solder joints and cracked surface mount solder IPC-9592A Requirements for Power Conversion joints. Very low vibration levels are important, Devices for the Computer and Telecommunica- if not essential2. tion Industries makes the same recommenda- Since HALT and HASS may identify failure tion. A typical progression of HALT would be: modes using “unrepresentative” stress condi- tions, it is easy for engineers to ignore impor- • Cold thermal step stress (see IPC-9592A) tant product improvement opportunities. Cor- • Hot thermal step stress rective action should also be verified, which • Rapid thermal shock stress may require a re-HALT to verify that a problem • Vibration step stress has indeed been solved (and that new problems • Combined thermal and vibration stress were not introduced)3.

Figure 5: Low-temp test graph.

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improving reliability through halt and hass testing continues

Conclusion and much better equipment available today, we Every weakness identified in HALT offers an can do much better. This is why the real leaders opportunity for improvement. Larger margins do not publish1. SMT translate into high reliability and that can re- sult in improved profit margins. Today, HALT References is required on an ever-increasing number of 1. G.K. Hobbs, Accelerated Reliability En- commercial and military programs. Many lead- gineering: HALT & HASS, Hobbs Engineering, ing companies use HALT and HASS techniques 2005 successfully; however, most of the leaders are 2. G.K. Hobbs, “Pitfalls to avoid in HALT being quiet about it because of the phenomenal and HASS,” 2007 improvements in reliability and vast cost sav- 3. A. Barnard, “The Ten things You Should ings attained. The basic philosophy is, “Find Know about HALT & HASS,” 2012 IEEE the weak spots however we can and then make them more robust.” Correct application of these techniques is Mark R. Chrusciel is director essential to success, and there are many incor- of global sales for Cincinnati rect sources of information on the techniques Sub Zero. He has served on the today. Used consistently, completely and cor- board of the Accelerated Stress rectly, HALT and HASS always work to the ben- Test and Reliability Workshop efit of the manufacturer and end user. A typi- for the last five years, and he is cal ROI for the techniques was 1,000:1 some 20 a senior member of the IEST. years ago and, with the improved techniques

“Groovy” Hologram Creates trol these three major properties of light at once. “Our lab uses nanotechnology to play with Strange State of Light light,” says Patrice Genevet, a research associate at Harvard SEAS and co-lead author of a paper Applied physicists at the Harvard School of published this month in Nano Letters. “In this re- Engineering and Applied Sciences (SEAS) have search, we’ve used holography in a novel way, in- demonstrated that they can change the intensity corporating cutting-edge nanotechnology in the (brightness), phase (two waves interfering with form of subwavelength structures at a scale of just one another to either strengthen or cancel each tens of nanometers.” One nanometer equals one other), and polarization (direction of light vibra- billionth of a meter. tions) of light rays using a hologram-like design Genevet works in the laboratory of Federico decorated with nanoscale structures. Capasso, Robert L. Wallace, Professor of Applied As a proof of principle, the researchers have Physics, and Vinton Hayes, Senior Research Fellow used it to create an unusual state of in Electrical Engineering at Harvard light called a radially polarized beam, SEAS. Capasso’s research group in which—because it can be focused recent years has focused on nano- very tightly—is important for appli- photonics—the manipulation of cations like high-resolution lithogra- light at the nanometer scale—with phy and for trapping and manipulat- the goal of creating new light beams ing tiny particles like viruses. and special effects that arise from the This is the first time a single, sim- interaction of light with nanostruc- ple device has been designed to con- tured materials.

September 2013 • SMT Magazine 73 Mil/Aero007 News Highlights

Medical, Aerospace Certifications EPTAC to Help with IDEA Counterfeit for API Technologies Programs API has received two new quality certifications for EPTAC Corporation has partnered with the Inde- its EMS business, including the ISO 13485:2003 pendent Distributors of Electronics Association medical certification and AS9100 Rev C aerospace (IDEA) to deliver several counterfeit component certification. The former marks the company’s first mitigation and inspection programs providing medical-certified facility certification. clients with educational options and pathways to IDEA certification. Positive Q4 Results Position OSI Systems for Growth Murrietta Receives Raytheon’s Highest Deepak Chopra, OSI Systems President and CEO, Supplier Award stated, “During the fourth quarter, our security Raytheon recognizes its Five Star Suppliers based division achieved record operating profits as the on three important factors: 100% on-time deliv- higher margin turnkey screening solution busi- ery, 100% sustained quality, and continuous pro- ness was a key factor in increasing our operating cess improvements. Murrietta Circuits was one margins from 7% in fiscal 2012 to 16% in fiscal of only 14 to be recognized for this tremendous 2013.” achievement.

Ducommun LaBarge Segment Posts IECQ Program to Address Counterfeit Flat Sales in Q2 Component Crisis The company’s DLT segment reported net sales In response to the growing demand and need for 2Q13 $107.5 million, compared to $107.8 of the electronics supply chain, IECQ launched a million in the 2Q12. The defense electronics and programme designed to address the international commercial aerospace revenue increased 16.5%, counterfeit crisis faced by the aerospace, defense, offset by a 25.8% decline in the segment’s non- medical, and high-performance (ADHP) sectors. A&D revenue. New Material May Transfer Heat Sypris’ Electronics Group Revenue Up More Effectively 6% to $7.7M in Q2 A team of theoretical physicists at the U.S. Naval Revenue for the Electronics Group was $7.7 mil- Research Laboratory and Boston College has iden- lion in 2Q13, compared to $7.3 million for 1Q13 tified cubic boron arsenide as a material with an and $16.1 million in 2Q12, reflecting factors in- extraordinarily high thermal conductivity and the cluding budgetary and funding uncertainties potential to transfer heat more effectively from within the U.S. DoD. electronic devices than diamond.

AVX Awarded 5-Star Supplier Award DARPA Unveils ATLAS Robot by Raytheon On Monday, July 8, 2013, the seven teams that AVX Corporation, a leading manufacturer of ad- progressed from DARPA’s Virtual Robotics Chal- vanced passive components and interconnect lenge (VRC) arrived at the headquarters of Bos- solutions, was honored with the 5-Star Supplier ton Dynamics in Waltham, Massachusetts to meet Excellence Award from Raytheon’s Integrated De- and learn about their new teammate, the ATLAS fense Systems (IDS) business unit. robot.

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+1 (408) 245-5400 www.hunter-technology.com column the art of failure A Study in PCB Failure Analysis: the Intermittent Connection by Derek Snider Insight Analytical Labs Inc.

Over the course of a failure analyst’s career, took a high-level overview of the failure analy- he will be exposed to an extensive and varied sis process, discussing the steps an analyst takes array of devices. No matter the technology— to turn a failing, rejected product into action- whether they be nanoscopic silicon sensors able knowledge for process improvement. In with moving parts so small as to defy belief or this column, we will see how these steps are massive circuit assemblies comprised of thou- applied to a specific failure. Naturally, examin- sands of discrete components and integrated ing a relatively trivial case would not provide circuits—no device is completely immune to the necessary depth of learning, so instead we failure. Variations in process control, insuffi- choose to give an example of a failure many an- ciently robust designs, and extended abuse by alysts dread: an intermittent failure on a print- an end user can all spell early doom for a device. ed circuit assembly. In our introductory article, Failure is the In this study, a single printed circuit assem- First Step on the Road to Success—the Failure bly was received as an RMA from an end-user Analysis Process (June 2013, SMT Magazine) we (Figure 1). The end-user was able to identify the

Figure 1: Photograph of the failed PCA.

76 SMT Magazine • September 2013 the art of failure a study in pcb failure analysis: the intermittent connection continues failing assembly only by swapping parts; lack- example) was causing the device to fail. When ing any sort of test equipment, the customer first powered up, the board was at room tempera- was unable to provide any detail that could ture; however, after being under bias for a length help to narrow the scope of the analysis beyond of time, the power dissipated by the board caused the most basic of failure descriptions (“this part enough self-heating to create a failure. Environ- doesn’t work anymore”). The first step in the mental testing was performed, and the tempera- failure analysis process is to verify the failure; ture of the board was modulated; a strong corre- after initial photodocumentation, the assembly lation was noted between higher board tempera- was put into functional testing using an appli- ture and reduced load current provided by the cation test bench. Initial results were disheart- failing output. With the failure verified and char- ening, to say the least; the assembly functioned acterized, the next step was to isolate the prob- as designed, with supply current and output lem; in this case, isolation was done completely levels within specifications. In the absence of non-destructively, by tracing the circuit from the any reproducible failure mode, an analyst must failing output back until an unexpected high re- rack their brain, grasping at any explanation for sistance (48,000 ohms) between two points on why the product has miraculously returned to the same node was noted (Figure 2). normal function. Could the product have been With the failure verified and isolated to a improperly used by the customer? For example, relatively small area, non-destructive testing were all connectors fully seated? Were power procedures were performed. For PCB failures, supply voltages stable and held at the correct X-ray analysis and optical inspection are chief levels? Had this board been processed with a among the non-destructive approaches avail- top secret, self-healing material pulled straight able; other techniques, like acoustic microsco- from the annals of science fiction that had re- py, are more appropriate for component-level paired whatever defect was responsible for the failures. At this point in the process, an ana- initial failure (hopefully not, lest our intrepid lyst would inspect for cracked solder joints or analyst find himself out of a job)? broken PCB traces, misaligned via drills, or any Fortunately, in this case, our analyst was res- other anomalous features that might help to ex- cued from the throes of despair and his search plain the failure mechanism; in this particular for a new career writing schlocky novellas about case, no issues were noted during non-destruc- autonomous, regenerating electronic assem- tive testing (Figure 3). While a negative result blies by a sudden change in the functional test like this may seem like no value added to the results: An output that was previously within analysis, in this case the data can be used to rule specifications suddenly dropped out, with only a fraction of the expected current being sup- plied to its load. Though our analyst rejoiced at being returned firmly to the realm of reality, these results indicated that the most likely root cause of failure would be hard to pin down—an intermittent connection. The initial functional test led to several key observations that helped to characterize the fail- ure. Initially, the assembly worked as intended, but after some period of time under power, the device would fail. Furthermore, the failure was not a “hard fail” (i.e., a short circuit or open cir- cuit); power was still being supplied to the output pin, but insufficient drive current was available. After repeating the functional test and seeing the Figure 2: Photograph of the area of interest. High same failure characteristics, it was hypothesized resistance was measured between Pin 19 and the that some thermal effect (thermal expansion, for capacitors connected to Via 1.

78 SMT Magazine • September 2013 the art of failure

a study in pcb failure analysis: the intermittent connection continues out certain types of defects (e.g., a crack in the copper trace between the two points as a result of warping of the PCB is unlikely). The next step in the failure analysis process, revealing the defect, would almost certainly involve destruction of the board; as a result, a strong hypothesis was necessary before embark- ing upon any further analysis. In order to de- termine the best course of action, our analyst reviewed the facts as they stood:

1. The failure can be thermally modulated— as board temperature increases, the failure be- comes more pronounced. 2. In the failing condition, high resistance Figure 4: Higher magnification X-ray image of the is measured between two points on the same PCB area of interest. The blue dashed line and node. This high resistance results in reduced arrows represents the direction and location of output current. cross-sectional analysis for Pin 19. 3. No signs of solder quality issues—crack- ing or non-wetting—were noted in the area of the failure. for this type of failure would be at the connec- 4. X-Ray inspection did not reveal any signs tion between the copper trace and the barrel of of damage to the copper trace between the two a via or plated through-hole; given this hypoth- suspect points. esis, the analyst elected to cross-section through the PTH for the suspect pin (Figure 4). Given this list of facts, our analyst deter- The area of interest was cut away from the mined that the most likely cause of failure was bulk of the PCB and encapsulated in epoxy. A an intermittent contact between the two points cross-section was performed by grinding into in question that became worse under thermal the suspect pin with progressively finer grits expansion (as the board materials heated and of polishing abrasive, finishing with a sub-mi- expanded, less material remained in contact to cron polishing compound to bring the sample conduct electricity). The most likely location surface to a finish suitable for high magnifica- tion imaging. The PTH was imaged with a high power optical microscope; as hypothesized, an incomplete connection between the copper trace and the PTH barrel was noted (Figures 5 and 6). The analyst had the proverbial smoking gun; now, the only remaining step was to tie the physical defect to its most likely cause. Though the physical defect had been re- vealed, the analyst’s job was not over; the goal of any failure analysis project is to find the root cause of failure and determine the most likely origin of any existing defect. Of the many pos- sible explanations for this type of failure, two were considered as the most likely candidates:

• Mechanical stresses (vibration, thermal cy- Figure 3: X-ray of the failed PCB area of interest. cling, board flexure) may have broken a trace No anomalies observed. that was originally well connected

September 2013 • SMT Magazine 79 the art of failure a study in pcb failure analysis: the intermittent connection continues

Figure 5: Photograph of the cross- Figure 6: High magnification image of the cross- sectioned Pin 19. sectioned Pin 19. The red circle indicates the location of the separated via ring.

• Insufficient etchback or smear removal part to produce actionable data that suppliers (follow-up after drilling holes in the board) was and manufacturers can use to improve their performed during the PCB manufacturing pro- product. Despite starting with little more cess, preventing a good bond between the bur- than a nebulous problem description (“this ied traces and the barrel doesn’t work”), the analyst was able to me- thodically work towards a more comprehen- If mechanical stresses were the root cause sive explanation of the failure; in doing so, of this failure, an analyst would expect to see an expensive chunk of scrap was transformed much more damage to the PCB’s copper traces into a valuable source of knowledge, identify- (some degree of tearing or other stress-related ing a process weakness and helping to prevent cracking); other than the separation from the further defective product from reaching end barrel wall, no such damage was noted. Improp- users. Future columns will continue to pro- er cleaning and etchback during manufactur- vide other approaches to failure analysis of ing, on the other hand, could very well result in printed circuit assemblies, components, and an incomplete bond between a buried trace and other electronic devices; in the mean time, the via barrel. The defect was therefore classified keep an open mind, and remember that fail- as most likely occurring during manufacturing. ure is nothing more than an opportunity to Corrective action was implemented by adding improve! SMT additional inspection and destructive physical analysis on incoming PCBs per IPC-A-600 as part of production screening; as a result, other Derek Snider is a program failures similar to this were found before reach- manager and failure analysis ing the end user, and the PCB manufacturer was engineer at Insight Analytical able to identify and correct an inadequacy in Labs, Inc., a company providing their process. failure analysis services to aero- space, medical, and semicon- Conclusion ductor manufacturing industries In this case study, we examined how the worldwide. To contact Snider, click here. failure analysis process enables a defective

80 SMT Magazine • September 2013 Working on your Strategic Plans for the Future?

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Molex to Acquire FCT Multitest Provides Solutions for ICs Electronics Group and Mobile Devices According to Tim Ruff, Molex senior VP of busi- The MT2168 pick-and-place handler offers a vari- ness development and corporate strategy, this is ety of smart features that meet the special require- a strategic acquisition that will help expand the ments of ICs for mobile devices. The MT2168 fully company’s presence in the medical electronics, in- supports advanced packaging. dustrial, telecom, and aerospace markets. Manncorp Installs Systems at Calsonic Kansei Mexicana Europlacer: Flexible Problem Solving Calsonic Kansei Mexicana S.A. de C.V., a subsidiary for Microtech of Japan’s Calsonic Kansei Corporation, recently Europlacer, a manufacturer of market-leading flex- purchased two ULTIMA STR2 selective solder sys- ible SMT placement machines, announces that tems and an ULTIMA SSP selective fluxer from Microtechrecently purchased an iineo system. Manncorp.

Arrow Electronics Reports Q2 Revenue Nordson ASYMTEK Launches of $89.9 Million Spectrum S-820-C Arrow Electronics, Inc. has reported second-quar- Nordson ASYMTEK, a Nordson company, a lead- ter 2013 net income of $89.9 million, or $.86 per er in dispensing and jetting technologies, has re- share on a diluted basis, compared with net in- leased its Spectrum S-820-C stainless steel dispens- come of $114.4 million, or $1.02 per share on a ing system that is third-party certified for Class 100 diluted basis in the second quarter of 2012. cleanroom use.

Indium8.9HFA Solder Paste Welcomed GOEPEL’s Inspection System Features by Industry New Camera Indium Corporation’s Indium8.9HFA solder paste GOEPEL electronic offers an internally-developed is a versatile, halogen-free, lead-free, solder paste camera and illumination system for optical inspec- with leading print performance on miniaturized tion of selective solder joints to be integrated into external test cells. The integration package con- components. Assemblers and OEMs are adopting tains a specifically designed four-megapixel BUZ- this new product at an accelerating pace. ZARD camera with GigE interface, multispectral illumination, a PC, and respective software. Dymax Debuts GA-140-SC Cure-In-Place Gasket Nordson ASYMTEK Improves Dymax has introduced GA-140-SC, a UV/Vis- Dispensing Speed ible light-curable, form-in-place and cure-in-place Nordson ASYMTEK, a Nordson company, has de- gasket. Formulated with patented See-Cure tech- veloped continuous path motion control software nology, GA-140-SC is bright blue in an uncured for jetting underfill for flip chips. The software -op state, enabling confirmation of placement prior to timizes dispense head motion, saving time and cure. increasing units per hour (UPH).

82 SMT Magazine • September 2013 column smt trends & technologies Doing More Than One Thing at a Time

by Eric Klaver Assembléon

With women being renowned for multitask- not. These include cleaning, lubricating and ing abilities, perhaps they should be designing attending to standard checklist actions. Best of production lines—it could make our processes all, performing these actions while production more efficient. is still going will actually keep your machines Look at maintenance. Although hardware in better condition than waiting for scheduled can last for years, it will pick up dirt during maintenance (well, as long as rush jobs don’t production—with just how much varying from delay your scheduled maintenance). shift to shift. You can plan fixed maintenance We do, however, need new tools to help. The slots per day, week or other fixed period but pro- rapid acceptance of smartphones and tablets duction goes down during those slots. If rush mean they are ideal for smart production envi- jobs are going through you might be tempted ronments (Figure 1). Such methods are already to skip maintenance actions, but that will have being used for verification and reel replenish- consequences. KPIs will drift outside control ment/warning notifications, which you can re- limits, and you may be forced to stop produc- act on and immediately make corrections. But tion altogether for repairs. what about in between those times? At the heart of the problem are the traditionally fixed roles of operators, technicians and supervisors, which can lead to a lack of cooperation. Cleaning and inspection is often not the opera- tor’s responsibility, with equipment faults and failures requiring calling in the technician. There is no real feed- back loop, with fixed maintenance schedules rigidly telling people what to do and when. And audits generally only look for compliance that mainte- nance has taken place—not its effec- tiveness. Maintenance is thus viewed as a cost or penalty to production, rather than a benefit to productive output and pre- dictability. It is seen as less important than just keeping the line running.

Maintenance: No Need to Interrupt Production While some major maintenance items require the line to be stopped, Figure 1: Rapid consumer use of smart devices makes them many small maintenance steps do ideal tools for use in production.

84 SMT Magazine • September 2013 smt trends & technologies doing more than one thing at a time continues

Smartphones and tablets can combine with be some minimum value that will be best for all intelligent maintenance procedures. They help the occupants. If the temperature varies say 3°C track all the required actions, and remind you if or F around this minimum, there will be little you forget or don’t have time for any of them. loss—people will hardly notice. Another 3° one As long as these actions are performed in time, way or the other and some people will feel a bit they can be done at any moment—effectively uncomfortable. Another 3° and more people customizing the standard manufacturer’s sched- will start to lose concentration. Another 3° and ule to your actual production situation. people will start shivering or sweating and will How can you fit all these actions in, though, want to get away from the office so they can be when your system is up and running? In real- comfortable again. When you hit specification ity, there are plenty of small stops: during a pro- limits—the legal minimum or maximum—peo- duction pause somewhere in the line, or during ple need to put down tools and leave the office. stencil cleaning, parts supply, changeovers, set- Each 3° increase or decrease from the optimum ups or many other temporary stops. These are has greater effect than the previous 3°. the exact timeslots where people could perform Similarly, the loss from your processes quick, necessary maintenance actions. doesn’t suddenly step up when the variation hits specification limits. Outside specification Taguchi and Loss limits you get massive losses, it’s true: loss of It’s all about working as close as possible production, loss of expensive components and to the minimum of the Taguchi loss function boards and—most important of all—loss of you (which shows loss vertically and variation hori- and your customer’s reputation. Just meeting zontally). Taguchi showed that costs don’t sud- specifications is not good enough, though. If denly step up as variation goes outside specifi- placement variation is at one extreme and (for cation limits (Figure 2). When a process runs at example) stencil variation is at the other ex- its optimum, the losses are at a minimum. As treme then you can still get rejects. The larger you move away from optimum, the losses rise the variation in process, the more rejects your exponentially. process will produce, even if each individual Pete Jessup of Ford Motor Company gave an process is within specification limits. example that explains this perfectly: What is The most important decision is of course when the best temperature for an office? This will be to buy new equipment, since that sets the over- different for everyone, of course, but there will all position of the curve—and your overall losses

Figure 2: As a process varies either side of optimum, the losses rise exponentially.

86 SMT Magazine • September 2013 smt trends & technologies

doing more than one thing at a time continues over the years that you’ll be using the equipment. chine more often and so are more likely to spot Once you’ve installed your production line you other potential defects. That in turn makes your need to keep losses at a minimum. Maintaining line more predictable—so you can meet the equipment during spare moments does exactly commitments you’ve made to your customers. this. It keeps your line performing at its best, and Closed-loop maintenance does require disci- keeps your losses to an absolute minimum. pline and drive from your operators, but it en- courages greater ownership and teamwork to re- Closed Loop Maintenance duce variation and waste—always a good thing Closed-loop maintenance draws the equip- for your overall equipment efficiency. ment manufacturer into the loop along with Smarter maintenance complements smarter the operator, technician and supervisor—all software and smarter hardware. And for surface share responsibility for equipment care. That mount assembly, multitasking is at the heart means helping to train and support the operat- of it. It effectively gives you an extra shift a ing and maintenance team, monitoring results week. SMT with the production team, and defining correc- tive actions. Assembléon’s recent closed-loop mainte- Eric Klaver has been with Assem- nance package is tablet-based for immediate bléon since 1998. He is currently feedback and action, and is an extension of to- the chairman of IEC work group tal productive maintenance (TPM). Operators, TC40WG36, which specializes in technicians and supervisors work together to component packaging. To contact co-ordinate shift maintenance tasks for fewer Klaver, click here. breakdowns. People pay attention to the ma-

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September 2013 • SMT Magazine 87 SMTonline Market News Highlights

Global Smart Grid Technology to Tablets Shipments Soar in Q2; Grow $220B by 2020 Up 43% YoY With the smart grid core and enabled technology Over 34 million tablets shipped in Q2 2013, a market expected to grow to $220 billion by 2020, 43% year-on-year increase. Tablets now account the smart grid is seen by many utilities around the for 31% of worldwide PC shipments, but Apple’s globe as the ticket to addressing the escalating performance faltered. Its tablet shipments de- demand for reliable power, renewable energy in- clined 14% on Q2 2012 and its market share tegration, and greater energy efficiency. dropped to 43%.

Global Mobile Phone Market Up Key Raw Material Demand to Double 6% in Q2 as LED Market Booms The worldwide mobile phone market grew 6.0% Global demand for precursor, a material used in year-over-year in the second quarter of 2013 manufacturing of light-emitting diodes (LEDs), (2Q13). According to the IDC Worldwide Quar- is set to more than double from 2012 to 2016, terly Mobile Phone Tracker, vendors shipped a to- as the market for LED lighting booms, accord- tal of 432.1 million mobile phones in 2Q13 com- ing to a new report entitled “Precursor for LED pared to 407.7 million units in the 2Q12. MOCVD—Market and Industry Analysis,” from Displaybank. Global Semiconductor Industry to Reach $394 Billion In 2017 Global Semiconductor Revenue to The Asia Pacific (APAC) region represents approx- Rise 6.9% in 2013 imately 75% of the global market. Some of the The SAF also forecasts that semiconductor rev- major players include Intel Corporation, Samsung enues will grow 2.9% year-over-year in 2014 to Electronics, Taiwan Semiconductor, Texas Instru- $329 billion and log a compound annual growth ments, and Toshiba Corporation. A combination of rate (CAGR) of 4.2% from 2012-2017, reaching factors influences market dynamics tremendously. $366 billion in 2017.

Market & Technology Drivers to Bring U.S. to Witness Uptick in Economy 3D-IC to Production in 2014 With semiconductor technology moving toward The U.S. economy is in for another year of systematic integration of stacked heterogeneous sluggish growth in 2013, but a rebound in chips and 3D-IC becoming a mainstream trend, the housing market is expected to lead to the latest developments will be featured at 3D- stronger gains next year, according to The Con- IC & Substrate Pavilion and Advanced Packag- ference Board of Canada’s U.S. Outlook, Summer ing Technology Symposium at SEMICON Taiwan 2013. 2013 and the SiP Global Summit 2013. Small Cells Market to Grow, 3D Scanning Market to Reach $4.08B Rise 125% in 2014 by 2018 In ABI Research’s latest forecast, overall enterprise The global 3D scanning market is forecast to grow and consumer Femtocell shipments will reach from an estimated $2.06 billion in 2013 to $4.08 5.7 million units in 2014 compared to 3.8 mil- billion by 2018, at an estimated CAGR of 14.6% lion units in 2013. While 3G indoor small cells from 2013 to 2018. Recent industry trends show will continue to represent the vast majority of the technology is continually improving—right shipments, LTE indoor small cells are expected to along with demand. ramp up significantly.

88 SMT Magazine • September 2013 column a short scoop Step Stencils, Part 2: Applications and Solutions

by Rachel Short PhotoStencil LLC

In my last Short Scoop, (The Ins and Outs 5. Thick stencils with reservoir pockets for of Step Stencils, Part 1) you heard a little about printing glue on a variety of components step stencils—what they are, why demand is in- with different stand-off heights creasing, different types, and what to look for. 6. Two-print stencils with relief pockets for In this column, we explore step stencil applica- printing component attachment glue tions and solutions. after SMT solder paste has been printed 7. 3-D electroform stencils with a formed Step stencil applications fall into eight cat- relief pocket for a high profile flex egories: connector

1. Step-up stencils for ceramic BGAs The following is a breakdown of these eight 2. Step-up stencils for intrusive reflow of categories. through-hole components 3. Step stencils with a relief pocket on the Ceramic BGAs contact side (board side) for: Ceramic BGAs (CBGA) present a problem to a. Raised vias the SMT assembly process. Slight variations in b. Bar codes ball co-planarity can result in an open contact c. Board hold-down clips to the balls. Printing higher solder bricks on the d. Additive traces CBGA pads can prevent this. Normally, a brick height of 7-8 mils is desirable, but .5 mm pitch 4. Step stencils for two-print applications QFPs, 0402 chip components, and R-packs will using mixed technology not tolerate an 8 mil thick stencil. Aperture sizes a. SMT/through-hole are too small to achieve good paste release with b. SMT/RF shield such a thick stencil. Therefore, c. Flip chip/SMT a step-up stencil is required.

90 SMT Magazine • September 2013 Designers: when you choose a fabricator, what guarantee do you have that they won't deliver scrap?

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A PCB AUDITING COMPANY www.nextlevelpcb.com a short scoop step stencils, part 2: applications and solutions continues

Intrusive Reflow of Through-Hole etched on the contact side of the stencil wher- Components ever there is a raised via. Typically, the relief There has been a trend to reflow through- pocket depth is one-half the stencil thickness, hole components with SMT components rather usually enough to clear the obstruction. than wave soldering them. For this applica- 2. Bar code on the PCB: A stencil with a re- tion category, solder paste is printed in and lief pocket etched in the area of the bar code around the through-hole and pad. Three ways allows the stencil to sit flat on the PCB during to achieve sufficient solder paste for this appli- printing and allows proper stencil gasketing in cation are: areas with adjacent print features. 3. Board hold-down clips: Some stencil 1. Overprint the hole/annular ring with an printers have edge clips to hold the PCB down oversized stencil aperture. during printing. If component pads are close to 2. Step-up and overprint the hole/annular the edge of the board, the stencil may not be ring with an oversized stencil aperture. able to gasket to the board on the edge and a 3. Two-print stencil where the second print relief pocket will be needed. stencil is very thick and provides more 4. PCB with additive traces: Traces added solder paste for the through-hole. to the PCB surface correct design problems by altering the lead wiring, but the trace adds Relief Etch Pocket on the Contact Side height. A relief pocket around the additive trace Relief pockets on the PCB side of the stencil will solve the problem. provide relief clearance for raised areas on the PCB, allowing good gasketing of the PCB to the Two-print Applications for Mixed stencil. Some common relief-etch applications Technology are: 1. SMT/through-hole mixed technologies: When overprint (oversized apertures for the 1. Raised via pads on the PCB: These features through-hole) with a normal step-up stencil prevent the stencil from gasketing to the PCB. doesn’t provide enough solder paste volume for For good stencil/board contact, a relief pocket is proper intrusive reflow, a thicker stencil must be used. The problem is SMT components won’t tolerate a 15–20 mil thick stencil and a step down from 20 mils to 5 mils won’t work well. For this situation, the two-print stencil opera- tion is a viable solution. The only alternative to providing more solder paste is to make the sten- cil thicker. In the two-print operation the SMT solder paste is printed with a normal 5 or 6 mil thick stencil. The second 15–20 mil thick stencil provides increased depth SMT paste relief pock- ets etched on the contact side to clear first print solder features. 2. SMT/RF Shield: Small hand-held commu- nication devices usually have RF shields posi- tioned very close to small SMT components. Additional paste height is required for the RF shield, requiring a thicker stencil than the thick- ness required for the SMT components. The spacing between the RF shield and the compo- nents prevents the use of a normal step stencil. The two-print option provides a solution when Figure 1: Nickel stencil with relief pocket. the distance between RF shield and SMT com-

92 SMT Magazine • September 2013 a short scoop

step stencils, part 2: applications and solutions continues ponents is as small as 15 mils (.38 mm) with paste height up to 8 mils (.2 mm) for the RF shield. 3. Flip chip/SMT mixed technologies: Some- times it’s desirable to print flux or solder paste for a flip chip component and solder paste for SMT devices. Both are then placed and run through the reflow cycle. Normally, the stencil thickness for the flip chip printing is much too thin for SMT printing. Once again, two-print stencils are an ideal solution. A thin (1–2 mil) electroform stencil prints either flux or solder paste on the flip chip pad sites. A second 5 mil thick SMT stencil is then used for solder paste. Relief pockets are formed on the contact side anywhere flip chip flux or paste was previously Figure 2: Electroformed step stencil, 5 mil base, 7 printed. mil step areas, with apertures.

Printing Glue for Components with Different Stand-off Heights 3D Stencils with Flex Circuit Relief There are advantages to printing glue rather Imagine two PCBs that are connected with than dispensing it. Set-up and process times are a flexible connector that rises 90 mils above the shortened since glue bricks are deposited in par- board surface and that is obstructing a normal allel rather than one dot at a time. Glue does stencil from making contact with the board. not print the same way as solder paste and it How do you print solder paste on the SMT pads is acceptable as well as useful to leave some of with the connector in the way? The solution is the glue remaining inside the stencil aperture. a 3D electroform stencil that is 5 mils thick, but Large apertures will release all the glue while has a 95 mil high relief pocket formed into the small apertures will release only a portion of the stencil. In order to apply the paste, a custom E- glue, which is useful for different component blade was formed with a notch for clearance of stand-off heights. An example is an application the relief pocket. with a chip component with a 4 mil stand-off, Step stencils provide unique solutions to a a 15 mil stand-off SOIC, and an SOIC with a wide range of complex printing applications. 30 mil stand-off on the same board. To achieve By tailoring the stencil to specific applications, height differentials, aperture sizes can be ad- a wide range of processing parameters for justed to provide glue height variation, or for thickness and aperture size can be achieved. applications requiring thicker glue deposition a Step stencils can easily accommodate varied print/controlled flood feature or a glue reservoir solder heights, mixed technologies, and even, stencil may be employed and can achieve glue in conjunction with two-print stencils, appli- deposition up to 50 mils. cation of dissimilar materials onto the same board. SMT Two-Print Glue and Solder Paste Application In this application the applied glue is thick- er than the solder. Solder is first applied using Rachel Short is vice president standard application techniques. A two-step of sales and marketing at stencil with formed reliefs is then used to apply PhotoStencil LLC. She may be the thicker glue. This application is attractive reached via e-mail, or by phone for glue attaching large chip devices for second at 719-304-4224. pass reflow.

September 2013 • SMT Magazine 93 column evolutionary solutions Deciding by the Numbers

by Karla Osorno EE Technologies, Inc.

In a contract manufacturing environment, cific data is value added and then establish thousands of decisions are made daily. Deci- methods of collection. Training employees on sions that have consequences on the end prod- the methods of collection and the reasons for uct are made by workers, middle managers and collection is also important. And of course, us- senior managers. These decisions are made on ing the data collected will speak volumes to the line, in support areas, and in conference the employees and increase their motivation to rooms. They are made months in advance and continue collection. When the data is collected in minutes, as the product moves throughout and not used the consequences can be costly to the production area. Organizations that suc- morale and profits. ceed in the short and long term create a culture Whether your plant has two employees, where data is always used for decision making. 200 or 2,000, each individual choice or deci- sion made by an employee creates a result. And Value of Data Based Decisions these results become an input in the next pro- Making decisions using data and metrics is cess step. This has a direct impact on the final one of the most important activities a manufac- products produced in your plant. turer can take on. Collecting the data is critical Most manufacturing plants will have pro- to understanding the operational performance. cesses and process controls that limit the num- Each company will want to choose which spe- ber of decisions required by the employee. As-

94 SMT Magazine • September 2013 2013 meptec SDUEMICON CTOR ROADMAPS SYU MPOSI M A Collaborative Update from Standards Bodies, Industry Groups, and Large OEMS

September 24, 2013 • Biltmore Hotel, Santa Clara, CA

n the spirit of collabora- metrics of progress. tion, this event will con- During its long and success- sist entirely of panel dis- ful existence, MEPTEC has rec- Icussions, rather than tra- ognized the need for one essen- ditional presentations. This tial ingredient above all others will allow for more interac- in achieving success with any tion among the speakers semiconductor industry road- and attendees, so that the maps: collaboration. synergies, gaps, and differ- First, collaboration among ences of opinion can be trade associations, standards explored more thoroughly. groups, OEMs, providers of A day full of panel discus- analytic and design software, sions will also allow repre- sub-contract service providers, sentatives of more compa- and suppliers throughout the nies, including device man- supply chain is increasingly The Biltmore Hotel is conveniently located at 2151 Laurelwood Road ufacturers and large OEMs, critical to success. Second, as in Santa Clara, CA in close proximity to the San Jose Airport. and industry and standards distinctions among semicon- organizations, to present ductor processing, packaging their views. Join us for this and assembly technologies, and Symposium Topics will include: first-of-a-kind collaborative design/testing protocols are dis- event! n Market Drivers – the current and future products that contin- appearing manufacturers have ue to drive semiconductor packaging down the road of “smaller, greater need for collaboration. faster, and cheaper” – logic, memory, power, other (including Over the years, MEPTEC’s The MEPTEC Roadmap MEMs and sensors) popular Roadmaps events have event will bring together stan- been attended by high level dards groups, industry groups n Packaging needs expressed by the major device manufactur- ers (ODMs), the end customers (OEMs), and the assembly and managers, CEOs, and CTOs, and consortia, industry experts, test suppliers (OSATs and EMS) Non-mechanical performance looking for validation and in- device manufactures, and rep- needs including interconnections, transmission speeds, switching sight into technology and busi- resentatives of the large OEMS protocols, new reliability requirements. ness directions for their compa- to update their roadmaps and nies, for their suppliers and, in development activities, which n Non-mechanical performance needs including interconnec- some cases even their custom- may include 2.5D/3D as well as tions, transmission speeds, switching protocols, new reliability requirements. ers. At past events they, and their other driving factors pertinent to competitors who were present- their business segments. Join us n Status of efforts of various Consortiums, Standards groups ing their own roadmaps, were for this first-of-a-kind collabora- and trade organizations to support their members and to help looking for strategic help and tive event! ◆ establish infrastructure.

REEGIST R ONLINE TODAY AT WWW.MEPTEC.ORG

Media Sponsors evolutionary solutions deciding by the numbers continues suming employees follow these processes and ask specific questions that require use of data documented procedures, the impact of poor that has been collected. For example, an inspec- decisions can be mitigated. The reality is that tor who states that there is a “problem with a most manufacturing processes are complex and line producing defective products all the time” documenting every scenario is next to impos- may be asked “in how many of the last eight sible. weeks was the quality below the company tar- Throughout a typical eight-hour shift, an get?” and “how far below the target was the employee may make multiple decisions. For ex- quality each of the eight weeks?” This requires ample, if each employee makes even 10 deci- the inspector to have the required data rather sions, a simple math calculation shows that this than solely an opinion or feeling that the re- equates to 20-20,000 decisions made in a plant sults are unsatisfactory. in just one shift. Area leaders also want their teams to emu- The goal of manufacturing leadership is to late their behavior by providing evidential data reduce variability in an effort to achieve stra- to support pending and prior decisions. A pro- tegic objectives that include providing qual- duction supervisor who authorizes overtime ity products on time and at the best cost. This should be able to show data that the cost of many decisions made in just one shift can cre- overtime for completion of a project is a bet- ate much variability. This variability is signifi- ter decision than adding new team, rather than cantly reduced when a culture of metric or data simply responding to an emergency situation based decision making is created. and using overtime to cover other is- sues. Or imagine your joy when Creating the Right Culture a materials lead provides data With intention, senior A production supervisor showing the root cause of a management can create and “ late shipment, along with a cultivate a culture of us- who authorizes overtime new procedure correcting this ing the data for decisions. It should be able to show issue. Simply acknowledging starts with defining expecta- teams for using accurate data tions and casting vision for data that the cost of (and for not using inaccurate what the culture will look data) will go far in cultivating like. Keeping it simple and overtime for completion a culture of accountability easy to duplicate is the way of a project is a better through metric-based deci- to go. sions. This is not about praise Once the expectations decision than adding or correction. By acknowledg- are communicated to the new team, rather than ing with a simple statement company, everyone will be of fact, the leader lets the on high alert to see if behav- simply responding to team know they are noticed ior matches what was stated an emergency situation and reinforces expectations by senior management. Ac- for data use. Acknowledge- knowledging progress and and using overtime to ment is highly motivating not perfection will go far to cover other issues. and increases the vitality of creating a sustainable culture. employees. Managers can set the ex- Leaders who repeatedly ample by asking questions that make hurried or random deci- require data, by asking for evi- sions are not cultivating a culture dence to support decisions, by acknowledging of data-based decisions. But neither are lead- all data-based decisions, and by avoiding any” ers who sit ondata and never make a decision. appearance of “flying by the seat of their pants.” Finding the right balance of analysis and action Middle managers and employees will emu- is extremely important. In most instances, cul- late what they are shown by their leaders. Lead- tivation of the right culture trumps the specific ers working with teams to solve problems can decisions and related consequences. It is worth

96 SMT Magazine • September 2013 evolutionary solutions

deciding by the numbers continues taking the time to ask a few key questions to make the data collection method selected more get the data and avoid a “fly by the seat of your effective. pants” culture. When the data is collected Course Corrections and used consistently and con- For each data collection tinually and when major deci- topic, you will undoubtedly sions are made with the data, Another important have a specific target or goal a culture of accountability is consideration“ is the you are trying to reach. As created. In this type of cul- your team moves toward the ture, there is an effect on mi- length of time the data desired result, the data will nor decisions too. Employees collection will cover. If help to assess performance at all levels of the company the situation is temporary and to take corrective action realize the impact of their as needed. This only works if decisions and activity. This then the data collection you are looking at the data recognition of their impact method will be less formal often enough to make course increases their morale, the or systematic. If the corrections. The frequency quality of their decisions, and of review will depend on the therefore the results. situation is more ongoing data, method of collection, then the method of data and result being tracked. Data Collection Methods Data review and course There are many methods collection may start less correction responsibility can of data collection. Typically, formally and ultimately be defined so that the appro- the best approach for decid- become automated. priate actions can be taken ing which method to use is in a timely fashion. Having a to start with the end in mind. culture of acceptance of course What problem will the data be correction is vital also. Course used to solve? What questions need correction is not necessarily in re- to be answered? With this information you will sponse to a problem. have more of an idea of the best method to use.” Using data-based decision making in manu- Another important consideration is the facturing is like an airplane journey. From Brian length of time the data collection will cover. Tracy’s book Flight Plan—The Real Secret of If the situation is temporary then the data col- Success, all airplanes are off course 99% of the lection method will be less formal or system- time. He explains that the pilot and avionics are atic. If the situation is more ongoing then the continually bringing the plane back on course. method of data collection may start less for- Your purpose as a leader and as an employee mally and ultimately become automated. Au- is to move your organization to its strategic des- tomation is great but not always required. Ben- tination. Wherever you find yourself culturally efits of automation must be weighed against and operationally as an organization, take steps the costs. today to move toward by the numbers and reap Manual tracking, spreadsheet tracking, and the rewards you have sown. SMT database tracking are common methods for col- lecting data. Extensive data tracking systems have also been developed in house or propri- Karla Osorno is business develop- etary systems purchased. These systems have ment officer for EE Technologies, an initially high cost. However, the savings Inc., an EMS provider delivering achieved with fewer production issues often complete engineering and manu- outweigh the initial costs. facturing services with locations Including the end user and the data col- in Nevada and Mexico. To read lection team in these discussions is benefi- past columns or to contact Osorno, click here. cial as they can each provide insight that will

September 2013 • SMT Magazine 97 Top Ten News Highlights from SMTonline this Month

Sanmina Q3 Profit Lead-Free Soldering a Improves c technology Symposium at SMTAI “I am pleased with our third quarter results. We continue to benefit from improved efficiencies and The SMTA will hold the Lead-Free Soldering Tech- favorable business mix. Our outlook for the fourth nology Symposium October 17, 2013 as a focused quarter is modest growth with further improve- symposium at SMTAI. The focus is on the findings ments in our operating model,” stated Jure Sola, of three industry consortia related to the advance- chairman and CEO. ment of lead-free technology.

Top Electronics Execs Plan Kitron Overcomes b Gathering in September d Challenging Markets; revenue Up 3.3% IPC announces its IPC Management Meetings, a forum for company leaders to gain a high-level Kitron’s revenue for second quarter amounted to perspective on technology, market trends, and NOK 430.3 million, a 3.3% increase compared management issues, will be held September 24, with the same period last year. EBIT was reduced 2013 in Chicago and open to senior executives. from NOK10.6 million to NOK 9.3 million for the second quarter.

98 SMT Magazine • September 2013 ble engineers have up to one year to complete the IEC’s Revenue Remains online program. e Negative in Fiscal Q3 CTS EMS Q2 Revenue Down For the quarter ended June 28, 2013, the com- h on Market Weakness pany reported revenue of $35,154,000, and net income of $382,000 or $0.04 per diluted share. W. Barry Gilbert, chairman of the board and CEO, CTS CEO Kieran O’Sullivan, stated, “We improved stated, “While revenue and earnings are down earnings and have taken steps to simplify our from the same quarter last year, we made quite manufacturing footprint while improving operat- a bit of progress from the $1.1 million loss in the ing margins. We are focused on the challenges in second quarter.” our EMS business…”

NBS Moves to New Facility; i PartnerTech Reports 2.5% f boosts Operations by 50% sales Increase in Q2

“Second quarter sales were 2.5% higher for com- “Our latest move is a significant sign that our parable units and in local currencies than the same having extolled ‘Made in the USA’ beginning in period of 2012. Operating profit of SEK 3 million 2010 was much more than a slogan,” explained was lower than the second quarter of 2012, while Michael Maslana, president and CEO. “It is now both cash flow and operating capital turnover im- widely recognized as an attractive attribute and in proved,” said Leif Thorwaldsson, president and the context of ongoing industry discussion about CEO. re-shoring, our expansion demonstrates both a timely and meaningful continued commitment.” Kimball’s Nanjing, China SMTA Offers Online SMT j Facility Earns ISO 13485 g processes Re-Certification Certification Program “We are proud to now have ISO 13485 certifica- tion in all of our manufacturing facilities. The ad- The goal of the re-certification program is to pres- dition of this certification will allow us to support ent new materials which have been added to the our medical customers’ needs in the rapidly ex- certification curriculum since the initial sessions in panding healthcare market in China,” stated Tom 2003 and test that engineers have a competent Ferris, group director of medical business develop- understanding of the updated information. Eligi- ment.

smtonline.com for the latest SMT news— anywhere, anytime.

September 2013 • SMT Magazine 99 Calendar

PCB West 2013 September 24–26, 2013 Events Santa Clara, California USA ID WORLD Rio de Janeiro 2013 September 26–27, 2013 For the IPC’s Calendar of Events, click here. Rio de Janeiro, Brazil

For the SMTA Calendar of Events, click here. SAE 2013 Counterfeit Parts Avoidance Symposium For the iNEMI Calendar, click here. September 27, 2013 Montreal, Quebec, Canada

For a complete listing, check out 2013 SMART Group European Conference SMT Magazine’s full events calendar here. October 2–3, 2013 Oxfordshire, UK

NEXTGEN AHEAD RFID in High-Tech September 9–11, 2013 October 2–3, 2013 Washington, D.C., USA Santa Clara, California, USA

International Test Conference 2013 Long Island SMTA Expo and Technical September 10–12, 2013 Forum Anaheim, California, USA October 9, 2013 Islandia, New York, USA Capital Expo & Tech Forum September 10, 2013 IEEE SMC 2013 Laurel, Maryland, USA October 13–16, 2013 Manchester, UK 2013 MEPTEC September 17–18, 2013 electronicAsia Tempe, Arizona, USA October 13–16, 2013 Hong Kong, China Failure Analysis of Electronics Short Course SMTA International September 17–20, 2013 October 13–17, 2013 University of Maryland, Maryland, USA Fort Worth, Texas, USA

Electronics Operating in Harsh Environments Workshop September 17, 2013 Cork, Ireland

IESF 2013: Integrated Electrical Solutions Forum September 19, 2013 Dearborn, Michigan, USA

MRO EUROPE 2013 September 24–26, 2013 London, UK

100 SMT Magazine • September 2013 PUBLISHER: Barry Matties EDITORIAL ADVISORY BOARD: Bill Coleman, Ph.D., Photo Stencil Happy Holden, Gentex Corporation PUBLISHER: RAY RASMUSSEN Craig Hunter, Vishay (916) 294-7147; Dr. Jennie S. Hwang, H-Technology Group Michael Konrad, Aqueous Technologies SALES MANAGER: BARB HOCKADAY Graham Naisbitt, Gen3 Systems & SMART Group (916) 608-0660; Ray Prasad, Ray Prasad Consultancy Group MARKETING SERVICES: TOBEY MARSICOVETERE Steve Pudles, IPC (916) 266-9160; [email protected] S. Manian Ramkumar, Ph.D., Rochester Institute of Technology Robert Rowland, RadiSys Corporation Dongkai Shangguan, Ph.D., National Center for Advanced Packaging, China EDITORIAL: Vern Solberg, Independent Technical Consultant GROUP EDITORIAL DIRECTOR: RAY RASMUSSEN Gary Tanel, Electronics Alliance (916) 294-7147; Michael McCutchen, ZESTRON America MANAGING EDITORS: LISA LUCKE (209) 304-4011; [email protected], MAGAZINE PRODUCTION CREW: and Andy Shaughnessy PRODUCTION MANAGER: SHELLY STEIN (770) 315-9901; MAGAZINE LAYOUT: RON MEOGROSSI AD DESIGN: SHELLY STEIN, Mike Radogna TECHNICAL EDITOR: PETE STARKEY INnovative TECHNOLOGY: BRYSON MATTIES +44 (0) 1455 293333; COVER ART: BRYSON MATTIES and SHELLY STEIN

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September 2013, Volume 28, Number 9 • SMT© (Surface Mount Technology©) is published monthly, by BR Publishing, Inc.

Advertiser Index Next Month in Alpha...... 29 Indium...... 77 SMT Magazine:

Aqueous...... 9 Integral Technology...... 23 Lead-free Blackfox...... 49 IPC...... 65, 81 Developments

Bob Willis...... 71 Manncorp...... 5 It’s been more than seven years since RoHS became the BR Publishing...... 41 Meptec...... 95 law of the land in Europe. Candor Industries...... 53 NextLevel PCB...... 91 But many OEMs and EMS companies still find them- Dragon Circuits...... 31 Nordson Asymtek...... 83 selves facing increasing chal- EasyBraid...... 35 P Kay Metal...... 61 lenges related to lead-free processes. In October, SMT Eagle Electronics...... 19 PCB List...... 2, 89 Magazine shines a light on the often murky world of EE Technologies...... 85 Prototron Circuits...... 43 lead-free assembly. Electrolube...... 59 Semblant...... 15 If you’re not a subscriber, what are you waiting for? Hunter Technology...... 75 SMTA...... 3 Click here to receive SMT Magazine in your inbox each Imagineering...... 7 US Circuit...... 67 month!

September 2013 • SMT Magazine 101