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AMIDAR Processor Implementation of an AMIDAR-based Java Processor Implementierung eines AMIDAR-basierten Java Prozessors Zur Erlangung des akademischen Grades Doktor-Ingenieur (Dr.-Ing.) genehmigte Dissertation von Dipl.-Inform. Changgong Li aus Heilongjiang, China Tag der Einreichung: 02.10.2018, Tag der Prüfung: 08.04.2019 Darmstadt — D 17 1. Gutachter: Prof. Dr.-Ing. Christian Hochberger 2. Gutachter: Prof. Dr. Wolfgang Karl Fachgebiet Rechnersysteme Fachbereich Elektrotechnik und Infor- mationstechnik Implementation of an AMIDAR-based Java Processor Implementierung eines AMIDAR-basierten Java Prozessors Genehmigte Dissertation von Dipl.-Inform. Changgong Li aus Heilongjiang, China 1. Gutachter: Prof. Dr.-Ing. Christian Hochberger 2. Gutachter: Prof. Dr. Wolfgang Karl Tag der Einreichung: 02.10.2018 Tag der Prüfung: 08.04.2019 Darmstadt — D 17 Li, Changgong: Implementation of an AMIDAR-based Java Processor Darmstadt, Technische Universität Darmstadt, Jahr der Veröffentlichung der Dissertation auf TUprints: 2019 Tag der mündlichen Prüfung: 08.04.2019 Verfügbar unter lediglich die vom Gesetz vorgesehenen Nutzungsrechte gemäß UrhG Erklärung laut Promotionsordung § 8 Abs. 1 lit. c PromO Ich versichere hiermit, dass die elektronische Version meiner Dissertation mit der schriftlichen Version übereinstimmt. § 8 Abs. 1 lit. d PromO Ich versichere hiermit, dass zu einem vorherigen Zeitpunkt noch keine Promotion versucht wurde. In diesem Fall sind nähere Angaben über Zeitpunkt, Hochschule, Dissertationsthema und Ergebnis dieses Versuchs mitzuteilen. § 9 Abs. 1 PromO Ich versichere hiermit, dass die vorliegende Dissertation selbstständig und nur unter Verwendung der angegebenen Quellen verfasst wurde. § 9 Abs. 2 PromO Die Arbeit hat bisher noch nicht zu Prüfungszwecken gedient. Darmstadt, den 02.10.2018 (Dipl.-Inform. Changgong Li) Kurzfassung In dieser Arbeit wird ein Java Prozessor vorgestellt, welcher auf der Adaptive Microinstruction Driven Architecture (AMIDAR) basiert. Dieser Prozessor wird bereits als Forschungsplattform zur Untersuchung und Entwicklung adaptiver Prozessor-Architekturen verwendet. Mittels eines konfigurierbaren Beschleu- nigers ist er in der Lage, zur Laufzeit einer Applikation auf deren spezifische Anforderungen zu reagieren und somit deren Ausführungs-Performance dynamisch zu erhöhen. Gegenüber klassischen RISC-Prozessoren besteht ein AMIDAR-basierter Prozessor aus vier unter- schiedlichen Arten von Komponenten: einer Token-Machine, verschiedenen funktionalen Einheiten (FUs), einem Token-Verteilungsnetzwerk sowie einer FU-Kommunikationsstruktur. Die Token-Machine ist eine spezielle FU, welche die Ausführungen der anderen FUs steuert. Dazu übersetzt sie die In- struktionen in einen Satz von Mikroinstruktionen, den sogenannten Tokens, und sendet diese über das Token-Verteilungsnetzwerk an die entsprechenden FUs. Die Tokens teilen einzelnen FUs mit, welche Operationen auf den Eingangsdaten ausgeführt werden und an welche FUs die Ergebnisse anschließend geschickt werden sollen. Nachdem eine Operation ausgeführt wurde, wird deren Ergebnis an die FU- Kommunikationsstruktur übergeben, damit es an die vorgegebene Ziel-FU weitergeleitet werden kann. Für den Instruktionssatz, welcher durch den Java-Bytecode definiert ist, sind insgesamt sechs FUs mit bestimmten Funktionalitäten für den Java Prozessor entwickelt worden. Diese umfassen einen Frame Stack, einen Heap Manager, einen Thread Scheduler, einen Debugger, eine Integer-ALU und eine Floating-Point Unit. Mit diesen FUs kann der Prozessor bereits die SPEC JVM98 Benchmarks fehler- frei durchführen. Dies deutet darauf hin, dass er sich über eingebettete Software hinaus für ein breites Spektrum von Anwendungen einsetzen lässt. Neben der Bytecode-Ausführung beinhaltet dieser Prozessor auch einige erweiterte Funktionen, welche seine Leistung und Nutzbarkeit deutlich verbessert haben. Zum Ersten enthält er einen Objekt- Cache basierend auf einer neuartigen Methode zur Generierung der Cache-Indizes, welche eine bessere durchschnittliche Trefferrate bietet, als die klassische XOR-basierte Methode. Zum Zweiten ist ein hard- warebasierter Garbage Collector in den Heap Manager integriert, welcher den durch den Garbage Collec- tion Prozess verursachten Overhead erheblich reduzieren kann. Zum Dritten ist die Thread-Verwaltung ebenfalls komplett in Hardware umgesetzt und kann deshalb parallel mit der laufenden Anwendung durchgeführt werden. Außerdem ist ein Debugging Framework für den Prozessor entwickelt worden, welches mehrere mächtige Debugging-Funktionalitäten auf Hardware- und Software-Ebene bereitstellt. I Abstract This thesis presents a Java processor based on the Adaptive Microinstruction Driven Architecture (AMI- DAR). This processor is intended as a research platform for investigating adaptive processor architec- tures. Combined with a configurable accelerator, it is able to detect and speed up hot spots of arbitrary applications dynamically. In contrast to classical RISC processors, an AMIDAR-based processor consists of four main types of components: a token machine, functional units (FUs), a token distribution network and an FU intercon- nect structure. The token machine is a specialized functional unit and controls the other FUs by means of tokens. These tokens are delivered to the FUs over the token distribution network. The tokens inform the FUs about what to do with input data and where to send the results. Data is exchanged among the FUs over the FU interconnect structure. Based on the virtual machine architecture defined by the Java bytecode, a total of six FUs have been developed for the Java processor, namely a frame stack, a heap manager, a thread scheduler, a debugger, an integer ALU and a floating-point unit. Using these FUs, the processor can already execute the SPEC JVM98 benchmark suite properly. This indicates that it can be employed to run a broad variety of applications rather than embedded software only. Besides bytecode execution, several enhanced features have also been implemented in the processor to improve its performance and usability. First, the processor includes an object cache using a novel cache index generation scheme that provides a better average hit rate than the classical XOR-based scheme. Second, a hardware garbage collector has been integrated into the heap manager, which greatly reduces the overhead caused by the garbage collection process. Third, thread scheduling has been realized in hardware as well, which allows it to be performed concurrently with the running application. Furthermore, a complete debugging framework has been developed for the processor, which provides powerful debugging functionalities at both software and hardware levels. III Contents 1 Introduction 1 1.1 Motivation . .1 1.2 Research Goals . .1 1.3 Thesis Outline . .3 2 Technical Background 4 2.1 AMIDAR . .4 2.1.1 Overview . .4 2.1.2 ADLA . .5 2.2 Java . .7 2.2.1 Java in Embedded Systems . .7 2.2.2 Concurrency . .8 2.3 Java Runtime System . 12 2.3.1 Memory Model . 12 2.3.2 Object Access . 13 2.3.3 Garbage Collection . 15 2.3.4 Thread Scheduling . 20 2.3.5 Lock Models . 24 2.4 Priority Queue Architectures . 28 3 Related Work 33 3.1 Java Processors . 33 3.2 Object Caches . 35 3.3 Hardware Garbage Collectors . 37 3.4 Hardware Schedulers . 40 3.5 Hardware Debuggers . 44 4 Implementation 47 4.1 Overview . 47 4.1.1 Processor Microarchitecture . 47 4.1.2 Support for 64-Bit Operations . 49 4.1.3 Infrastructure . 50 4.1.4 Native Methods . 51 4.1.5 Executable Generation . 52 4.1.6 System Boot . 53 4.2 AMIDAR Executable Format . 53 4.2.1 Layout . 53 4.2.2 Header . 54 4.2.3 Table Section . 55 4.2.4 Info Section . 60 4.2.5 Data Section . 61 4.2.6 Static Resolution . 63 4.2.7 Evaluation . 67 4.3 Token Machine . 68 4.3.1 Decoding Pipeline . 69 4.3.2 Datapath of the Token Execution Module . 72 4.3.3 Execution of Tokens . 72 4.3.4 Exception Handling . 74 V 4.3.5 FU Interfaces . 77 4.4 Frame Stack . 78 4.4.1 Datapath Components . 79 4.4.2 Execution of Tokens . 81 4.4.3 Generation of Root Set . 83 4.4.4 Overflow Handling . 84 4.5 Heap Manager . 84 4.5.1 Memory Layout . 84 4.5.2 Components of the Heap Manager . 88 4.5.3 Object Cache . 93 4.5.4 Object Allocation . 101 4.5.5 Garbage Collection . 104 4.5.6 Wishbone Object Access . 117 4.6 Thread Scheduler . 117 4.6.1 Datapath Components . 117 4.6.2 Hardware-Software Interface . 130 4.6.3 Implementation of Thread Management . 138 4.6.4 Implementation of Java Monitor Construct . ..
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