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Load Byte Accumulator Chapter 4 Computer Architecture Computer Systems F I F T H E D I T I O N Pep/9 virtual machine Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 4.1 Hardware 185 Computer Systems F I F T H E D I T I O N Figure 4.1 Main memory FIGURE 4 . 1 Block diagram of the Central processing Pep/9 computer. Disk unit Input Output System bus Data flow Control Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Central Processing Unit (CPU) T e CPU contains six specialized memory locations called registers. As shown in FIGURE 4.2 , they are ❯ T e 4-bit status register (NZVC) ❯ T e 16-bit accumulator (A) ❯ T e 16-bit index register (X) ❯ T e 16-bit program counter (PC) ❯ T e 16-bit stack pointer (SP) ❯ T e 24-bit instruction register (IR) Central processing unit (CPU) FIGURE 4 . 2 The CPU of the Pep/9 N Z V C computer. Status bits (NZVC) Accumulator (A) Index register (X) Program counter (PC) Stack pointer (SP) Instruction register (IR) 9781284079630_CH04_Pass03.indd 185 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N Figure 4.2 Central processing unit (CPU) .:6# Status bits (.:6#) Accumulator ( ! ) Index register ( 8 ) Program counter (0#) Stack pointer (30) Instruction register ()2) Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Computer Systems F I F T H E D I T I O N Figure 4.3 Main memory 0000 0001 0002 0003 0004 0005 0006 . FFFE FFFF Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Computer Systems F I F T H E D I T I O N Figure 4.4 Main memory 0000 0003 0004 0007 000A 000B 000D . Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 000B 000B Computer Systems F I F T H 1E D I1 T I O0 N 1 0 0 0 Figure1 4.5 1 1 0 1 0 0 0 1 000C 000C 0 0 0 0 0 0 1 0 (a) The content in binary. (a) The content in binary. 000B 1 1 0 1 0 0 0 1 02 D1 02 D1 000C 000B 000C 000B 000C (a) The content in binary. (b) The content in hexadecimal. (b) The content in hexadecimal. 02 D1 000B 02D1 000B 02D1 000B 000C (c) The content in a machine (b) The content in(c) hexadecimal. The contentlanguage in a machine listing. language listing. Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 000B 02D1 (c) The content in a machine language listing. Computer Systems F I F T H E D I T I O N Figure 4.6 FIGURE 4 . 6 The Pep/9 instruction set at Level ISA3. Instruction Specif er Instruction 0000 0000 Stop execution 0000 0001 Return from CALL 0000 0010 Return from trap 0000 0011 Move SP to A 0000 0100 Move NZVC f ags to A〈12..15〉 0000 0101 Move A〈12..15〉 to NZVC f ags 0000 011r Bitwise invert r 0000 100r Negate r 0000 101r Arithmetic shift left r 0000 110r Arithmetic shift right r 0000 111r Rotate left r 0001 000r Rotate right r 0001 001a Branch unconditional 0001 010a Branch if less than or equal to 0001 011a Branch if less than 0001 100a Branch if equal to 0001 101a Branch if not equal Copyrightto © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 0001 110a Branch if greater than or equal to 0001 111a Branch if greater than 0010 000a Branch if V 0010 001a Branch if C 0010 010a Call subroutine 0010 011n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Unimplemented opcode, nonunary trap 0101 0aaa Add to stack pointer (SP) 0101 1aaa Subtract from stack pointer (SP) 0110 raaa Add to r 0111 raaa Subtract from r 1000 raaa Bitwise AND to r 1001 raaa Bitwise OR to r 1010 raaa Compare word to r 1011 raaa Compare byte to r〈8..15〉 1100 raaa Load word r from memory 1101 raaa Load byte r〈8..15〉 from memory 1110 raaa Store word r to memory 1111 raaa Store byte r〈8..15〉 to memory 190 9781284079630_CH04_183_230.indd 190 29/01/16 8:05 pm FIGURE 4 . 6 The Pep/9 instruction set at Level ISA3. Instruction Specif er Instruction 0000 0000 Stop execution 0000 0001 Return from CALL 0000 0010 Return from trap 0000 0011 Move SP to A 0000 0100 Move NZVC f ags to A〈12..15〉 0000 0101 Move A〈12..15〉 to NZVC f ags 0000 011r Bitwise invert r 0000 100r Negate r 0000 101r Arithmetic shift left r 0000 110r Arithmetic shift right r Figure 4.6 Computer0000 111r Systems RotateF I F T Hleft E r D I T I O N 0001 000r Rotate right r (continued) 0001 001a Branch unconditional 0001 010a Branch if less than or equal to 0001 011a Branch if less than 0001 100a Branch if equal to 0001 101a Branch if not equal to 0001 110a Branch if greater than or equal to 0001 111a Branch if greater than 0010 000a Branch if V 0010 001a Branch if C 0010 010a Call subroutine 0010 011n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Unimplemented opcode, nonunary trap 0101 0aaa Add to stack pointer (SP) 0101 1aaa Subtract from stack pointer (SP) Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 0110 raaa Add to r 0111 raaa Subtract from r 1000 raaa Bitwise AND to r 1001 raaa Bitwise OR to r 1010 raaa Compare word to r 1011 raaa Compare byte to r〈8..15〉 1100 raaa Load word r from memory 1101 raaa Load byte r〈8..15〉 from memory 1110 raaa Store word r to memory 1111 raaa Store byte r〈8..15〉 to memory 190 9781284079630_CH04_183_230.indd 190 29/01/16 8:05 pm FIGURE 4 . 6 The Pep/9 instruction set at Level ISA3. Instruction Specif er Instruction 0000 0000 Stop execution 0000 0001 Return from CALL 0000 0010 Return from trap 0000 0011 Move SP to A 0000 0100 Move NZVC f ags to A〈12..15〉 0000 0101 Move A〈12..15〉 to NZVC f ags 0000 011r Bitwise invert r 0000 100r Negate r 0000 101r Arithmetic shift left r 0000 110r Arithmetic shift right r 0000 111r Rotate left r 0001 000r Rotate right r 0001 001a Branch unconditional 0001 010a Branch if less than or equal to 0001 011a Branch if less than 0001 100a Branch if equal to 0001 101a Branch if not equal to 0001 110a Branch if greater than or equal to 0001 111a Branch if greater than 0010 000a Branch if V 0010 001a Branch if C 0010 010a Call subroutine 0010 011n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunaryFigure trap 4.6 UnimplementedF I F T H E D I T I O opcode, N nonunary trap Computer0011 1aaa Systems (continued) 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Unimplemented opcode, nonunary trap 0101 0aaa Add to stack pointer (SP) 0101 1aaa Subtract from stack pointer (SP) 0110 raaa Add to r 0111 raaa Subtract from r 1000 raaa Bitwise AND to r 1001 raaa Bitwise OR to r 1010 raaa Compare word to r 1011 raaa Compare byte to r〈8..15〉 1100 raaa Load word r from memory 1101 raaa Load byte r〈8..15〉 from memory 1110 raaa Store word r to memory 1111 raaa Store byte r〈8..15〉 to memory 190 Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 9781284079630_CH04_183_230.indd 190 29/01/16 8:05 pm Computer Systems F I F T H E D I T I O N Figure 4.7 Instruction specifier Operand specifier (a) The two parts of a nonunary instruction Instruction specifier (b) A unary instruction Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Figure 4.7 4.1 Hardware 191 Instruction FIGURE 4 . 7 specifier The Pep/9 instruction format. Operand specifier (a) The two parts of a nonunary instruction. Instruction specifier (b) A unary instruction. E x a m p l e 4 . 1 Figure 4.6 shows that the “branch if equal to” instruction has an instruction specif er of 0001 100a. Because the letter a can be zero or one, there are really two versions of the instruction—0001 1000 and 0001 1001. Similarly, there are eight versions of the decimal output trap instruction. Its instruction specif er is 0011 1aaa, where aaa can be any combination from 000 to 111. ❚ FIGURE 4.8 s u m m a r i z e s t h e m e a n i n g o f t h e p o s s i b l e f elds in the instruction specif er for the letters a and r. Generally, the letter a stands for addressing mode, and the letter r stands for register. When r is 0, the instruction operates on the accumulator.
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