Load Byte Accumulator

Chapter 4

Computer Architecture Computer Systems F I F T H E D I T I O N

Pep/9 virtual machine

Computer Systems F I F T H E D I T I O N Figure 4.1

Main memory FIGURE 4 . 1 Block diagram of the Central processing Pep/9 computer. Disk unit Input Output

System bus Data flow Control

Central Processing Unit (CPU) T e CPU contains six specialized memory locations called registers. As shown in FIGURE 4.2 , they are

❯ T e 4-bit status register (NZVC) ❯ T e 16-bit accumulator (A) ❯ T e 16-bit index register (X) ❯ T e 16-bit program counter (PC) ❯ T e 16-bit stack pointer (SP) ❯ T e 24-bit instruction register (IR)

Central processing unit (CPU) FIGURE 4 . 2 The CPU of the Pep/9 N Z V C computer. Status bits (NZVC)

Accumulator (A)

Index register (X)

Program counter (PC)

Stack pointer (SP)

Instruction register (IR)

9781284079630_CH04_Pass03.indd 185 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N Figure 4.2

Central processing unit (CPU)

.:6# Status bits (.:6#)

Accumulator ( ! )

Index register ( 8 )

Program counter (0#)

Stack pointer (30)

Instruction register ()2)

Main memory

0000 0001 0002

0003

0004 0005 0006 . . .

FFFE FFFF

Main memory 0000 0003 0004 0007 000A 000B 000D ......

Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 000B 000B Computer Systems F I F T H 1E D I1 T I O0 N 1 0 0 0 Figure1 4.5 1 1 0 1 0 0 0 1 000C 000C 0 0 0 0 0 0 1 0 (a) The content in binary. (a) The content in binary. 000B

1 1 0 1 0 0 0 1 02 D1 02 D1 000C 000B 000C 000B 000C (a) The content in binary. (b) The content in hexadecimal. (b) The content in hexadecimal.

02 D1 000B 02D1 000B 02D1 000B 000C (c) The content in a machine (b) The content in(c) hexadecimal. The contentlanguage in a machine listing. language listing.

000B 02D1

(c) The content in a machine language listing. Computer Systems F I F T H E D I T I O N Figure 4.6 FIGURE 4 . 6 The Pep/9 instruction set at Level ISA3.

Instruction Specif er Instruction 0000 0000 Stop execution 0000 0001 Return from CALL 0000 0010 Return from trap 0000 0011 Move SP to A 0000 0100 Move NZVC f ags to A〈12..15〉 0000 0101 Move A〈12..15〉 to NZVC f ags

0000 011r Bitwise invert r 0000 100r Negate r 0000 101r Arithmetic shift left r 0000 110r Arithmetic shift right r 0000 111r Rotate left r 0001 000r Rotate right r

0001 001a Branch unconditional 0001 010a Branch if less than or equal to 0001 011a Branch if less than 0001 100a Branch if equal to 0001 101a Branch if not equal Copyrightto © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 0001 110a Branch if greater than or equal to 0001 111a Branch if greater than 0010 000a Branch if V 0010 001a Branch if C 0010 010a Call subroutine

0010 011n Unimplemented opcode, unary trap

0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Unimplemented opcode, nonunary trap

0101 0aaa Add to stack pointer (SP) 0101 1aaa Subtract from stack pointer (SP)

0110 raaa Add to r 0111 raaa Subtract from r 1000 raaa Bitwise AND to r 1001 raaa Bitwise OR to r

1010 raaa Compare word to r 1011 raaa Compare byte to r〈8..15〉 1100 raaa Load word r from memory 1101 raaa Load byte r〈8..15〉 from memory 1110 raaa Store word r to memory 1111 raaa Store byte r〈8..15〉 to memory

190

9781284079630_CH04_183_230.indd 190 29/01/16 8:05 pm FIGURE 4 . 6 The Pep/9 instruction set at Level ISA3.

0000 011r Bitwise invert r 0000 100r Negate r 0000 101r Arithmetic shift left r 0000 110r Arithmetic shift right r Figure 4.6 Computer0000 111r Systems RotateF I F T Hleft E r D I T I O N 0001 000r Rotate right r (continued)

0001 001a Branch unconditional 0001 010a Branch if less than or equal to 0001 011a Branch if less than 0001 100a Branch if equal to 0001 101a Branch if not equal to 0001 110a Branch if greater than or equal to 0001 111a Branch if greater than 0010 000a Branch if V 0010 001a Branch if C 0010 010a Call subroutine

0010 011n Unimplemented opcode, unary trap

0101 0aaa Add to stack pointer (SP) 0101 1aaa Subtract from stack pointer (SP) Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 0110 raaa Add to r 0111 raaa Subtract from r 1000 raaa Bitwise AND to r 1001 raaa Bitwise OR to r

190

9781284079630_CH04_183_230.indd 190 29/01/16 8:05 pm FIGURE 4 . 6 The Pep/9 instruction set at Level ISA3.

0000 011r Bitwise invert r 0000 100r Negate r 0000 101r Arithmetic shift left r 0000 110r Arithmetic shift right r 0000 111r Rotate left r 0001 000r Rotate right r

0010 011n Unimplemented opcode, unary trap

0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunaryFigure trap 4.6 UnimplementedF I F T H E D I T I O opcode, N nonunary trap Computer0011 1aaa Systems (continued) 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Unimplemented opcode, nonunary trap

0101 0aaa Add to stack pointer (SP) 0101 1aaa Subtract from stack pointer (SP)

0110 raaa Add to r 0111 raaa Subtract from r 1000 raaa Bitwise AND to r 1001 raaa Bitwise OR to r

190

9781284079630_CH04_183_230.indd 190 29/01/16 8:05 pm Computer Systems F I F T H E D I T I O N Figure 4.7

Instruction specifier

Operand specifier

(a) The two parts of a nonunary instruction

Instruction specifier

(b) A unary instruction

Figure 4.7 4.1 Hardware 191

Instruction FIGURE 4 . 7 specifier The Pep/9 instruction format. Operand specifier

(a) The two parts of a nonunary instruction.

Instruction specifier

(b) A unary instruction.

E x a m p l e 4 . 1 Figure 4.6 shows that the “branch if equal to” instruction has an instruction specif er of 0001 100a. Because the letter a can be zero or one, there are really two versions of the instruction—0001 1000 and 0001 1001. Similarly, there are eight versions of the decimal output trap instruction. Its instruction specif er is 0011 1aaa, where aaa can be any combination from 000 to 111. ❚

FIGURE 4.8 s u m m a r i z e s t h e m e a n i n g o f t h e p o s s i b l e f elds in the instruction specif er for the letters a and r. Generally, the letter a stands for addressing mode, and the letter r stands for register. When r is 0, the instruction operates on the accumulator. When r is 1, the instruction operates on the index register. Pep/9 executes each nonunary instruction in one of eight addressing modes—immediate, direct, indirect, stack-relative, stack-relative

Computer Systems FIGURE 4 . 8 F I F T H E D I T I O N Figure 4.8 The Pep/9 instruction speciﬁ er ﬁ elds.

aaa Addressing Mode a Addressing Mode r Register

000 Immediate 0 Immediate 0 Accumulator, A

001 Direct 1 Indexed 1 Index register, X

010 Indirect (b) The addressing-a ﬁ eld. (c) The register-r ﬁ eld.

011 Stack-relative

100 Stack-relative deferred

101 Indexed

110 Stack-indexed

111 Stack-deferred indexed

(a) The addressing-aaa ﬁ eld.

9781284079630_CH04_183_230.indd 191 29/01/16 8:05 pm 4.1 Hardware 191

Instruction FIGURE 4 . 7 specifier The Pep/9 instruction format. Operand specifier

(a) The two parts of a nonunary instruction.

Instruction specifier

(b) A unary instruction.

FIGURE 4.8 s u m m a r i z e s t h e m e a n i n g o f t h e p o s s i b l e f elds in the instruction specif er for the letters a and r. Generally, the letter a stands for addressing mode, and the letter r stands for register. When r is 0, the instruction operates on the accumulator. When r is 1, the instruction operates Figure 4.8 F I F T H E D I T I O N on the index register. Pep/9 executesComputer each nonunary instruction Systems in one of eight (continued) addressing modes—immediate, direct, indirect, stack-relative, stack-relative

FIGURE 4 . 8 The Pep/9 instruction speciﬁ er ﬁ elds. aaa Addressing Mode a Addressing Mode r Register

000 Immediate 0 Immediate 0 Accumulator, A

001 Direct 1 Indexed 1 Index register, X

010 Indirect (b) The addressing-a ﬁ eld. (c) The register-r ﬁ eld.

011 Stack-relative

100 Stack-relative deferred

101 Indexed

110 Stack-indexed

(a) The addressing-aaa ﬁ eld.

9781284079630_CH04_183_230.indd 191 29/01/16 8:05 pm 192 CHAPTER 4 Computer Architecture

deferred, indexed, stack-indexed, or stack-deferred indexed. Later chapters describe the meaning of the addressing modes. For now, it is important only that you know how to use the tables of Figures 4.7 and 4.8 to determine which register and addressing mode a given instruction uses. T e meaning of the letter n in the unary trap instruction is described in a later chapter.

Example 4.2 Determine the opcode, register, and addressing mode of the 1100 1011 instruction. Starting from the lef , determine with the help of Figure 4.6 that the opcode is 1100. T e next bit af er the opcode is the r bit, which is 1, indicating the index register. T e three bits af er the r bit are the aaa bits, which are 011, indicating stack-relative addressing. T erefore, the instruction loads a word from memory into the index register using stack- relative addressing. ❚

T e operand specif er, for those instructions that are not unary, indicates the operand to be processed by the instruction. T e CPU can interpret the operand specif er several dif erent ways, depending on the bits in the instruction specif er. For example, it may interpret the operand specif er as an ASCII character, as an integer in two’s complement representation, or as an address in main memory where the operand is stored. Instructions are stored in main memory. T e address of an instruction in main memory is the address of the f rst byte of the instruction.

Example 4.3 FIGURE 4.9 shows two adjacent instructions stored in main memory at locations 01A3 and 01A6. T e instruction at 01A6 is unary; the instruction at 01A3 is not. In this example, the instruction at 01A3 has Opcode: 0111 Register-r f eld: 1 Addressing-aaa f eld: 101 Operand specif er: 0000 0011 0100 1110

Computer Systems F I F T H E D I T I O N Figure 4.9

FIGURE 4 . 9 Two instructions in main memory.

Main memory

0 1 1 1 1 1 0 1 00000011 01001110 01A3 01A4 01A5

0 0 0 0 1 1 0 0 01A6

Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 9781284079630_CH04_Pass03.indd 192 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N Direct addressing • Oprnd = Mem[OprndSpec] • The operand speciﬁer is the memory address of the operand.

Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Computer Systems F I F T H E D I T I O N The stop instruction • Instruction speciﬁer: 0000 0000 • Causes the computer to stop

Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Computer Systems F I F T H E D I T I O N The load word instruction • Instruction speciﬁer: 1100 raaa • Loads one word (two bytes) from memory to register r

r Oprnd ; N r < 0 , Z r = 0

FIGURE 4 . 10 The load word instruction.

Instruction specifier Operand specifier Opcode r aaa 11000001 00000000 01001010 C 1 0 0 4 A

Example 4.4 Suppose the instruction to be executed is C1004A in hexadecimal, which FIGURE 4.10 shows in binary. T e register-r f eld in this example is 0, which indicates a load word to the accumulator instead of the index register. T e addressing-aaa f eld is 001, which indicates direct addressing. FIGURE 4.11 shows the ef ect of executing the load word instruction, assuming Mem[004A] has an initial content of 92EF. T e load word instruction does not change the content of the memory location. It sends a copy of the two memory cells (at addresses 004A and 004B) to the register. Whatever was in the register before the instruction was executed, in this case 036D, is destroyed. T e N bit is set to 1 because the bit pattern loaded has 1 in the sign bit. T e Z bit is set to 0 because the bit pattern is not all 0’s. T e V and C bits are unaf ected by the load word instruction. Figure 4.11 shows the data f ow lines and control lines that the load word instruction activates. As indicated by the solid lines,4.2 Direct data fAddressing ows from 195 the main memory on the bus to the CPU, and then into the register. For this data transfer to take place, the CPU must send a control signal (as indicated by the dashed lines) to main memory, telling it to put the data on the bus. FIGURE T e 4 . CPU 10 Computer also tells main Systemsmemory the addressF I F T Hfrom E D I Twhich I O N to fetch Figure 4.10, 4.11 The load word instruction. the data. ❚ Instruction specifier Operand specifier Opcode r aaa 11000001 00000000 01001010 FIGURE 4 . 11 C1 00 4A Execution of the load word instruction.

Example 4.4 SupposeCPU the instructionMem to be executed is C1004ACPU in Mem hexadecimal, which FIGURE 4.10 shows in binary. T e register-r f eld in NZ 92EF C1004A NZ 10 92EF this example is 0, which indicates 004Aa load wordLoad to theaccumulator accumulator instead 004A of the index register.A T 036D e addressing-aaa f eld is 001, which indicatesA direct 92EF addressing. FIGURE 4.11 shows the ef ect of executing the load word instruction, assuming Mem[004A] has an initial content of 92EF. T e load word instruction does(a) not Before. change the content of the memory location.(b) It After.sends a copy of the two memory cells (at addresses 004A and 004B) to the register. Whatever was in the register before the instruction was executed, in this case 036D, is destroyed. T e N bit is set to 1 because the bit pattern loaded Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company has 1 in the sign bit. T e Z bit is set to 0 because the bit pattern is not all 0’s. T e V and C bits are unaf ected by the load word instruction. Figure 4.11 shows the data f ow lines and control lines that the load 9781284079630_CH04_183_230.inddword instruction 195 activates. As indicated by the solid lines, data f ows from 29/01/16 8:05 pm the main memory on the bus to the CPU, and then into the register. For this data transfer to take place, the CPU must send a control signal (as indicated by the dashed lines) to main memory, telling it to put the data on the bus. T e CPU also tells main memory the address from which to fetch the data. ❚

FIGURE 4. 11 Execution of the load word instruction.

CPU Mem CPU Mem

NZ 92EF C1004A NZ 10 92EF 004A Load accumulator 004A A 036D A 92EF

(a) Before. (b) After.

9781284079630_CH04_Pass03.indd 195 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N The store word instruction • Instruction speciﬁer: 1110 raaa • Stores one word (two bytes) from register r to memory

Oprnd r

The Store Word Instruction 196 CHAPTER 4 Computer Architecture T e store word instruction has instruction specif er 1110 raaa. T is instruction stores one word (two bytes) from either the accumulator or the index register to a memory location. With direct addressing, the operand Thespeci fStore es the memoryWord Instruction location in which the information is stored. T e RTL Tspeci e f store cation word for the instruction store instruction has instruction is specif er 1110 raaa. T is instructionOprnd ← stores r one word (two bytes) from either the accumulator or the index register to a memory location. With direct addressing, the operand speci Examplef es the 4.5 memory Suppose location the instructionin which the to information be executed is stored. is E9004A T e RTL in specihexadecimal,f cation for which the store FIGURE instruction 4.12 shows is in binary. T is time, the register-r f eldOprnd indicates ← r that the instruction will af ect the index register. T e addressing-aaa f eld, 001, indicates direct addressing. Example FIGURE 4.5 4.13 Suppose shows the the instruction ef ect of executing to be executed the store is E9004Ainstruction, in hexadecimal,assuming the which index FIGURE register 4.12 has shows an initial in binary. content T is of time, 16BC. the Tregister-r e store finstruction eld indicates does that not change the instruction the content will of the af ectregister. the It index sends register. a copy of T the e addressing-aaaregister to two fmemory eld, 001, cells indicates (at addresses direct addressing. 004A and 004B). Whatever was in theFIGURE memory 4.13 cells shows before thethe instruction ef ect of executing was executed, the in store this case instruction, F082, is assumingdestroyed. theT e indexstore instruction register has af ects an initialnone of content the status of bits. 16BC. T e store❚ instruction does not change the content of the register. It sends a copy of the register to two memory cells (at addresses 004A and 004B). Whatever was in the memory cells before the instruction was executed, in this case F082, is FIGURE 4 .12 destroyed. T e store instruction af ects none of the status bits. ❚ The store word instruction.

Instruction specifier Operand specifier Opcode r aaa FIGURE 4 . 12 11101001 00000000 01001010 Computer Systems F I F T H E D I T I O N Figure 4.12, 4.13 The store word instruction.E 9 0 0 4 A

Instruction specifier Operand specifier Opcode r aaa 11101001 00000000 01001010 FIGURE 4 .13 E900 4A Execution of the store word instruction.

CPU Mem CPU Mem

X 16BC F082 X 16BC 16BC FIGURE 4 . 13 E9004A 004A Store index register 004A Execution of the store word instruction.

CPU Mem CPU Mem

X 16BC F082 E9004A X 16BC 16BC (a) Before. (b) After. 004A Store index register 004A

9781284079630_CH04_183_230.indd 196 29/01/16 8:05 pm

9781284079630_CH04_Pass03.indd 196 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N The add instruction • Instruction speciﬁer: 0110 raaa • Adds one word (two bytes) from memory to register r

r r + Oprnd ; N r < 0 , Z r = 0 ,

V overﬂow , C carry { } { }

The Add Instruction 4.2 Direct Addressing 197 T e add instruction has instruction specif er 0110 raaa. It is similar to the load word instruction in that data is transferred from main memory to Theregister Add r in Instruction the CPU. But with the add instruction, the original content of the register is not just written over by the content of the word from main Tmemory. e add instruction Instead, the has content instruction of the speciwordf fromer 0110 main raaa. memory It is similar is added to theto loadthe content word instruction of the register. in that T e data sum isis transferredplaced in the from register, main and memory all four to registerstatus bits r in are the set CPU. accordingly. But with As the with add the instruction, load word the instruction, original content a copy ofof thethe registermemory is word not justis sent written to the over CPU. by Tthe e originalcontent contentof the word of the from memory main memory.word is unchanged. Instead, the T content e RTL speci of thef cation word offrom the addmain instruction memory isis added to the content of the register. T e sum is placed in the register, and all four statusr ← bits r + areOprnd set ;accordingly. N ← r < 0 , Z As ← with r = 0 the , V ←load {over wordf ow instruction, } , C ← { carry }a copy of the memory word is sent to the CPU. T e original content of the memory Example 4.6 word is unchanged. Suppose T e RTL the speci instructionf cation of to the be add executed instruction is 69004A is in hexadecimal, which FIGURE 4.14 shows in binary. T e register-r f eld indicatesr ← r + that Oprnd; the Ninstruction ← r < 0, Z will ← r a=f ect0, V the ← {index overf owregister. }, C ← T{ carry e addressing-} aaa f eld, 001, indicates direct addressing. Example FIGURE 4.6 4.15 Suppose shows the the instruction ef ect of executing to be executed the add is instruction, 69004A in hexadecimal,assuming the index which register FIGURE has 4.14 an initial shows content in binary. of 0005 T eand register-r Mem[004A] f eld indicates that the instruction will af ect the index register. T e addressing- aaa f eld, 001, indicates direct addressing. FIGURE 4.15 shows the ef ect of executing the add instruction, FIGURE 4 . 14 assuming the index register has an initial content of 0005 and Mem[004A] The add instruction.

Instruction specifier Operand specifier Opcode r aaa FIGURE 4 . 14 Computer01101001 Systems00000000F I F T H E D I T I O N 01001010Figure 4.14, 4.15 The add instruction.6 9 0 0 4 A

Instruction specifier Operand specifier Opcode r aaa 01101001 00000000 01001010 FIGURE 4 . 15 6900 4A Execution of the add instruction.

CPU Mem CPU Mem

FIGURE 4 . 15 NZVC FFF9 69004A NZVC 1000 FFF9 004A Add index register 004A Execution of the addX instruction. 0005 X FFFE

CPU Mem CPU Mem

NZVC FFF9 69004A NZVC 1000 FFF9 004A Add index register 004A (a) Before.X 0005 (b) XAfter.FFFE

9781284079630_CH04_183_230.indd 197 29/01/16 8:05 pm

9781284079630_CH04_Pass03.indd 197 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N The subtract instruction • Instruction speciﬁer: 0111 raaa • Subtracts one word (two bytes) from memory from register r

r r Oprnd ; N r < 0 , Z r = 0 , V overﬂow , C carry { } { }

has –7 (dec) = FFF9 (hex). In decimal, the sum 5 + (–7) is –2, which is 198 CHAPTERshown as FFFE 4 Computer (hex) in Architecture Figure 4.15 (b). T e f gure shows the NZVC bits in binary. T e N bit is 1 because the sum is negative. T e Z bit is 0 because the sum is not all 0’s. T e V bit is 0 because an overf ow did not occur, and the hasC bit –7 is (dec)0 because = FFF9 a carry (hex). did Innot decimal, occur out the of sum the most5 + (–7)signi isf cant –2, bit.which is❚ shown as FFFE (hex) in Figure 4.15 (b). T e f gure shows the NZVC bits in binary. The Subtract T e N bit isInstruction 1 because the sum is negative. T e Z bit is 0 because the sum is not all 0’s. T e V bit is 0 because an overf ow did not occur, and the T e subtract instruction has instruction specif er 0111 raaa. It is similar to C bit is 0 because a carry did not occur out of the most signif cant bit. ❚ the add instruction, except that the operand is subtracted from the register. TheT e resultSubtract is placed Instruction in the register, and the operand is unchanged. With subtraction, the C bit represents a carry from adding the negation of the Toperand. e subtract T e instruction RTL specif hascation instruction of the subtract specif instructioner 0111 raaa. is It is similar to the add instruction, except that the operand is subtracted from the register. ← − ← < ← = ← ← T er result r Oprnd is placed ; N in r the 0 register, , Z r and 0 , V the operand{ overf ow } is, C unchanged. {carry } With subtraction, the C bit represents a carry from adding the negation of the Example 4.7 operand. T e RTL Suppose specif cation the instruction of the subtract to beinstruction executed is is 71004A in hexadecimal, which FIGURE 4.16 shows in binary. T e register-r f eld indicatesr ← r − that Oprnd; the instructionN ← r < 0, Z will ← ra =f ect 0, V the ← accumulator.{ overf ow }, C ← {carry } FIGURE 4.17 shows the ef ect of executing the subtract instruction, Exampleassuming 4.7the accumulator Suppose the has instruction an initial content to be of executed 0003 and is Mem[004A] 71004A in hexadecimal,has 0009. In decimal, which theFIGURE dif 4.16erence shows 3 – 9 inis –6, binary. which T is e shown register-r as FFFAf eld indicates(hex) in Figure that the 4.17(b). instruction T e f willgure a showsf ect the the accumulator. NZVC bits in binary. T e N bit FIGURE 4.17 s h o w s t h e e f ect of executing the subtract instruction, assuming the accumulator has an initial content of 0003 and Mem[004A] FIGURE 4 . 16 has 0009. In decimal, the dif erence 3 – 9 is –6, which is shown as FFFA The subtract instruction. (hex) in Figure 4.17(b). T e f gure shows the NZVC bits in binary. T e N bit Instruction specifier Operand specifier Opcode r aaa Computer Systems F I F T H E D I T I O N Figure 4.16, 4.17 FIGURE 4 .16 01110001 00000000 01001010 The subtract instruction.7 1 0 0 4 A Instruction specifier Operand specifier Opcode r aaa FIGURE 4 . 17 01110001 00000000 01001010 Execution of the subtract71 instruction. 00 4A

CPU Mem CPU Mem

FIGURE 4 .17 NZVC 0009 71004A NZVC 1000 0009 Execution of the subtract instruction.004A Subtract accumulator 004A A 0003 A FFFA CPU Mem CPU Mem

NZVC 0009 71004A NZVC 1000 0009 004A Subtract accumulator 004A A 0003 AFFFA (a) Before. (b) After.

(a) Before. (b)Copyright Af ©ter. 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company

9781284079630_CH04_183_230.indd 198 29/01/16 8:05 pm

9781284079630_CH04_Pass03.indd 198 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N The and instruction • Instruction speciﬁer: 1000 raaa • ANDs one word (two bytes) from memory to register r

r r Oprnd ; N r < 0 , Z r = 0 ^

is 1 because the sum is negative. T e Z bit is 0 because the sum is not all 0’s. T e V bit is 0 because an overf ow did not occur, and the C bit is 0 because a carry did not occur when –9 was added to 3. ❚ The And and Or Instructions T e and instruction has instruction specif er 1000 raaa, and the or instruction has instruction specif er 1001 raaa. Both instructions are similar to the add instruction. Rather than add the operand to the register, each instruction performs a logical operation on the register. T e and operation is useful for masking out undesired 1 bits from a bit pattern. T e or operation is useful for inserting 1 bits into a bit pattern. Both instructions af ect the N and Z bits and leave the V and C bits unchanged. T e RTL specif cations for the and and or instructions are r ← r ⋀ Oprnd; N ← r < 0, Z ← r = 0 r ← r ⋁ Oprnd; N ← r < 0, Z ← r = 0

Example 4.8 Suppose the instruction to be executed is 89004A in hexadecimal, which FIGURE 4.18 shows in binary. T e opcode indicates that the and instruction will execute and the register-r f eld indicates that the instruction will af ect the index register. FIGURE 4.19 s h o w s t h e e f ect of executing the and instruction, assuming the index register has an initial content of 5DC3 and Mem[004A] has 00FF. In binary, 00FF is 0000 0000 1111 1111. At every position where there is a 1 in Mem[004A], the corresponding bit in the index register is unchanged. At every position where there is a 0, the corresponding bit is cleared to 0. T e f gure shows the NZ bits in binary. T e N bit is 0 because the quantity in the index register is not negative when interpreted as a signed integer. T e Z bit is 0 because the index register is not all 0’s. ❚

Example 4.9 FIGURE 4.20 shows the operation of the or instruction. T e initial state is identical to that of Example 4.8, except that the opcode of the instruction specif er 99 is 1001, which indicates the or instruction. T is time, at every position where there is a 0 in Mem[004A], the corresponding

FIGURE 4 . 18 Computer Systems F I F T H E D I T I O N Figure 4.18, 4.19 200 CHAPTER 4 Computer Architecture The and instruction.

Instruction specifier Operand specifier Opcode r aaa 10001001 00000000 01001010 FIGURE 4 . 19 89 00 4A Execution of the and instruction.

CPU Mem CPU Mem

NZ 00FF 89004A NZ 00 00FF 004A And index register 004A X 5DC3 X 00C3 9781284079630_CH04_Pass03.indd 199 19/01/16 5:56 pm

(a) Before. (b) After.

FIGURE 4 . 20 Execution of the or instruction.

CPU Mem CPU Mem

NZ 00FF 99004A NZ 00 00FF 004A Or index register 004A X 5DC3 X 5DFF

(a) Before. (b) After.

bit in the index register is unchanged. At every position where there is a 1, the corresponding bit is set to 1. T e N bit is 0 because the index register would not be negative if it were interpreted as a signed integer. ❚ The Invert and Negate Instructions T e invert instruction has instruction specif er 0000 011r, and the negate instruction has instruction specif er 0000 100r. Both instructions are unary. T ey have no operand specif er. T e invert instruction performs the NOT operation on the register. T at is, each 1 is changed to 0, and each 0 is changed to 1. It af ects the N and Z bits. T e RTL specif cation of the invert instruction is

r ← ¬r ; N ← r < 0 , Z ← r = 0

9781284079630_CH04_183_230.indd 200 29/01/16 8:05 pm Computer Systems F I F T H E D I T I O N The or instruction • Instruction speciﬁer: 1001 raaa • ORs one word (two bytes) from memory to register r

r r Oprnd ; N r < 0 , Z r = 0 _

FIGURE 4 . 19 Execution of the and instruction.

CPU Mem CPU Mem

NZ 00FF 89004A NZ 00 00FF 004A And index register 004A X 5DC3 X 00C3

(a) Before. (b) After. Computer Systems F I F T H E D I T I O N Figure 4.20

FIGURE 4 . 20 Execution of the or instruction.

CPU Mem CPU Mem

NZ 00FF 99004A NZ 00 00FF 004A Or index register 004A X 5DC3 X 5DFF

(a) Before. (b) After.

bit in the index register is unchanged.Copyright © 2017 by AtJones &every Bartlett Learning, position LLC an Ascend Learning where Company there is a 1, the corresponding bit is set to 1. T e N bit is 0 because the index register would not be negative if it were interpreted as a signed integer. ❚ The Invert and Negate Instructions T e invert instruction has instruction specif er 0000 011r, and the negate instruction has instruction specif er 0000 100r. Both instructions are unary. T ey have no operand specif er. T e invert instruction performs the NOT operation on the register. T at is, each 1 is changed to 0, and each 0 is changed to 1. It af ects the N and Z bits. T e RTL specif cation of the invert instruction is

r ← ¬r ; N ← r < 0 , Z ← r = 0

9781284079630_CH04_183_230.indd 200 29/01/16 8:05 pm Computer Systems F I F T H E D I T I O N The invert instruction • Instruction speciﬁer: 0000 011r • Bit-wise NOT operation on register r • Each 0 changed to 1, each 1 changed to 0

r r;N r < 0 , Z r = 0 ¬

T e negate instruction interprets the register as a signed integer and FIGURE 4 . 21 negates it. T e 16-bit register stores signed integers in the range –32768 The invert instruction. to 32767. T e negate instruction af ects the N, Z, and V bits. T e V bit is Instruction specifier set only if the original value in the register is –32768, because there is no Opcode r corresponding positive value of 32768. T e RTL specif cation of the negate 00000110 instruction is 0 6

r ← −r ; N ← r < 0 , Z ← r = 0 , V ← {over f ow }

Example 4.10 Suppose the instruction to be executed is 06 in hexadecimal, which FIGURE 4.21 shows in binary. T e opcode indicates that the invert instruction will execute, and the register-r f eld indicates that the instruction will af ect the accumulator. FIGURE 4.22 shows the ef ect of executing the invert instruction, assuming the accumulator has an initial content of 0003 (hex), which is 0000 0000 0000 0011 (bin). T e not instruction changes the bit pattern to 1111 1111 1111 1100. T e N bit is 1 because the quantity in the accumulator is negative when interpreted as a signed integer. T e Z bit is 0 because the 4.2accumulator Direct Addressing is not all 0’s. 201 ❚

Example 4.11 FIGURE 4.23 shows the operation of the negate instruction. F I F T H E D I T I O N Figure 4.21, 4.22 T e negate instruction interprets the register as a signedT e initialComputer integer state and is identical Systems FIGUREto that 4of . 21 Example 4.10, except that the opcode The invert instruction. negates it. T e 16-bit register stores signed integers inof the the range instruction –32768 specif er 1A is 0000 100, which indicates the negate to 32767. T e negate instruction af ects the N, Z, and Vinstruction. bits. T e V T bit e isnegation of Instruction3 is –3, whichspecifier is 1111 1111 1111 1101 (bin) = set only if the original value in the register is –32768, becauseFFFD (hex). there is no Opcode r ❚ corresponding positive value of 32768. T e RTL specif cation of the negate 00000110 instruction is 06

← − ← < ← = ← r r; N r 0, Z r 0, V { overf ow} CPU CPU FIGURE 4 . 22 Execution of the invert NZ 10NZ Example 4.10 Suppose the instruction to be executed is 06 in hexadecimal, 06 instruction. Invert accumulator which FIGURE 4.21 shows in binary. T e opcode indicates that the invertA 0003 A FFFC instruction will execute, and the register-r f eld indicates that the instruction will af ect the accumulator. (a) Before. (b) After. FIGURE 4.22 shows the ef ect of executing the invert instruction, assuming the accumulator has an initial content of 0003 (hex), which is 0000 0000 0000 0011 (bin). T e not instruction changes the bit pattern to 1111

Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 1111 1111 1100. T e N bit is 1 because the quantity in the accumulatorCPU is CPU FIGURE 4 . 23 negative when interpreted as a signed integer. T e Z bit is 0 because the Execution of the negate NZ NZ 10 accumulator is not all 0’s. ❚ 08 instruction. Negate accumulator A 0003 A FFFD Example 4.11 FIGURE 4.23 shows the operation of the negate instruction. T e initial state is identical to that of Example 4.10, except that the opcode(a) Before. (b) After. of the instruction specif er 1A is 0000 100, which indicates the negate instruction. T e negation of 3 is –3, which is 1111 1111 1111 1101 (bin) = FFFD (hex). ❚

CPU CPU FIGURE 4 . 22 9781284079630_CH04_183_230.indd 201 29/01/16 8:05 pm Execution of the invert NZ NZ 10 06 instruction. Invert accumulator A 0003 A FFFC

(a) Before. (b) After.

CPU CPU FIGURE 4 . 23 Execution of the negate NZ NZ 10 08 instruction. Negate accumulator A 0003 A FFFD

(a) Before. (b) After.

9781284079630_CH04_Pass03.indd 201 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N The negate instruction • Instruction speciﬁer: 0000 100r • Negate (take two’s complement of) register r

r r;N r < 0 , Z r = 0

r ← −r ; N ← r < 0 , Z ← r = 0 , V ← {over f ow }

Example 4.11 FIGURE 4.23 shows the operation of the negate instruction. T e initial state is identical to that of Example 4.10, except that the opcode of the instruction specif er 1A is 0000 100, which indicates the negate instruction. T e negation of 3 is –3, which is 1111 1111 1111 1101 (bin) = FFFD (hex). ❚

CPU CPU FIGURE 4 . 22 Execution of the invert NZ 10NZ 06 instruction. Invert accumulator A 0003 A FFFC Computer Systems F I F T H E D I T I O N Figure 4.23 (a) Before. (b) After.

CPU CPU FIGURE 4 . 23 Execution of the negate NZ NZ 10 08 instruction. Negate accumulator A 0003 A FFFD

(a) Before. (b) After.

9781284079630_CH04_183_230.indd 201 29/01/16 8:05 pm Pep/9 RTL speciﬁcation of the instruction set

Instruction Register transfer language specification STOP Stop execution RET PC Mem[SP] ; SP SP + 2 ← ← RETTR NZVC Mem[SP] 4..7 ; A Mem[SP + 1] ; X Mem[SP + 3] ; PC Mem[SP + 5] ; SP Mem[SP + 7] ← ⟨ ⟩ ← ← ← ← MOVSPA A SP ← MOVFLGA A 8..11 0 , A 12..15 NZVC ⟨ ⟩← ⟨ ⟩← MOVAFLG NZVC A 12..15 ← ⟨ ⟩ NOTr r r ; N r < 0 , Z r = 0 ← ¬ ← ← NEGr r r ; N r < 0 , Z r = 0 , V overflow ←− ← ← ← { } ASLr C r 0 , r 0..14 r 1..15 , r 15 0 ; N r < 0 , Z r = 0 , V overflow ← ⟨ ⟩ ⟨ ⟩← ⟨ ⟩ ⟨ ⟩← ← ← ← { } ASRr C r 15 , r 1..15 r 0..14 ; N r < 0 , Z r = 0 ← ⟨ ⟩ ⟨ ⟩← ⟨ ⟩ ← ← ROLr C r 0 , r 0..14 r 1..15 , r 15 C ← ⟨ ⟩ ⟨ ⟩← ⟨ ⟩ ⟨ ⟩← RORr C r 15 , r 1..15 r 0..14 , r 0 C ← ⟨ ⟩ ⟨ ⟩← ⟨ ⟩ ⟨ ⟩← BR PC Oprnd ← BRLE N = 1 Z = 1 PC Oprnd ∨ ⇒ ← BRLT N = 1 PC Oprnd ⇒ ← BREQ Z = 1 PC Oprnd ⇒ ← BRNE Z = 0 PC Oprnd ⇒ ← BRGE N = 0 PC Oprnd ⇒ ← BRGT N = 0 Z = 0 PC Oprnd ∧ ⇒ ← BRV V = 1 PC Oprnd ⇒ ← BRC C = 1 PC Oprnd ⇒ ← CALL SP SP 2;Mem[SP] PC ; PC Oprnd ← − ← ← NOPn Trap: Unary no operation NOP Trap: Nonunary no operation

DECI Trap: Oprnd decimal input ← { } DECO Trap: decimal output Oprnd { } ← HEXO Trap: hexadecimal output Oprnd { } ← STRO Trap: string output Oprnd { } ← ADDSP SP SP + Oprnd ← SUBSP SP SP Oprnd F I F T H E D I T I O N Computer← − Systems ADDr r r + Oprnd ; N r < 0 , Z r = 0 , V overflow , C carry ← The← load byte← ← { } ← { } SUBr r r Oprnd ; N r < 0 , Z r = 0 , V overflow , C carry ← − ← ← ← { } ← { } ANDr r r Oprnd ; N r < 0 , Z r = 0 ← ∧ instruction← ← ORr r r Oprnd ; N r < 0 , Z r = 0 ←• ∨Instruction specifier:← 1101← raaa CPWr T rLoadsOprnd one; byteN fromT < memory0 , Z toT =the0 right, V overflow , C carry ; N N V ←• − ← ← ← { } ← { } ← ⊕ CPBr T rhalf8.. 15of registerbyte rOprnd ; N T < 0 , Z T = 0 , V 0 , C 0 ← ⟨ ⟩− ← ← ← ← LDWr r Oprnd ; N r < 0 , Z r = 0 ← ← ← LDBr r 8..15 byte Oprnd ; N 0 , Z r 8..15 = 0 ⟨ ⟩← ← ← ⟨ ⟩ STWr Oprnd r ← STBr byte Oprnd r 8..15 ← ⟨ ⟩ Trap T Mem[FFF6] ; Mem[T 1] IR 0..7 ; Mem[T 3] SP ; Mem[T 5] PC ; Mem[T 7] X ; ← − ←Copyright © 2017 ⟨by Jones & Bartlett⟩ Learning, LLC an Ascend Learning Company− ← − ← − ← Mem[T 9] A ; Mem[T 10] 4..7 NZVC ; SP T 10 ; PC Mem[FFFE] − ← − ⟨ ⟩← ← − ←

2 202 CHAPTER 4 Computer Architecture

The Load Byte and Store Byte Instructions 202 CHAPTER T ese instructions, 4 Computer along Architecture with the two that follow, are byte instructions. Byte instructions operate on a single byte of information instead of a word. T e load byte instruction has instruction specif er 1101 raaa, and the store byte Theinstruction Load hasByte instruction and Store speci Bytef er 1111 Instructions raaa. T e load byte instruction Tloads ese theinstructions, operand intoalong the with right the half two of that either follow, the are accumulator byte instructions. or the index Byte instructionsregister, and operateaf ects theon aN single and Zbyte bits. of Itinformation leaves the leinsteadf half of of a the word. register T e loadunchanged. byte instruction T e store has byte instruction instruction speci storesf er 1101 the raaa, right and half the of store either byte the instructionaccumulator has or the instruction index register speci finto er 1111 a one-byte raaa. Tmemory e load location byte instruction and does loadsnot af theect operandany status into bits. the T right e RTL half speci off eithercation the of theaccumulator load byte instructionor the index is register, r 〈8..15 and〉 ← byteaf ects Oprnd the ;N N and← 0 ,Z Z bits.← r〈 8..15It leaves〉 = 0 the lef half of the register unchanged. T e store byte instruction stores the right half of either the accumulator and the RTL orspeci thef indexcation register of the store into abyte one-byte instruction memory is location and does not af ect any status bits. T e RTL specif cation of the load byte instruction is byte Operand ← r〈8..15〉 r 〈8..15〉 ← byte Oprnd; N ← 0, Z ← r〈8..15〉 = 0 Example 4.12 Suppose the instruction to be executed is D1004A in and the RTL specif cation of the store byte instruction is hexadecimal, which FIGURE 4.24 shows in binary. T e register-r f eld in this examplebyte Operand is 0, which ← r〈 8..15indicates〉 a load to the accumulator instead of the index register. T e addressing-aaa f eld is 001, which indicates direct addressing. Example FIGURE 4.12 4.25 Suppose shows the the e instructionf ect of executing to be the executed load byte is D1004A instruction, in hexadecimal,assuming Mem[004A] which FIGURE has an 4.24 initial shows content in binary. of 92. T T e e register-r N bit is always f eld in set this to example is 0, which indicates a load to the accumulator instead of the index register. T e addressing-aaa f eld is 001, which indicates direct addressing. FIGURE 4 . 24 FIGURE 4.25 shows the ef ect of executing the load byte instruction, The load byte instruction. assuming Mem[004A] has an initial content of 92. T e N bit is always set to Instruction specifier Operand specifier Opcode r aaa F I F T H E D I T I O N Figure 4.24, 4.25 FIGURE 4 . 24 Computer11010001 Systems00000000 01001010 The load byte instruction.D 1 0 0 4 A

Instruction specifier Operand specifier Opcode r aaa 11010001 00000000 01001010 FIGURE 4 . 25 D1 00 4A Execution of the load byte instruction.

CPU Mem CPU Mem

FIGURE 4 . 25 NZ 92 D1004A NZ 00 92 Execution of the load byte instruction.004A Load bytbyte 004A A 036D accumulator A 0392 CPU Mem CPU Mem

NZ 92 D1004A NZ 00 92 004A Load byte 004A A 036D A 0392 (a) Before. accumulator (b) After.

9781284079630_CH04_183_230.indd 202 29/01/16 8:05 pm

9781284079630_CH04_Pass03.indd 202 19/01/16 5:56 pm Computer Systems F I F T H E D I T I O N The store byte instruction • Instruction speciﬁer: 1111 raaa • Stores one byte from the right half of register r to memory

byte Oprnd r 8..15 h i

FIGURE 4 . 26 Execution of the store byte instruction.

CPU Mem CPU Mem F1004A A 036D 92 Store byte A 036D 6D 004A accumulator 004A

(a) Before. (b) After.

0 with this instruction. T e Z bit is set to 0 because the eight bits loaded into the right half of the accumulator are not all 0’s. ❚

Example 4.13 FIGURE 4.26 shows the ef ect of executing the store byte instruction. T e initial state is the same as in Example 4.12, except that the instruction is store byte instead of load byte. T e right half of the accumulatorCopyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company is 6D, which is sent to the memory cell at address 004A. ❚ The Input and Output Devices T e input device is at address FC15, and is attached to an ASCII character input device like a keyboard. You get a character from the input device by executing the load byte instruction from address FC15. T e output device is at address FC16 and is attached to an ASCII output device like a screen. You send a character to the output device by executing the store byte instruction to address FC16.

Example 4.14 Suppose the instruction to be executed is D1FC15 in hexadecimal, which is the load byte instruction from the input device with direct addressing. FIGURE 4.27 shows the ef ect of executing the instruction, assuming that the next character in the input stream is W. T e character from the input stream can come from the keyboard or from a f le. T e f gure shows the keyboard wired into the memory location at address FC15. T e user has pressed the W key. T e ASCII value of the letter W is 57 (hex), which is sent to the accumulator. T e dashed lines from the CPU to main memory represent control signals that instruct the memory subsystem to put the byte from address FC15 onto the system bus. T e memory subsystem has a special input circuit that detects when a memory load request is made from address FC15. It then performs all the necessary steps to put the next character from the input stream into Mem[FC15], which is then put on the system bus. T is is an example of levels of abstraction in a computer system. T e details of how the

9781284079630_CH04_183_230.indd 203 29/01/16 8:05 pm 204 CHAPTER 4 Computer Architecture

Computer Systems F I F T H E D I T I O N Figure 4.27

FIGURE 4 . 27 Load The byte load byte instruction from from the inputinput device. device Mem Mem CPU Keyboard CPU Keyboard 204 CHAPTER 4 Computer Architecture 57 QWE D1FC15 57 QWE A 0000 Load byte A 0057 FC15 FC15 accumulator

FIGURE 4. 27 The load byte instruction from the input device. (a) Before. (b) After. Mem Mem CPU Keyboard CPU Keyboard character is transferred from the keyboard to Mem[FC15] are hidden from 57 QWE D1FC15 57 QWE A 0000 Load byte A 0057 the Level ISA3 programmer, who only needs to know that to get the next FC15 FC15 accumulator ASCII character from the input stream you load a byte from that address. ❚

Example 4.15 Suppose the instruction to be executed is F1FC16 in (a) Before. (b) After. hexadecimal, which is the store byte instruction to the output device with FIGURE 4.28 direct addressing.Copyright © 2017 by Jones & Bartlett Learning, LLC anshows Ascend Learning the Company ef ect of executing the instruction, assuming that 69 (hex), which is the ASCII value for the letter i, is in the character is transferred from the keyboard to Mem[FC15] are hiddenright halffrom of the accumulator. T e f gure shows the screen wired into the the Level ISA3 programmer, who only needs to know that to getmemory the next location at address FC16. T e ASCII value of the letter i is sent to ❚ ASCII character from the input stream you load a byte from that address.Mem[FC16]. As with the input device, the memory subsystem has a special circuit that detects when a byte is stored to Mem[FC16] and routes it to the Example 4.15 Suppose the instruction to be executed is F1FC16output stream in to be displayed on the screen. ❚ hexadecimal, which is the store byte instruction to the output device with direct addressing. FIGURE 4.28 shows the ef ect of executing the instruction, Big Endian Versus Little Endian assuming that 69 (hex), which is the ASCII value for the letter i, is in the T ere are two CPU design philosophies regarding the transfer of information right half of the accumulator. T e f gure shows the screen wired into the between the registers of the CPU and the bytes in main memory. T e memory location at address FC16. T e ASCII value of the letter i is sent to problem arises because main memory is always byte-addressable and a Mem[FC16]. As with the input device, the memory subsystem has a special circuit that detects when a byte is stored to Mem[FC16] and routes it to the ❚ output stream to be displayed on theFIGURE screen. 4 . 28 The store byte instruction to the output device. Big Endian Versus Little Endian Mem Screen Mem Screen T ere are two CPU design philosophiesCPU regarding the transfer of information CPU between the registers of the CPU and the bytes in48 main memory.H T e F1FC16 69 Hi A 0069 Store byte A 0069 problem arises because main memory is always FC16 byte-addressable and a FC16 accumulator

FIGURE 4. 28 The store byte instruction to the output device. (a) Before. (b) After.

Mem Screen Mem Screen CPU CPU 48 H F1FC16 69 Hi A 0069 Store byte A 0069 FC16 FC16 accumulator 9781284079630_CH04_183_230.indd 204 29/01/16 8:05 pm

(a) Before. (b) After.

9781284079630_CH04_183_230.indd 204 29/01/16 8:05 pm 204 CHAPTER 4 Computer Architecture

FIGURE 4. 27 The load byte instruction from the input device.

Mem Mem CPU Keyboard CPU Keyboard 57 QWE D1FC15 57 QWE 204 CHAPTER 4 Computer ArchitectureA 0000 Load byte A 0057 FC15 FC15 accumulator

FIGURE 4 . 27 (a) Before. (b) After. The load byte instruction from the input device.

Mem Mem CPU Keyboard CPU Keyboardcharacter is transferred from the keyboard to Mem[FC15] are hidden from 57 QWE D1FC15 57 QWEthe Level ISA3 programmer, who only needs to know that to get the next A 0000 Load byte A 0057 ASCII character from the input stream you load a byte from that address. ❚ FC15 FC15 accumulator Example 4.15 Suppose the instruction to be executed is F1FC16 in hexadecimal, which is the store byte instruction to the output device with (a) Before. (b) After. direct addressing. FIGURE 4.28 shows the ef ect of executing the instruction, assuming that 69 (hex), which is the ASCII value for the letter i, is in the right half of the accumulator. T e f gure shows the screen wired into the character is transferred from the keyboard to Mem[FC15] are hidden from the Level ISA3 programmer, who only needs to know that to memoryget the next location at address FC16. T e ASCII value of the letter i is sent to ASCII character from the input stream you load a byte from thatMem[FC16]. address. ❚ As with the input device, the memory subsystem has a special circuit that detects when a byte is stored to Mem[FC16] and routes it to the ❚ Example 4.15 Suppose the instruction to be executed is output F1FC16 stream in to be displayed on the screen. hexadecimal, which is the store byte instruction to the output device with Big Endian Versus Little Endian direct addressing. FIGURE 4.28 shows the ef ect of executing the instruction, assuming that 69 (hex), which is the ASCII value for the letter T i, ere is arein thetwo CPU design philosophies regarding the transfer of information right half of the accumulator. T e f gure shows the screen wiredbetween into the the registers of the CPU and the bytes in main memory. T e memory locationComputer at address FC16. Systems T e ASCII value ofF the I F Tletter H problemE Di isI T sent I O N arisesto because mainFigure memory 4.28 is always byte-addressable and a Mem[FC16]. As with the input device, the memory subsystem has a special circuit that detects when a byte is stored to Mem[FC16] and routes it to the output stream to be displayed onFIGURE the screen. 4. 28 ❚ Store The byte store byte instruction to to outputthe output device. device

Big Endian Versus Little Endian Mem Screen Mem Screen CPU CPU T ere are two CPU design philosophies regarding the transfer of information 48 H F1FC16 69 Hi between the registers of the CPUA and0069 the bytes in main memory. T e Store byte A 0069 FC16 FC16 problem arises because main memory is always byte-addressable and a accumulator

FIGURE 4 . 28 The store byte instruction to the output device. (a) Before. (b) After.

Mem Screen Mem Screen CPU CPU 48 H F1FC16 69 Hi A 0069 Store byte A 0069 FC16 FC16 accumulator 9781284079630_CH04_Pass03.indd 204 19/01/16 5:56 pm

(a) Before. (b) After.

9781284079630_CH04_183_230.indd 204 29/01/16 8:05 pm 4.2 Direct Addressing 205

register in a CPU typically contains more than one byte. T e design question is, in what order should the sequence of bytes be stored in main memory? T ere are two choices. T e CPU can store the most signif cant byte at the lowest address, called big-endian order, or it can store the least signif cant byte at the lowest address, called little-endian order. T e choice of which order to use is arbitrary as long as the same order is used consistently for all instructions in the instruction set. T ere is no dominant standard in the computing industry. Some processors use big-endian order, some use little-endian order, and some can use either order depending on a switch that is set by low-level sof ware. Pep/9 is a big-endian CPU. Figure 4.13 shows the ef ect of the store instruction. T e most signif cant byte in the register is 16, which is stored at the lowest address, 004A. T e next byte in the register is BC and is stored at the next higher address, 004B. Figure 4.11 shows the load instruction, which is consistent. T e most signif cant byte of the register gets 92, which is the byte from the lowest address at 004A. T e next byte gets EF from the next higher address at 004B. I n c o n t r a s t , FIGURE 4.29 shows what happens when a load instruction executes in a little-endian CPU. T e byte at the lowest address, 004A, is 92 and is put in the least signif cant byte of the register. T e byte from the next higher address, 004B, is put to the lef of the low-order byte in the register. FIGURE 4.30 shows the ef ect of a load instruction in a CPU with 32-bit registers for both big-endian and little-endian ordering. A 32-bit register holds four bytes, which are loaded into the accumulator from most signif cant to least signif cant byte, or from least signif cant to most signif cant byte, depending on whether the CPU uses big-endian or little-endian ordering, respectively. T e word endian comes from Jonathan Swif ’s 1726 novel Gulliver’s Travels, in which two competing kingdoms, Lilliput and Blefuscu, have dif erent customsComputer for breaking eggs. Systems T e inhabitants Fof I F Lilliput T H E D Ibreak T I O N their eggs Figure 4.29 at the little end, and hence are known as little endians, while the inhabitants of

FIGURE 4 .29 A little-endian CPU The load instruction in a little-endian CPU.

CPU Mem CPU Mem

NZ 92EF Little-endian CPU NZ 10 92EF 004A Load accumulator 004A A 036D A EF92

(a) Before. (b) After.

Computer Systems F I F T H E D I T I O N Figure 4.30

FIGURE 4 . 30 The loadA instruction 32-bit with a 32-bit register register. load

Big Endian Little Endian Initial State Final State Final State

Mem[019E] 89 89 89

Mem[019F] AB AB AB

Mem[01A0] CD CD CD

Mem[01A1] EF EF EF

Accumulator 89 AB CD EF EF CD AB 89

Blefuscu break their eggs at the big end, and hence are known as big endians. T e novel is a parody ref ecting the absurdity of Copyrightwar © 2017over by Jones meaningless & Bartlett Learning, LLC an Ascend Learningissues. Company T e terminology is f tting, as whether a CPU is big-endian or little-endian is of little fundamental importance.

4.3 von Neumann Machines In the earliest electronic computers, each program was hand-wired. To change the program, the wires had to be manually reconnected, a tedious and time-consuming process. T e Electronic Numerical Integrator and Calculator (ENIAC) computer described in Section 3.1 was an example of this kind of machine. Its memory was used only to store data. In 1945, John von Neumann had proposed in a report published by the University of Pennsylvania that the United States Ordnance Department build a computer that would store in main memory not only the data, but the program as well. T e stored-program concept was a radical idea at the time. Maurice V. Wilkes built the Electronic Delay Storage Automatic Calculator (EDSAC) at Cambridge University in England in 1949. It was the f rst computer to be built that used von Neumann’s stored-program idea. Practically all commercial computers today are based on the stored-program concept, with programs and data sharing the same main memory. Such computers are called von Neumann machines, although some believe that J. Presper Eckert, Jr., originated the idea several years before von Neumann’s paper. The von Neumann Execution Cycle T e Pep/9 computer is a classic von Neumann machine. FIGURE 4.31 is a pseudocode description of the steps required to execute a program:

9781284079630_CH04_183_230.indd 206 29/01/16 8:05 pm Computer Systems F I F T H E D I T I O N The von Neumann execution cycle • Fetch instruction at Mem[PC]. • Decode instruction fetched. • Increment PC. • Execute the instruction fetched. • Repeat.

Load the machine language program Initialize PC and SP do { Fetch the next instruction Decode the instruction speciﬁer Increment PC Execute the instruction fetched } while (the stop instruction does not execute)

Load the machine language program into memory starting at address 0000 PC ← 0000 SP ← Mem[FFF4] do { Fetch the instruction specifier at address in PC PC ← PC + 1 Decode the instruction specifier if (the instruction is not unary) { Fetch the operand specifier at address in PC PC ← PC + 2 } Execute the instruction fetched } while ((the stop instruction does not execute) && (the instruction is legal))

Address! Machine Language (bin) 0000 1101 0001 0000 0000 0000 1101 0003 1111 0001 1111 1100 0001 0110 0006 1101 0001 0000 0000 0000 1110 0009 1111 0001 1111 1100 0001 0110 000C 0000 0000 000D 0100 1000 0110 1001 000F

Address! Machine Language (hex) 0000 D1000D ;Load byte accumulator 'H' 0003 F1FC16 ;Store byte accumulator output device 0006 D1000E ;Load byte accumulator 'i' 0009 F1FC16 ;Store byte accumulator output device 000C 00 ;Stop 000D 4869 ;ASCII "Hi" characters

Output Hi

FIGURE 4 . 34 The von Neumann execution cycle for the program of Figure 4.33.

Mem Mem 0000 0000 D1000D 0003 0003 F1FC16 CPU CPU 0006 0006 D1000E 0009 0009 F1FC16 A A 000C 000C 00 PC 000D Screen PC 000D 4869 Screen ...... IR IR FC16 FC16

(a) Initial state before loading. (b) Program loaded into main memory.

Mem Mem

0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU CPU 0006 D1000E 0006 D1000E 0009 F1FC16 0009 F1FC16 A A 000C 00 000C 00

Mem Mem 0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU 0006 D1000E CPU 0006 D1000E 0009 F1FC16 0009 F1FC16 0048 A 000C 00 A 000C 00 PC 0003 000D 4869 Screen PC 0003 000D 4869 Screen ...... IR D1000D IR D1000D FC16 FC16

(e) Increment PC. (f ) Execute. Load byte for H to accumulator. (continues )

9781284079630_CH04_183_230.indd 211 29/01/16 8:05 pm 4.3 von Neumann Machines 211

FIGURE 4. 34 The von Neumann execution cycle for the program of Figure 4.33.

Mem Mem 0000 0000 D1000D 0003 0003 F1FC16 CPU CPU 0006 0006 D1000E 0009 0009 F1FC16 A A 000C 000C 00 PC 000D Screen PC 000D 4869 Screen ...... Figure 4.34 IR F I F T H IRE D I T I O N ComputerFC16 Systems FC16 (continued)

(a) Initial state before loading. (b) Program loaded into main memory.

Mem Mem

0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU CPU 0006 D1000E 0006 D1000E 0009 F1FC16 0009 F1FC16 A A 000C 00 000C 00 PC 0000 000D 4869 Screen PC 0000 000D 4869 Screen ...... IR IR D1000D FC16 FC16

Mem Mem 0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU 0006 D1000E CPU 0006 D1000E 0009 F1FC16 0009 F1FC16 0048 A 000C 00 A 000C 00

(e) Increment PC. (f ) Execute. Load byte for H to accumulator. (continues )

9781284079630_CH04_183_230.indd 211 29/01/16 8:05 pm 4.3 von Neumann Machines 211

FIGURE 4 . 34 The von Neumann execution cycle for the program of Figure 4.33.

Mem Mem 0000 0000 D1000D 0003 0003 F1FC16 CPU CPU 0006 0006 D1000E 0009 0009 F1FC16 A A 000C 000C 00 PC 000D Screen PC 000D 4869 Screen ...... IR IR FC16 FC16

(a) Initial state before loading. (b) Program loaded into main memory.

Mem Mem

0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU CPU 0006 D1000E 0006 D1000E 0009 F1FC16 0009 F1FC16 A A 000C 00 000C 00 PC 0000 000D 4869 Screen PC 0000 000D 4869 Screen ...... D1000D Figure 4.34 IR F I F T H IRE D I T I O N ComputerFC16 Systems FC16 (continued)

(e) Increment PC. (f ) Execute. Load byte for H to accumulator. (continues )

9781284079630_CH04_183_230.indd 211 29/01/16 8:05 pm

FIGURE 4.34 The von Neumann execution cycle for the program of Figure 4.33. (continued )

Mem Mem

0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU CPU 0006 D1000E 0006 D1000E 0009 F1FC16 0009 F1FC16 A 0048 0048 000C 00 A 000C 00 PC 0003 000D 4869 Screen PC 0006 000D 4869 Screen ...... IR F1FC16 IR F1FC16 FC16 FC16

(g) Fetch instruction at Mem[PC]. (h) Increment PC.

Mem Mem 0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU 0006 D1000E CPU 0006 D1000E 0009 F1FC16 0009 F1FC16 A 0048 A 0048 000C 00 Copyright © 2017 by000C Jones & Bartlett00 Learning, LLC an Ascend Learning Company PC 0006 000D 4869 Screen PC 0006 000D 4869 Screen ...... IR F1FC16 IR D1000E FC16 48 H FC16 48 H

(i) Execute. Store byte from accumulator to output device. (j) Fetch instruction at Mem[PC].

Mem Mem

0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU 0006 D1000E CPU 0006 D1000E 0009 F1FC16 0009 F1FC16 0048 0069 A 000C 00 A 000C 00 PC 0009 000D 4869 Screen PC 0009 000D 4869 Screen ...... D1000E D1000E IR H IR FC16 48 FC16 48 H

(k) Increment PC. (l) Execute. Load byte for i to accumulator.

9781284079630_CH04_183_230.indd 212 29/01/16 8:05 pm 212 CHAPTER 4 Computer Architecture

FIGURE 4.34 The von Neumann execution cycle for the program of Figure 4.33. (continued )

Mem Mem

(g) Fetch instruction at Mem[PC]. (h) Increment PC.

Mem Mem 0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU 0006 D1000E CPU 0006 D1000E 0009 F1FC16 0009 F1FC16 0048 0048 A 000C 00 A 000C 00 PC 0006 000D 4869 Screen PC 0006 000D 4869 Screen ...... IR F1FC16 IR D1000E FC16 48 H FC16 48 H

(i) Execute. Store byte from accumulator to output device. (j) Fetch instruction at Mem[PC].

Mem Mem 0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU CPU 0006 D1000E 0006 D1000E 0009 F1FC16 0009 F1FC16 A 0048 A 0069 000C 00 Copyright © 2017 000Cby Jones & Bartlett00 Learning, LLC an Ascend Learning Company PC 0009 000D 4869 Screen PC 0009 000D 4869 Screen ...... D1000E D1000E IR H IR FC16 48 FC16 48 H

(k) Increment PC. (l) Execute. Load byte for i to accumulator.

9781284079630_CH04_183_230.indd 212 29/01/16 8:05 pm 212 CHAPTER 4 Computer Architecture

FIGURE 4.34 The von Neumann execution cycle for the program of Figure 4.33. (continued )

Mem Mem

0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU CPU 0006 D1000E 0006 D1000E 0009 F1FC16 0009 F1FC16 A 0048 A 0048 000C 00 000C 00 PC 0003 000D 4869 Screen PC 0006 000D 4869 Screen ...... IR F1FC16 IR F1FC16 FC16 FC16

(g) Fetch instruction at Mem[PC]. (h) Increment PC.

Mem Mem 0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU CPU 0006 D1000E 0006 D1000E 0009 F1FC16 0009 F1FC16 A 0048 A 0048 000C 00 000C 00 PC 0006 000D 4869 Screen PC 0006 000D 4869 Screen ...... IR F1FC16 IR D1000E FC16 48 H FC16 48Figure 4.34H Computer Systems F I F T H E D I T I O N (continued)

(i) Execute. Store byte from accumulator to output device. (j) Fetch instruction at Mem[PC].

Mem Mem 0000 D1000D 0000 D1000D 0003 F1FC16 0003 F1FC16 CPU 0006 D1000E CPU 0006 D1000E 0009 F1FC16 0009 F1FC16 0048 0069 A 000C 00 A 000C 00 PC 0009 000D 4869 Screen PC 0009 000D 4869 Screen ...... D1000E D1000E IR H IR FC16 48 FC16 48 H

(k) Increment PC. (l) Execute. Load byte for i to accumulator.

9781284079630_CH04_183_230.indd 212 29/01/16 8:05 pm

Address! Machine Language (bin) 0000 1101 0001 1111 1100 0001 0101 0003 1111 0001 0000 0000 0001 0011 0006 1101 0001 1111 1100 0001 0101 0009 1111 0001 1111 1100 0001 0110 000C 1101 0001 0000 0000 0001 0011 000F 1111 0001 1111 1100 0001 0110 0012 0000 0000

Address! Machine Language (hex) 0000 D1FC15 ;Input first character 0003 F10013 ;Store first character 0006 D1FC15 ;Input second character 0009 F1FC16 ;Output second character 000C D10013 ;Load first character 000F F1FC16 ;Output first character 0012 00 ;Stop

Input up

Output pu

Address! Machine Language (bin) 0000 1100 0001 0000 0000 0000 1101 0003 0110 0001 0000 0000 0000 1111 0006 1001 0001 0000 0000 0001 0001 0009 1111 0001 1111 1100 0001 0110 000C 0000 0000 000D 0000 0000 0000 0101 000F 0000 0000 0000 0011 0011 0000 0000 0011 0000

Address! Machine Language (hex) 0000 C1000D ;A <- first number 0003 61000F ;Add the two numbers 0006 910011 ;Convert sum to character 0009 F1FC16 ;Output the character 000C 00 ;Stop 000D 0005 ;Decimal 5 000F 0003 ;Decimal 3 0011 0030 ;Mask for ASCII char

Output 8

Address! Machine Language (bin) 0000 1101 0001 0000 0000 0001 1001 0003 1111 0001 0000 0000 0000 1001 0006 1100 0001 0000 0000 0001 0011 0009 0110 0001 0000 0000 0001 0101 000C 1001 0001 0000 0000 0001 0111 000F 1111 0001 1111 1100 0001 0110 0012 0000 0000 0013 0000 0000 0000 0101 0015 0000 0000 0000 0011 0017 0000 0000 0011 0000 0019 0111 0001

Address! Machine Language (hex) 0000 D10019 ;Load byte accumulator 0003 F10009 ;Store byte accumulator 0006 C10013 ;A <- first number 0009 610015 ;Add the two numbers 000C 910017 ;Convert sum to character 000F F1FC16 ;Output the character 0012 00 ;Stop 0013 0005 ;Decimal 5 0015 0003 ;Decimal 3 0017 0030 ;Mask for ASCII char 0019 71 ;Byte to modify instruction

Output 2

Intel x-86 computer architecture

Of course, this is not a very practical program. If you wanted to subtract the two numbers, you would simply write the program of Figure 4.36 with the subtract instruction in place of the add instruction. But it does show that in a von Neumann machine, main memory places no signif cance on the bits it is storing. It simply remembers 1’s and 0’s and has no idea which are program bits, which are data bits, which are ASCII characters, and so on. Furthermore, the CPU cranks out the von Neumann execution cycle and interprets the bits accordingly, with no idea of their history. When it fetches the bits at Mem[0009], it does not know, or care, how they got there in the f rst place. It simply repeats the fetch, decode, increment, execute cycle over and over.

The x86 Architecture

T e designation x86 refers to a family of processors example, the 64-bit processors have a 32-bit execution beginning with the 8086 introduced by Intel in 1978 mode so that older sof ware can run unchanged on the and continuing with the 80186, 80286, 80386, 80486 newer CPUs. series; the Pentium series; and the Core series. T e CPU FIGURE 4.38 shows the registers in a typical registers vary in size from 16 bits in the 8086, to 32 bits 32-bit model. T e x86 processors are little-endian and in the 80386, to 64 bits beginning with the Pentium 4. number the bits in a register starting from 0 for the T e processors are generally backward compatible. For least signif cant bit. T e EFLAGS register has a number

FIGURE 4 . 38 F I F T H E D I T I O N Figure 4.38 The registersComputer in a typical Systems32-bit x86 CPU.

... 31 012 EFLAGS

AX AH AL EAX

EBX ECX EDX ESI EDI

ESP EBP

EIP

9781284079630_CH04_183_230.indd 219 29/01/16 8:05 pm 220 CHAPTER 4 Computer Architecture

the stack pointer SP of Pep/9. EBP is the base pointer, Computer FIGURE Systems 4 . 39 F I F T H E D I T I O N Figure 4.39 which points to the bottom of the current stack frame. The x86 status bits corresponding to the Pep/9 has no corresponding register. EIP is called the Pep/9 status bits. instruction pointer in Intel terminology and corresponds to the program counter PC in Pep/9. FIGURE 4.40 Status Bit Intel Name EFLAGS Position shows a machine language instruction that adds the content of the ECX register N SF 7 to the content of the EAX register and puts the sum in the ECX register. As with all von Neumann machines, Z ZF 6 a machine language instruction begins with an opcode f eld, 000000 in this example, which is the opcode for V OF 11 the add instruction. T e following f elds correspond to C CF 0 the register-r f eld and the addressing-aaa f eld of Pep/9 but with meaning specif c to the x86 instruction set. T e 1 in the s f eld indicates that the sum is on 32-bit quantities. of status bits besides the four NZVC bits in Pep/9. If s were 0, only a single byte would be added. T e 11 FIGURE 4.39 shows the location ofCopyright the © 2017 four by Jones & Bartlett bits Learning, LLCthat an Ascend Learning Companyin the mod f eld indicates that the r/m f eld is a register. correspond to the Pep/9 status bits. SF stands for sign T e 000 in the reg f eld, along with the 0 in the d f eld, f ag, and OF stands for overf ow f ag. indicates the EAX register, and the 001 in the r/m f eld, T e x86 architecture has four general-purpose along with the 0 in the d f eld, indicates the ECX register. accumulators named EAX, EBX, ECX, and EDX that T e hexadecimal abbreviation of the instruction is 01C1. correspond to the single Pep/9 accumulator. Figure 4.38 T is is only one format from the x86 instruction shows that the rightmost two bytes of the EAX register set. T ere are multiple formats with some instruction are named AX, the lef byte of AX is named AH for specif ers preceded by special pref x bytes that change A-high, and the right byte of AX is named AL for the format of the instruction specif er, and some A-low. T e other accumulators are named accordingly. followed by operand specif ers that might include a For example, the rightmost byte of the ECX register is so-called scaled indexed byte. T e instruction format named CL. scheme is complicated because it evolved from a small T e x86 architecture has two index registers CPU with the requirement of backward compatibility. corresponding to the single X register of Pep/9. ESI is the Pep/9 illustrates the concepts underlying machine source index register, and EDI is the destination index languages in all von Neumann machines without the register. ESP is the stack pointer, which corresponds to above complexities.

FIGURE 4 . 40 The x86 instruction format for the add register instruction.

Opcode d s mod reg r/m 00 0000 10 110 000 0 1 0 1 C 1

9781284079630_CH04_183_230.indd 220 29/01/16 8:05 pm 220 CHAPTER 4 Computer Architecture

the stack pointer SP of Pep/9. EBP is the base pointer, FIGURE 4 . 39 which points to the bottom of the current stack frame. The x86 status bits corresponding to the Pep/9 has no corresponding register. EIP is called the Pep/9 status bits. instruction pointer in Intel terminology and corresponds to the program counter PC in Pep/9. FIGURE 4.40 Status Bit Intel Name EFLAGS Position shows a machine language instruction that adds the content of the ECX register N SF 7 to the content of the EAX register and puts the sum in the ECX register. As with all von Neumann machines, Z ZF 6 a machine language instruction begins with an opcode f eld, 000000 in this example, which is the opcode for V OF 11 the add instruction. T e following f elds correspond to C CF 0 the register-r f eld and the addressing-aaa f eld of Pep/9 but with meaning specif c to the x86 instruction set. T e 1 in the s f eld indicates that the sum is on 32-bit quantities. of status bits besides the four NZVC bits in Pep/9. If s were 0, only a single byte would be added. T e 11 FIGURE 4.39 shows the location of the four bits that in the mod f eld indicates that the r/m f eld is a register. correspond to the Pep/9 status bits. SF stands for sign T e 000 in the reg f eld, along with the 0 in the d f eld, f ag, and OF stands for overf ow f ag. indicates the EAX register, and the 001 in the r/m f eld, T e x86 architecture has four general-purpose along with the 0 in the d f eld, indicates the ECX register. accumulators named EAX, EBX, ECX, and EDX that T e hexadecimal abbreviation of the instruction is 01C1. correspond to the single Pep/9 accumulator. Figure 4.38 T is is only one format from the x86 instruction shows that the rightmost two bytes of the EAX register set. T ere are multiple formats with some instruction are named AX, the lef byte of AX is named AH for specif ers preceded by special pref x bytes that change A-high, and the right byte of AX is named AL for the format of the instruction specif er, and some A-low. T e other accumulators are named accordingly. followed by operand specif ers that might include a For example, the rightmost byte of the ECX register is so-called scaled indexed byte. T e instruction format named CL. scheme is complicated because it evolved from a small T e x86 architecture has two index registers CPU with the requirement of backward compatibility. corresponding to theComputer single X register Systems of Pep/9. ESI is theF I F T H Pep/9 E D I T I O illustrates N the Figure concepts 4.40 underlying machine source index register, and EDI is the destination index languages in all von Neumann machines without the register. ESP is the stackx86 pointer, add which corresponds register to above complexities.instruction

FIGURE 4 . 40 The x86 instruction format for the add register instruction.

Opcode d s mod reg r/m 00 0000 10 110 000 0 1 0 1 C 1

9781284079630_CH04_183_230.indd 220 29/01/16 8:05 pm Computer Systems F I F T H E D I T I O N Memory devices • Read/Write memory ‣ Also called Random-Access Memory (RAM) ‣ Can load from RAM and store to RAM • Read-Only memory (ROM) ‣ Can load from ROM ‣ Cannot store to ROM • RAM and ROM are both random Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 4.4 Programming at Level ISA3 221

FIGURE 4 . 41 4.4 Programming at Level ISA3 A memory map of the To program at Level ISA3 is to write a set of instructions in binary. To execute Pep/9 memory. The the binary sequence, f rst you must load it into main memory. T e operating shaded part is read-only memory. system is responsible for loading the binary sequence into main memory. An operating system is a program. Like any other program, a sof ware Mem 0000 4.4 Programmingengineer must atdesign, Level write, ISA3 test, and debug it. Most operating221 systems are Globals so large and complex that teams of engineers must write them. T e primary function of an operating system is to control the execution of application Application programs on the computer. Because the operating system is itself a program, program it must reside in main memory in order to be executed. So main memory FIGURE 4 . 41 must store not only the application programs, but also the operating system. 4.4 Programming at Level ISA3 A memory map of the In the Pep/9 computer, the bottom part of main memory—that is, the Pep/9 memory. The Heap To program at Level ISA3 is to write a set of instructionspart with in highbinary. memory To execute addresses—is reserved for the operating system. T e Application shaded part is read-only the binary sequence, f rst you must load it into maintop memory.part is reserved T e operating for the application program. FIGURE 4.41 is a memoryF I F T H E D I T I O N Figure 4.41 Computermemory. Systems system is responsible for loading the binary sequencemap ofinto the main Pep/9 memory. computer system. It shows that the operating system starts Run-time An operating system is a program. Like anyat other memory program, location a soFB8Ff ware and occupies the restMem of main memory. T at leaves stack engineer must design, write, test, and debug it. Mostmemory operating locations systems 0000 to are FB8E for the0000 applicationGlobals program. FB8F so large and complex that teams of engineers must write T e them.loader Tis that e primary part of the operating system that loads the application System function of an operating system is to control theprogram execution into ofmain application memory so it can be executed. What loads the loader? stack T e Pep/9 loader, along with several other partsApplication of the operating system, is programs on the computer. Because the operating system is itself a program, program permanently stored in main memory. it must reside in main memory in order to be executed. So main memory FC0F System must store not only the application programs, but also the operating system. Read-Only Memory globals In the Pep/9 computer, the bottom part of main memory—that is, the Heap T ere are two types of electronic-circuit elements from which memory part with high memory addresses—is reserved for the operating system. T e Application FC15 Input device devices are manufactured—read/write circuit elements and read-only top part is reserved for the application program. FIGURE 4.41 is a memory FC16 Output device circuit elements. map of the Pep/9 computer system. It shows that the operating system starts Run-time FC17 In the program of Figure 4.35 , when the store byte instruction, F10013, at memory location FB8F and occupies the rest of main memory. T at leaves stack Loader executed, the CPU transferred the content of the right half of the accumulator memory locations 0000 to FB8E for the application program. to Mem[0013]. T e original content of Mem[0013] was destroyed, and FC52 T e loader is that part of the operating system that loads the application FB8F the memory location then contained 0111 0101System (bin), the binary code for Operating system Trap program into main memory so it can be executed. What loads the loader? stack the letter u. When the load byte instruction, D10013, executed, the bits at handler T e Pep/9 loader, along with several other parts locationof the operating 0013 were system, sent back is to the accumulator so they could be sent to the permanently stored in main memory. output device. FC0F FFF4 FB8F T e circuit element at memory location 0013System is a read/write circuit. T e FFF6 FC0F Read-Only Memory store byte instruction did a write operation on it,globals which changed its content. FFF8 FC15 T e read byte instruction did a read operation on it, which sent a copy of FFFA FC16 T ere are two types of electronic-circuit elements from which memory its content to the accumulator. If theFC15 circuit elementInput device at location 0013 were FFFC FC17 devices are manufactured—read/write circuit elements and read-only a read-only circuit, the store byte instructionFC16 Output would device not have changed its FFFE FC52 circuit elements. content. FC17 Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company In the program of Figure 4.35 , when the store byte instruction, F10013, Loader executed, the CPU transferred the content of the right half of the accumulator to Mem[0013]. T e original content of Mem[0013] was destroyed, and FC52

the memory location then contained 0111 0101 (bin), the binary code for Operating system Trap the letter u. When the load byte instruction, D10013, executed, the bits at handler location 0013 were sent back to the accumulator9781284079630_CH04_183_230.indd so they could 221be sent to the 29/01/16 8:05 pm output device. FFF4 FB8F T e circuit element at memory location 0013 is a read/write circuit. T e FFF6 FC0F store byte instruction did a write operation on it, which changed its content. FFF8 FC15 T e read byte instruction did a read operation on it, which sent a copy of FFFA FC16 its content to the accumulator. If the circuit element at location 0013 were FFFC FC17 a read-only circuit, the store byte instruction would not have changed its FFFE FC52 content.

9781284079630_CH04_183_230.indd 221 29/01/16 8:05 pm Computer Systems F I F T H E D I T I O N The load option • SP ← Mem[FFF6] • PC ← Mem[FFFC] • Start the von Neumann cycle

FIGURE 4 . 42 The Pep/9 load option.

CPU Mem SP FFF6 FC0F ... 224 CHAPTER 4 Computer Architecture PC 224 CHAPTER 4 Computer Architecture FFFC FC17

F I F T H E D I T I O N Figure 4.42 Computer FIGURE 4 .Systems42 (a) Initial state. FIGURE 4 . 42 The Pep/9 load option. The Pep/9 load option. CPU CPU CPU Mem Mem Mem SP FFF6SP FC0FFC0F FFF6 FC0F SP FFF6 FC0F ...... PC ... PC PC FFFC FC17 FFFC FC17 FFFC FC17

(a) Initial state. (a) Initial state. (b) SP Mem[FFF6]

CPU CPU CPUMem Mem Mem SP FC0F FFF6 FC0F SP FC0F FFF6 FC0F SP ...FC0F FFF6 FC0F PC ...... PC FFFCPC FC17FC17 FFFC FC17 FFFC FC17

(b) SP Mem[FFF6] (b) SP Mem[FFF6] (c) PC Mem[FFFC]

CPU CPU Selecting the loadMem option initializes the stack pointer and program Mem Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company SP counterFC0F to the predeterminedFFF6 FC0F values stored at FFF6 and FFFC. It just so SP FC0F FFF6 FC0F ... PC happensFC17... that the value at address FFF6 is FC0F, the bottom of the system PC FC17 FFFC FC17 FFFC stack.FC17 FC0F is the value the stack pointer should have when the system stack is empty. It also happens that the value at address FFFC is FC17. In fact, FC17 is the address of the f rst instruction to be executed in the loader.

(c) PC T Mem[FFFC] e system programmer who wrote the operating system decided where (c) PC Mem[FFFC] the system stack and the loader should be located. Realizing that the Pep/9 computer would fetch the vectors from locations FFFA and FFFC when the load Selecting the load option initializes the stack pointer and program Selecting the load option initializes theoption stack is pointerselected, and she placed program the appropriate values in those locations. Because counter to the predetermined values stored at FFF6 and FFFC. It just so counter to the predetermined values storedthe at FFF6f rst step and in FFFC. the execution It just so cycle is fetch, the f rst instruction to be executed happens that the value at address FFF6 is FC0F, the bottom of the system happens that the value at address FFF6 is FC0F,af er selectingthe bottom the ofload the option system is the f rst instruction of the loader program. stack. FC0F is the value the stack pointer should have when the system stack stack. FC0F is the value the stack pointer should have when the system stack is empty. It also happens that the value at address FFFC is FC17. In fact, is empty. It also happens that the value at address FFFC is FC17. In fact, FC17 is the address of the f rst instruction to be executed in the loader. FC17 is the address of the f rst instruction to be executed in the loader. T e system programmer who wrote the operating system decided where T e system programmer who wrote the operating system decided where the system stack and the loader should be located. Realizing that the Pep/9 the system stack and the loader should be located. Realizing that the Pep/9 computer would fetch the vectors from locations FFFA and FFFC when the load computer9781284079630_CH04_183_230.indd would fetch the vectors 224 from locations FFFA and FFFC when the load 29/01/16 8:05 pm option is selected, she placed the appropriate values in those locations. Because option is selected, she placed the appropriate values in those locations. Because the f rst step in the execution cycle is fetch, the f rst instruction to be executed the f rst step in the execution cycle is fetch, the f rst instruction to be executed af er selecting the load option is the f rst instruction of the loader program. af er selecting the load option is the f rst instruction of the loader program.

9781284079630_CH04_Pass03.indd 224 19/01/16 5:57 pm 9781284079630_CH04_183_230.indd 224 29/01/16 8:05 pm Computer Systems F I F T H E D I T I O N The execute option • SP ← Mem[FFF4] • PC ← 0000 • Start the von Neumann cycle

Hex Version for the Loader D1 00 0D F1 FC 16 D1 00 0E F1 FC 16 00 48 69 zz

Output Hi