Advanced Source/Drain and Contact Design for Nanoscale CMOS
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Advanced Source/Drain and Contact Design for Nanoscale CMOS by Reinaldo Vega A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Chenming Hu Professor Junqiao Wu Spring 2010 Advanced Source/Drain and Contact Design for Nanoscale CMOS Copyright © 2010 by Reinaldo Vega Abstract Advanced Source/Drain and Contact Design for Nanoscale CMOS by Reinaldo Vega Doctor of Philosophy in Engineering – Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The development of nanoscale MOSFETs has given rise to increased attention paid to the role of parasitic source/drain and contact resistance as a performance-limiting factor. Dopant-segregated Schottky (DSS) source/drain MOSFETs have become popular in recent years to address this series resistance issue, since DSS source/drain regions comprise primarily of metal or metal silicide. The small source/drain extension (SDE) regions extending from the metallic contact regions are an important design parameter in DSS MOSFETs, since their size and concentration affect contact resistance, series resistance, band-to-band tunneling (BTBT), SDE tunneling, and direct source-to-drain tunneling (DSDT) leakage. This work investigates key design issues surrounding DSS MOSFETs from both a modeling and experimental perspective, including the effect of SDE design on ambipolar leakage, the effect of random dopant fluctuation (RDF) on specific contact resistivity, 3D FinFET source/drain and contact design optimization, and experimental methods to achieve tuning of the SDE region. It is found that DSS MOSFETs are appropriate for thin body high performance (HP) and low operating power (LOP) MOSFETs, but not low standby power (LSTP) MOSFETs, due to a trade-off between ambipolar leakage and contact resistance. It is also found that DSDT will not limit DSS MOSFET scalability, nor will RDF limit contact resistance scaling, at the end of the CMOS roadmap. Furthermore, it is found that SDE tunability in DSS MOSFETs is achievable in the real-world, for an implant-to- silicide (ITS) process, by employing fluorine implant prior to metal deposition and silicidation. This is found to open up the DSS process design space for the trade-off between SDE junction depth and contact resistance. Si1-xGex process technology is also explored, and Ge melt processing is found to be a promising low-cost alternative to epitaxial Si1-xGex growth for forming crystalline Si1-xGex films. Finally, a new device structure is proposed, wherein a bulk Tri-Gate MOSFET utilizes high-k trench isolation (HTI) to achieve enhanced control over short channel effects. This structure (the HTI MOSFET) is shown, through 3D TCAD modeling, to extend bulk 1 LSTP scalability to the end of the CMOS roadmap. In a direct performance comparison to FinFETs, the HTI MOSFET achieves competitive circuit delay. ____________________________________ Professor Tsu-Jae King Liu Committee Chair 2 To my teachers i Table of Contents Chapter 1: Introduction………………………………………………….…………….…1 1.1 Moore’s Law is a Byproduct…………………………………………………....1 1.2 Motivation for Alternative Device Structures…………………………………..5 1.3 Dissertation Objectives and Outline…………………………………………….7 1.4 References……………………………………………………………………….9 Chapter 2: FinFET Source/Drain Design Optimization.........................................11 2.1 Introduction……………………………………………………………………..11 2.2 LSTP Design Study……………………………………………………………..12 2.2.1 Simulation Setup………………………………………………………..13 2.2.2 Effect of NSDE on Leakage……………………………………………....16 2.2.3 Effect of LSDE on Leakage………………………………………………19 2.2.4 Effect of NSDE and LSDE on ION………………………………………….20 2.2.5 Effect of VDD on ION…………………………………………………….21 2.2.6 LSTP Performance Comparison of DSS and RSD Structures………….22 2.3 HP Design Study………………………………………………………………..23 2.3.1 Effect of Silicide Gating on DSS FinFET Performance………………..24 2.3.2 3-D Contact Optimization for RSD FinFETs…………………………..26 2.3.3 DSS vs. RSD FinFET AC Performance………………………………..28 2.3.4 Recessed Strap (RS) DSS FinFETs…………………………………….31 2.4 Summary………………………………………………………………………..35 2.5 References……………………………………………………………………....35 Chapter 3: Sub-10 nm Double Gate MOSFET Design…………………………...41 3.1 Introduction……………………………………………………………………..41 3.2 Modeling Approach…………………………………………………………….41 3.3 Effect of SDE Junction Abruptness…………………………………………….43 3.4 Effect of Schottky Barrier Height………………………………………………44 3.5 Effect of Gate Sidewall Spacers………………………………………………..46 3.6 Effect of Gate Dielectric………………………………………………………..48 3.7 Effect of Silicide Gating………………………………………………………..49 3.8 Delay Optimization…………………………………………………………….53 3.9 Summary……………………………………………………………………….57 3.10 References……………………………………………………………………...57 Chapter 4: The Effect of Random Dopant Fluctuations on Specific Contact Resistivity……………………………………………………………………..60 4.1 Introduction…………………………………………………………………….60 4.2 Modeling Approach……………………………………………………………60 ii 4.3 Analytical Model Derivation…………………………………………………....62 4.4 Modeling Results………………………………………………………………..69 4.5 Summary………………………………………………………………………...72 4.6 References…………………………………………………………………….....72 Chapter 5: High-k Trench Isolation as an Alternative to FinFETs for Ultimate Scalability……………………………………………………………………...74 5.1 Introduction……………………………………………………………………..74 5.2 Device Structure and Modeling Approach……………………………………...74 5.3 Conventional Bulk Tri-Gate vs. HTI Tri-Gate MOSFET……………………....76 5.4 FinFET vs. HTI Tri-Gate MOSFET………………………………………….…78 5.4.1 Drain Current Normalization in the HTI MOSFET………………….…80 5.4.2 Pitch-Constrained DC Design Optimization……………………....…....81 5.4.3 Pitch-Constrained AC Design Optimization…………………………....83 5.5 Summary………………………………………………………………………...86 5.6 References…………………………………………………………………….....86 Chapter 6: Implant-to-Silicide Process Technology…………………………….…88 6.1 Introduction………………………………………………………………….…..88 6.2 DSS Diode Fabrication………………………………………………….………89 6.3 DSS SDE Formation Using ITS………………………………………….……..89 6.4 Diode Capacitance-Voltage Analysis…………………………………….……..94 6.5 Diode Current-Voltage Analysis………………………………………………..98 6.6 DSS MOSFET Fabrication……………………………………………………..100 6.7 DSS MOSFET Electrical Results………………………………………………101 6.8 Summary………………………………………………………………………..105 6.9 References………………………………………………………………………105 Chapter 7: Silicon Germanium Process Technology……………...........................110 7.1 Introduction…………………………………………………………………..…110 7.2 LPCVD of In-Situ Doped N- and P-Type Si1-xGex at 425 ºC…………………..111 7.3 SPER of LPCVD Si1-xGex Films……………………………………………….118 7.4 Ge Melt Processing……………………………………………………………..121 7.5 Summary………………………………………………………………………..126 7.6 References………………………………………………………………………126 Chapter 8: Conclusions…………………………………………………………………..129 8.1 Summary………………………………………………………………………..129 8.2 Future Research Prospects……………………………………………………...130 8.3 Conclusions……………………………………………………………………..131 iii Acknowledgements Many people struggle to find their path in life. For some, they cannot figure out how best to use their gifted mind. For others, they face the torture of one self-delusion after another, always thinking they have reached happiness but never actually feeling it. Some people stumble upon their passion, while for others it is force fed. I was one of those strange individuals who is just plain-old curious, and my pursuit of answers led me to my current position in life. I have been fortunate enough to meet along the way countless wonderful individuals who, knowingly or not, have shaped my life and my ambitions. First on the list is my Ph.D. advisor, Prof. Tsu-Jae King Liu. I cannot say enough good things about her, and the praise she has endured from me and others is enough to fill a book. Few if any can match her technical prowess, and even fewer have the respect she has rightfully earned throughout her career. Her personal and professional advice will always remain with me, and her responsiveness, her professionalism, and her trust in me has been invaluable throughout my time here at UC Berkeley. I am also grateful to Prof. Chenming Hu for his generosity and for the interesting discussions we have had. He has always managed to ask interesting questions about my research and, despite his remarkable knowledge, he is always open to new ideas. I would also like to thank Prof. Junqiao Wu for serving on my qualifying exam and dissertation committees, as well as Prof. Sayeef Salahuddin for serving on my qualifying exam committee, both of whom have provided valuable feedback. I would like to thank all UC Berkeley Microlab staff for their hard work in keeping such a lively, borderline chaotic lab running smoothly. I would especially like to thank Bob Hamilton, Sia Parsa, Jimmy Chang, Danny Pestal, and Evan Stateler for their assistance with Tystar 19, GCAWS6, and Centura MXP. I would also like to thank Prof. Eugene Haller and his students – Swanee Shin and Christopher Liao – for their assistance with TEM analysis and understanding the Ge melt process. Furthermore, I would like to thank Salah Uddin, Raza Uddin, and Ning Chen, for their good company in the Microlab and many extended discussions/debates about cars and everything car-related. Not all of my processing was performed in the Microlab, and so I would like to extend my appreciation to those vendors who helped me outsource