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Designing a Single Chip Chess Grandmaster While Knowing Nothing About Chess*

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Designing a Single Chip Chess Grandmaster While Knowing Nothing About Chess* Designing a Single Chip Chess Grandmaster While Knowing Nothing About Chess* Feng-hsiung Hsu IBM T. J. Watson Research Center [email protected] (*Well, I did know close to nothing about chess...) Outline Project History Problem Descriptions Design Philosophy Chip Architecture System Performance World Chess Champion on a PC? Project History Started as a one-person student project at Carnegie Mellon ('85) First Grandmaster Level Chess Machine (Deep Thought, '88) Became an IBM Project in '89 New Chip Design in Full Swing from '92 First Release Chip in '95 ('96 Match) Second Release Chip in '97 ('97 Rematch) Problem Descriptions (Speed) FIDE Rating 3600 3400 3200 3000 Gary Kasparov Deep Blue 2800 Target Zone 2600 Deep Blue Prototype 2400 Deep Thought Hitech 2200 Belle at 8 2000 Belle at 7 1800 Belle at 6 1600 Belle at 5 1400 1200 Belle at 4 4 5 678910 11 12 13 Normalized search depth Problem Descriptions Search speed appears to be a necessary condition Speed can be obtained by increasing the level of integration (single chip chess machines) and by using massive parallelism But is speed alone enough? Problem Descriptions Speed alone might not be enough Deep Thought was a tournament GM But not a match GM Human Grandmasters, in serious matches, learn from computers' mistakes, exploit the weaknesses, and drive a truck thru the gaping holes Need to have very few weaknesses, and only weaknesses that are difficult to exploit Design Philosophy Chip speed is secondary Integration level is paramount Encapsulate every chess evaluation terms from chess books Create evaluation terms to deal with every known computer weaknesses Add hooks to handle new weaknesses, if they appear, with external FPGA hardware Put everything on one chip Deep Blue Architecture DB BOARD P2SC MEMORY I/O DB BOARD Scalable parallel system 30 node IBM RS/6000 SP supercomputer 16 chess accelerator chips per node 200 million chess positions per second average Chess Machine Basics Move Move Repetition Generator Stack Detector Move Bus (19-bit) Fast Status Eval Signals Evaluation Alphabeta Search Function Control Control Slow Signals Eval Move Systolic Eval Gen Array Pipelined (8x1) Evaluation (8x8) RAMs Pipelined Post-evaluation Logic Post-evaluation Pipelined Game Phase Search Control Endgame Control Repetition King Endgame Detector Piece and ROM Placement Pawn Tables Array Move Tables Search Stack Datapath Chip Architecture Entry e4 ... No Legal? Leaf? No e5 to Parent ... Yes Yes Early Fast Eval d4 >= in <= Exit Window? Move ... Move Evaluation Generator Generation Yes Function d Continue to Parent Slow Eval Qd4 No Has Yes Return move? Cutoff? Yes No Next Chip Architecture (Move Gen) The move generator is an extension of the move generator used in Deep Thought 8 by 8 combinatorial array, one cell per square of the chess board Intercell wiring corresponding to the way chess pieces move Can generate checking and check evasion moves Also "generalized checking" moves Chip Architecture (Eval) A fully parallel implementation of the evaluation function is too big Use a pipelined implementation Divide the evaluation into two parts Fast evaluation in one cycle, including all the big terms ''Slow'' evaluation computed in a 8-cycle sequence (+3 additional cycles), one cycle per column of the chess board Use small RAMs instead few large RAMs Fast and Slow Evaluation Fast Eval 1 cycle Slow Evaluation ... 8 + 3 cycles (if needed) Time Time when a move was made Fast Eval to slow eval Game Phase Control mat adj Endgame Draw? Logic & ROMs Endgame Adjustment to Endgame Evaluation Endgame Adjustment to search control King Logic & pawn run? Pawn Array Piece Incremental Evaluation to search control Placement Piece Placement Table Aggr+to Both colors (1024x10) To Vict+to Alphabeta White Only Mux Aggr+fr (512x10) Search Control Aggr+fr Black Only Mux Vict+to (512x10) AggrIsWhite Endgame ROM Interface KP vs K Piece Counts Address KR vs KP to Generators Endgame adder tree XORed Piece KQ vs KP Locations for each piece type KRP vs KP Main Slow Evaluation Flow PC type RAM 1 Rank 8 r to l signals RAM 2 Piece Reg & Right Transformation to Merge and Adder tree Left to Signals Rank 2 alphabeta search control RAM N-1 Rank 1 RAM N to Left to right scan alphabeta Dev RAM search control FSMs Pin RAM Adder Tree REGs Chip Statistics 3-level metal 0.6-micron 5-V CMOS 1.5 million transistors, 1 W 1.4 cm x 1.4 cm 2.5 million chess positions/sec 25 to 100 billion general purpose instructions per second A single chip system appears to play at strong Grandmaster and possibly Super Grandmaster level System Performance A 480-chip system was assembled for the 1997 Rematch with Kasparov System sustained speed was about 200 million chess positions per second, or roughly 1/5 of the potential peak speed First match win ever by a computer over World Chess Champion (3.5 to 2.5) 78 million web hits (1997 figure) 5-7 billion impressions from Rematch alone IBM stock went up the next day World Chess Champion on a PC? 0.6-micron CMOS not state of the art Design was not speed optimized 30 million chess positions/sec per chip appears possible with, say, a 0.35-micron process A small array of chips plugged into a PC could be sufficient to beat Kasparov, if a single chip is not sufficient Shogi (Japanese Chess) next?.
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