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Miniaturized Transistors Miniaturized Transistors Edited by Lado Filipovic and Tibor Grasser Printed Edition of the Special Issue Published in Micromachines www.mdpi.com/journal/micromachines Miniaturized Transistors Miniaturized Transistors Special Issue Editors Lado Filipovic Tibor Grasser MDPI Basel Beijing Wuhan Barcelona Belgrade • • • • • Special Issue Editors Lado Filipovic Tibor Grasser Institute for Microelectronics Institute for Microelectronics Austria Austria Editorial Office MDPI St. Alban-Anlage 66 4052 Basel, Switzerland This is a reprint of articles from the Special Issue published online in the open access journal Micromachines (ISSN 2072-666X) from 2018 to 2019 (available at: https://www.mdpi.com/journal/ micromachines/special issues/Miniaturized Transistors) For citation purposes, cite each article independently as indicated on the article page online and as indicated below: LastName, A.A.; LastName, B.B.; LastName, C.C. Article Title. Journal Name Year, Article Number, Page Range. ISBN 978-3-03921-010-7 (Pbk) ISBN 978-3-03921-011-4 (PDF) c 2019 by the authors. Articles in this book are Open Access and distributed under the Creative Commons Attribution (CC BY) license, which allows users to download, copy and build upon published articles, as long as the author and publisher are properly credited, which ensures maximum dissemination and a wider impact of our publications. The book as a whole is distributed by MDPI under the terms and conditions of the Creative Commons license CC BY-NC-ND. Contents About the Special Issue Editors ..................................... vii Lado Filipovic and Tibor Grasser Editorial for the Special Issue on Miniaturized Transistors Reprinted from: Micromachines 2019, 10, 300, doi:10.3390/mi10050300 ................ 1 Yanfeng Jiang, Wenjie Wang, Zirui Wang and Jian-Ping Wang Incorporation of Phosphorus Impurities in a Silicon Nanowire Transistor with a Diameter of 5nm Reprinted from: Micromachines 2019, 10, 127, doi:10.3390/mi10020127 ................ 4 Xiaoling Duan, Jincheng Zhang, Jiabo Chen, Tao Zhang, Jiaduo Zhu, Zhiyu Lin and Yue Hao High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor Reprinted from: Micromachines 2019, 10, 75, doi:10.3390/mi10010075 ................ 14 Yongbeom Cho, Jae Yoon Lee, Eunseon Yu, Jae-Hee Han, Myung-Hyun Baek, Seongjae Cho and Byung-Gook Park Design and Characterization of Semi-Floating-Gate Synaptic Transistor Reprinted from: Micromachines 2019, 10, 32, doi:10.3390/mi10010032 ................ 23 Jurgen¨ Lorenz, Eberhard B¨ar, Sylvain Barraud, Andrew R. Brown, Peter Evanschitzky, Fabian Kl upfel¨ and Liping Wang Process Variability—Technological Challenge and Design Issue for Nanoscale Devices Reprinted from: Micromachines 2019, 10, 6, doi:10.3390/mi10010006 ................. 33 Yasuhisa Omura Empirical and Theoretical Modeling of Low-Frequency Noise Behavior of Ultrathin Silicon-on-Insulator MOSFETs Aiming at Low-Voltage and Low-Energy Regime Reprinted from: Micromachines 2019, 10, 5, doi:10.3390/mi10010005 ................. 49 Pengying Chang, Xiaoyan Liu, Fei Liu and Gang Du Remote Phonon Scattering in Two-Dimensional InSe FETs with High-κ Gate Stack Reprinted from: Micromachines 2018, 9, 674, doi:10.3390/mi9120674 ................. 65 Ying Wang, Chan Shan, Wei Piao, Xing-ji Li, Jian-qun Yang, Fei Cao and Cheng-hao Yu 3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance Reprinted from: Micromachines 2018, 9, 659, doi:10.3390/mi9120659 ................. 76 Zhaonian Yang, Yuan Yang, Ningmei Yu and Juin J. Liou Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET Reprinted from: Micromachines 2018, 9, 657, doi:10.3390/mi9120657 ................. 84 Jaehyun Lee, Oves Badami, Hamilton Carrillo-Nunez, Salim Berrada, Cristina Medina-Bailon, Tapas Dutta, Fikru Adamu-Lema, Vihar P. Georgiev and Asen Asenov Variability Predictions for the Next Technology Generations of n-type SixGe1−x Nanowire MOSFETs Reprinted from: Micromachines 2018, 9, 643, doi:10.3390/mi9120643 ................. 94 Xaver Klemenschits, Siegfried Selberherr and Lado Filipovic Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review Reprinted from: Micromachines 2018, 9, 631, doi:10.3390/mi9120631 .................105 v Nianduan Lu, Wenfeng Jiang, Quantan Wu, Di Geng, Ling Li and Ming Liu A Review for Compact Model of Thin-Film Transistors (TFTs) Reprinted from: Micromachines 2018, 9, 599, doi:10.3390/mi9110599 .................136 Raymond J. E. Hueting The Balancing Act in Ferroelectric Transistors: How Hard Can It Be? Reprinted from: Micromachines 2018, 9, 582, doi:10.3390/mi9110582 .................162 Lukas Gnam, Paul Manstetten, Andreas H¨ossinger, Siegfried Selberherr and Josef Weinbub Accelerating Flux Calculations Using Sparse Sampling † Reprinted from: Micromachines 2018, 9, 550, doi:10.3390/mi9110550 .................176 vi About the Special Issue Editors Lado Filipovic studied electrical engineering at Carleton University, in Ottawa, Canada, where he received the degree of Bachelor in electrical engineering (B.Eng.) in 2006 and Master in applied science (M.A.Sc) in 2009. He joined the Institute for Microelectronics in January 2010, where he completed his doctoral degree in December 2012, which focused on topography simulations of novel semiconductor processes. Since then his scientific interests have broadened to studying and modeling the effects of fabrication-induced variability on semiconductor geometries and their application in the fabrication of quantum metrology devices. His added research interests involve the design and simulation of environmental sensors and, more specifically, using metal oxide semiconductors and two-dimensional semiconductors for the detection of toxic gases and pollutants. Tibor Grasser is a professor of microelectronics reliability and an IEEE Fellow. He has been the head of the Institute for Microelectronics since 2016. He has edited various books, e.g. on advanced device modeling (World Scientific), the bias temperature instability (Springer) and hot carrier degradation (Springer), is a distinguished lecturer of the IEEE EDS, is a recipient of the Best and Outstanding Paper Awards at IRPS (2008, 2010, 2012, and 2014), IPFA (2013 and 2014), ESREF (2008) and the IEEE EDS Paul Rappaport Award (2011). He currently serves as an Associate Editor for the IEEE Transactions on Electron Devices following his assignment as Associate Editor for Microelectronics Reliability (Elsevier) and has been involved in various outstanding conferences such as IEDM, IRPS, SISPAD, ESSDERC, and IIRW. Prof. Grasser’s current research interests include theoretical modeling of performance aspects of 2D and 3D devices (charge trapping, reliability), starting from the ab initio level over more efficient quantum-mechanical descriptions up to TCAD modeling. The models developed in his group have been made available in the most important commercial TCAD environments. vii micromachines Editorial Editorial for the Special Issue on Miniaturized Transistors Lado Filipovic * and Tibor Grasser * Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Vienna, Austria * Correspondence: fi[email protected] (L.F.); [email protected] (T.G.) Received: 25 April 2019; Accepted: 25 April 2019; Published: 2 May 2019 Complementary Metal Oxide Semiconductor (CMOS) devices and fabrication techniques have enabled tremendous technological advancements in a short period of time. In recent decades transistor scaling has enabled us to fit into our pockets what would be considered a supercomputer a few decades ago. However, as we approach the physical limits of scaling, the question frequently asked is: What is the future of CMOS? Sustaining increased transistor densities along the path of Moore’s Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of 10 years ago, technological advancements have accelerated to today’s FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes afterwards? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly simulate future devices. There are 13 papers published in this Special Issue, covering recent advances in research aspects related to transistor miniaturization, including process and device simulation as well as novel transistor designs and innovative working principles for future transistor technologies. Two reviews are included in this Special Issue, covering technology computer aided design (TCAD) process and device simulations. To enable high performance TCAD and accelerated simulations, alternative meshing strategies are sought after, another topic addressed herein. High performance TCAD is indispensable for the design of future transistor structures. The sophistication and physical accuracy of the semiconductor models which are used today have reached unprecedented levels, allowing researchers to predict the best candidates for next generation devices without ever stepping foot into a fabrication facility. Using semiconductor TCAD, several authors in this Special Issue have proposed and analyzed different
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