Computer Organization Unit-II Final part

Central Processing Unit CPU – is the main component of the computer, which is used for data processing. When a data comes in the system from the outside world through a user using an input device, the data has to be first converted into the digital form and then it will be processed using the CPU. The will be coordinating all the devices using the control signals. The main components of the CPU are “ALU – Arithmetic and Logic Unit”, “ CU - Control unit” and “Register Set”. ALU unit will be taking the data stored in the register sets and will be processing the data using arithmetic, logic or shift operations. The data will be moving to and fro from register sets to ALU device. The major of the computers are designed using a single bus structure, in which the same bus line has to be shared among all the devices. Therefore there must be a device which will coordinate this data transfer through a single bus structure. This device is called as a Control Unit. The below diagram depicts the important parts of the CPU.

General Register Organization: In the previous details we discussed that when a data is to be processed, it has to be first fetched from the memory and then the data processing will begin. But if every time we continuously fetching the data from the memory, then many time cycles will be wasted. Instead we can store the repeatedly used data in the general purpose registers, such that we can retrieve it very fast without any time delays or processor cycles being wasted. CPU will be having a large no of Registers which are used for the above purpose. Since the registers are present, they have to be connected an incoming connection and outgoing connection, so that they can store and share the data. But the type of the bus system available in the computer is the Single bus system. Therefore the registers are also to be connected using this type of organization only. This is called as CPU General Register Organization. The following diagram represents the CPU General Registers organization.

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 1 Computer Organization Unit-II Final part

In this structure, we can see that the general purpose registers R1 to R7 are connected to the 8x1 pins from 1 to 7 and the input signal which is the external inputs or else simply the other input signal will be connected at the input pin 0. Each multiplexer has a set of input select signals such as SELA for Multiplexer A which is connected to A Bus and SELB for Multiplexer B which is connected to B Bus. Basing on the select signal combinations the different registers are selected at a time. After acquiring the data from the A bus and B Bus, the data will be transferred to ALU to perform a data transformation. So in-order to select what type of data transformation to perform, the ALU itself has another set of select signals called as OPR codes ( Operational Codes or Operation selector). OPR codes are of 5 length and each combination is used to control a different type of operation which an ALU will be performing. After the data transformation is complete, the resultant data will be stored in the AC accumulator and it can take two paths. The first path is that the resultant can be redirected to the output devices using the OUTR register. The second path is that the resultant can again be stored in the cpu registers for quick retrieval for another operation.(Ex: in loops). So if we consider the second part, then the data has to be stored in the general purpose registers again, therefore any one register should be having a load command. This will be decided as per the 3x8 Decoder signals generated using the set of select signals SELD. The seven signals generated will be used to control seven registers in which the data will be stored. This is the method of general register organization in the cpu. Control unit will be generating this all select signals in a format called as CONTROL WORD. The control word format is as follows.

SELA is used to control the A Multiplexer inputs SELB is used to control the B Multiplexer inputs SELC is used to indicate the register in which the resultant will be stored OPR is used to specify the type of the operation that will be executed by a ALU Unit.

The select signals combination table is given below Binary Code SELA SELB SELD “000” Input Input None

“001” R1 R1 R1

“010” R2 R2 R2

“011” R3 R3 R3

“100” R4 R4 R4

“101” R5 R5 R5

“110” R6 R6 R6

“111” R7 R7 R7 The above table represents the different possibilities of a multiplexer selecting the input signals basing on the set of select signals.

The following table gives the OPR codes using which the CPU will be performing the different operations. These OPR Codes are derived by using the combination circuits of Arithmetic circuit, Logic circuit, and Shift Circuit. When all the above circuits are combined the different select signals used to run the complete circuit is nothing but the OPR Codes. The combination of S 0,S1,S2,S3 and Default carry in C0 signals. OPR Code Operation Symbol “00000” Transfer A TSFA “00001” Increment A INCA

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 2 Computer Organization Unit-II Final part

“00010” Add A+B ADD “00101” Subtract A – B SUB “00110” Decrement A DECA “01000” AND A and B AND “01010” OR A and B OR “01100” XOR A and B XOR “01110” Complement A COMA “10000” Shift Right A SHRA “11000” Shift Left A SHLA

The following table indicates the several examples of micro operations performed by the ALU Unit. Micro Operation Symbolic Designation Control Word SELA SELB SELD OPR R1 ← R2 – R3 R2 R3 R1 SUB “010 011 001 00101” R4 ← R4 V R5 R4 R5 R4 OR “100 101 100 01010” R6 ← R6 + 1 R6 – R6 INCA “110 000 110 00001”

These are some examples of the control words that are generated to perform an operation. The conrol unit will only generate the output in the form of Control Words. The control words are interpreted by the devices to perform an operation.

Stack Organization: In the following topics we will be discussing the different types of stack implementation in the system. Before proceeding to the stack implementation, we will be knowing what is a stack. Stack is a data structure in which the data is stored and retrieved in a organized format. The operations of the stack are simply called as LIFO – Last In First Out. This means the element which is entered last in the stack will be the element first to be retrieved. There are different operations performed on stack in-order to implement the above operations. PUSH is an operation which is used to enter an element on to the top of the stack. POP is an operation which is used to delete or pop the top most element. Now we will see different implementations of stack in different scenarios.

Register Stack: The register stack is implemented using registers in the cpu. The different other things which are used to control this stack are the following. SP → Stack Pointer Register which keeps track of the current location in which an element has to be stored. FULL → This Register is used to indicate whether a stack is FULL or not. If FULL =1 then the stack is full. If FULL=0 then the stack is not full.(This doesn't mean the stack is empty) EMTY → This register is used to indicate whether a stack is EMPTY or not. If EMTY=1 then the stack is empty or if EMTY =0 that means the stack is not empty. (Again this doesn't mean that the stack is full, only some elements might be present in the stack.) The implementation of the stack is as follows. First we will consider the size of the stack, we will consider the size of the stack as 64 of each 16 bits. That means each memory location of the register will be storing 16 bits of data and there are 64 registers for implementation of the stack. First the stack pointer will be pointing to the “0” location. If you are performing a PUSH operation, then the stack pointer SP will be incremented to the next location and then the 16 data will be entered into

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 3 Computer Organization Unit-II Final part the register. Again if another element is to be entered then the SP will be again incremented and finally the data will be entered into the register. We will discuss this operation with the help of an example: Consider we are inserting the elements A, B, C, D into the stack. Then the different steps are as follows. • SP → 0, EMTY → 1, FULL → 0. Stack is empty. • PUSH A → SP → SP +1 => SP → 1, EMTY = 0, FULL =0. A entered. • PUSH B → SP → SP +1 => SP → 2, EMTY =0, FULL=0. B entered. • So on.., we will be acquiring some conditions here. First we should check after every insertion whether a stack is empty or not. This will be checked in the following way. After every successful insertion, we will check the following registers. We should check that EMTY =0 or not and simultaneously we should check FULL =1. if FULL =1 then stack is full and the stack pointer will be returned to the 0 position of the registers. SP returns to the 0 position because, the total address are 26=64; the addresses will be from 0 to 63. then 63=111111 in binary. If we increment SP beyond this that will be 000000 because we will be neglecting the carry because 6 bit positions cannot store 7 bits. Therefore we can say that when the SP is in incrementing movement and returns to 0 then the stack is full with elements. Likewise if the SP is in decrement movement and returns to 0 then the stack will be empty. These are the several conditions we have to check when working with the register stacks. The different operations along with the set of conditions are represented below:

Stack PUSH Operation: SP ← SP + 1; M[SP] ← DR; if (SP=0) then FULL ← 1; EMTY ← 0; Stack POP Operation: DR ← M[SP]; SP ← SP -1; if(SP=0) then EMTY ← 1;

FULL ← 0;

The next topic is the memory stack: MEMORY STACK The memory stack will be implemented in the following way. Memory unit will be storing different kinds of data. We can store programs( nothing but set of instructions), Data (Operands in the programs after initializing), and some free space. We can instruct a system to initialize the stack in the free memory banks of the computer. Before working on the stack operations, the stack memory will be initialized in the memory. Initializing of the stack means, memory will be allocated, stack pointer will be declared and finally two registers which will store the result whether the stack is full or empty. So when a stack is declared, the memory will be occupied as per the amount to be used to initialize the stack. For example a 50 amount of stack will occupy the following memory location. Think that the starting location is 3000, then the ending location will be 3050 location. Each location will be n bits length. The stack pointer can be implemented in two ways, either an incrementation mode or decremental mode. Consider the decremental mode. In this the stack pointer SP will be pointing to the ending location first. Then the element will be entered into the stack and then the SP

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 4 Computer Organization Unit-II Final part will be decremented. This PUSH operation will continue until all the memory locations of the stack are full nothing but SP has reached to the starting point (Ex: 3000 memory location). If PUSH Operation is carried out using the SP decrement mode, then the POP Operation will be carried out using the SP increment mode. The operations will be summarized as follows: PUSH Operation: M[SP] ← DR SP ← SP -1 POP Operation: SP ← SP +1 DR ← M[SP] the operations represented above are using SP decremental mode of operation.

Reverse Polish Notation: The best usage of the stack is in expression evaluation. There are three ways of representing the expression. • Infix Expression • Prefix Expression • Postfix Expression. In Infix expression we will write the expression as A*B + C*D. In Prefix Expression we will write the expression as +**ABCD. In Postfix Expression we will write the expression as AB*CD*+

In all the above expressions Post fix expressions are evaluated correctly. The stack expression evaluation will also be based on the post fix expression evaluation only. Post fix notations are also called as Reverse Polish Notation.

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 5 Computer Organization Unit-II Final part

Working of Stack: We will take an example expression and then we will work out the stack evaluation. Ex: 3*6+9*8

So the stack will be first initialized and will be empty. The first operation along with the following set of operations are given below. • PUSH 3 • PUSH 6 • PUSH * . Since * is a multiplication operator, the following operations will be executing • POP • POP • MUL A, B ( A will get the value from first POP, and B will get the value from second POP) • PUSH RESULT ( A*B will be stored in the RESULT) • Now the stack is having only one variable that is multiplication of 3 *6 =18; • PUSH 9 • PUSH 8 • PUSH * ( again * is an operator, which will perform two POP operations and multiplies the two variables and again PUSH operation will enter the result.) • The result is 9*8=72 • Now the stack has two values 18 and 72 ( as represented in diagram) • PUSH + (again + is an operator, which will perform two POP operations and multiplies the two variables and again PUSH operation will enter the result.) • Finally the stack is having only one value I.e.., 18+72 which is 90. • POP will return the result 90 as the final result. These are the several steps which will be performed by the stack when expression is being evaluated.

Instruction Formats: The instruction formats depicted below will be used as per the scenario.

Three Address Instructions: Three address instructions will be having the following fields. Operation,Destination, Source 1, Source 2 Ex: ADD R1, A, B R1 ← M[A]+M[B] ADD R2, C, D R2 ← M[C]+M[D] MUL X, R1, R2 M[X] ← R1 * R2

Two Address Instructions: Two address instructions will be having the following fields.

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 6 Computer Organization Unit-II Final part

Operation, Destination, Source Ex: MOV R1,A R1 ← M[A] ADD R1, B R1 ← R1+M[B] MOV R2,C R2 ← M[C] MOV R2,D R2 ← R2+M[D] MUL R1,R2 R1 ← R1 + R2 MOV X,R1 M[X] ← R1

One Address Instructions: One address instructions will be having the following fields. Operation Source Ex: LOAD A AC ← M[A] ADD B AC ← AC + M[B] STORE T M[T] ← AC LOAD C AC ← M[C] ADD D AC ← AC +M[D] MUL T AC ← AC * M[T] STORE X M[X] ← AC

Zero Address Instructions: Zero address instructions will be having the following fields. Zero address instructions will be achieved using the stack operations.

PUSH A T0S ← A PUSH B TOS ← B ADD TOS ← (A +B) PUSH C TOS ← C PUSH D TOS ← D ADD TOS ← (C +D ) MUL TOS ← (C+D)*(A+B) POP X M[X] ← TOS

ADDRESSING MODES: The default addressing modes we discussed are “Direct ”, “Indirect Addressing mode”, “Immediate addressing mode”. Apart from this several other types of addressing modes are available. They are: Register Mode: In this mode the operands are in registers that reside within the CPU.

Register indirect mode: In this mode the operands will be present in one register and in-order to retrieve that data, we have to follow a path. The actual register in which the data will be present has to be derived from the set of registers as follows. M[R1] → R2; M[R2] → R3; M[R3] → R4; and R4 will contain the data. So if we want to retrieve the data in R4 we have to follow the path from R1.

Auto-increment and Auto-decrement mode: In this mode the register after fetching the effective address of an operand will automatically increments itself. We can take the example of PC register,

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 7 Computer Organization Unit-II Final part which after every successful fetching of an incrementation will be incrementing itself.

Relative Addressing mode: In this simply the data present in the PC will be added to the address part of the instruction and the data or operand will be fetched. Think that the memory 800 is having the instruction and the data is present somewhere, the address in the PC is 25, then simply add 800 to 25, resulting in 825 which is the address of the data.

Indexed Addressing mode: In this addressing mode simply all the memory locations are organized by assigning the index values. Using this index values the communication or the data retrieving will be taking place.

Base Register Addressing mode: In this addressing mode the base register whose data is used to find the effective address will be used and using this root node the leaf addresses will be found.

You can find the numeric example in the Moris Mano Third Edition Reprint 2007 Text book at page no 265.

Data transfer and Manipulation In this topic we will be discussing the following topics. Data Transfer Instructions Data Manipulation Instructions Program Control Instructions

Data Transfer Instructions: Data transfer instructions will be used to move the data in the following scenarios. “Memory to Register Transfer”, “Register to Register Transfer”, “Input – Output Registers to CPU register Transfers”. In all the above instructions the data will be taken from the source unit and will be transferred to the destination register or a memory unit. The typical data transfer instructions are: • Load LD • Store ST • Move MOV • Exchange XCH • Input IN • Output OUT • Push PUSH • Pop POP. These are the several data transfer instructions. When a data transfer instruction is executing, naturally the source data has to be fetched and then it will be sent or written to the destination. Therefore the fetching of the source data will be done in the 8 forms we discussed above. Using different types of addressing modes. The illustration of the load command using all the types of addressing modes are given below.

Mode Assembly convention Register Transfer Direct Address LD ADR AC ← M[ADR] Indirect Address LD @ADR AC ← M[M[ADR]] Relative Address LD $ADR AC ← M[PC + ADR]

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 8 Computer Organization Unit-II Final part

Immediate Operand LD #NBR AC ← NBR Index Address LD ADR(X) AC ← M[ADR + XR] Register Transfer LD R1 AC ← R1 Register Indirect LD (R1) AC ← M[R1] Auto-increment LD (R1)+ AC ← M[R1], R1 ← R1+1 The above table shows the implementation of Load LD operation in all the types of addressing modes.

Data Manipulation Instructions: Data manipulation instructions will be used for data processing. Data processing in the sense we will be performing the following transformations on the data.

Arithmetic Instructions Logical and Bit Manipulation Instructions Shift Instructions We will be discussing all the above instructions one by one.

Arithmetic Instructions: arithmetic instructions will be consisting of the following operations. Name Mnemonic Increment INC Decrement DEC ADD ADD Subtract SUB Multiply MUL Divide DIV Add with Carry ADDC Subtract with borrow SUBB Negate(2's complement) NEG Logic and Bit Manipulation Instructions:

Name Mnemonic Clear CLR Complement COM AND AND Or OR Exclusive- OR XOR Clear Carry CLRC Set Carry SETC Complement Carry COMC

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 9 Computer Organization Unit-II Final part

Enable EI Disable Interrupt DI Shift Instructions: Name Mnemonic Logical Shift Right SHR Logical Shift Left SHL Arithmetic Shift Right SHRA Arithmetic Shift Left SHLA Rotate Left ROL Rotate Right ROR Rotate Right through RORC carry Rotate Left through carry ROLC Program Control: In a normal program execution, the instruction will be fetched from the memory using the PC register and the instruction will be thereafter transferred to the IR Register. Then finally the instruction will be executed and after that the PC will be incremented to the next location. But if the programmer is programming to consider any conditions, then the program execution sequence will be altered as per the conditions. So naturally in this particular scenario the program control will be changing. Therefore when a condition satisfies the program will be either branching or it will Jump or some other sub routines will be executing.

The different branch conditions are described below: Name Mnemonic Branch BR Jump JMP Skip SKP Call CALL Return RET Compare COM (by subtraction) Test TST (By AND gate) So if any of the above branching statements are used then the conditions which are initializing this branching conditions should also be denoted. The system will be having this checking conditions as “Flag bits”. The flag bits are those which will decide which branch to follow. This flag bits are also called as “Status Bit conditions”. The different flag bits or status bits are discussed below in detail:

C Bit: This is called as a “Carry Flag Bit” which is set to one if end carry C8 in the arithmetic operation or shift operation from an ALU unit is getting as 1. It is cleared to “0” if the C8 carry position is not getting any carry.

S Bit: This is called as “Sign bit”, in which we will check whether the highest order bit F7 in the 8 bits.

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 10 Computer Organization Unit-II Final part

If F7 is equal to 1, that means a negative number is coming and if F7 is equal to “0”, that means a positive number is coming.

Z Bit: This is called as “Zero flag bit”, in which we will check whether the AC is having all the values as “0” or not. If Z flag is set to one that means the AC value is 0 otherwise the accumulator value is not empty.

V Bit: This is called as “Overflow bit”, in which we will check whether there is an overflow occurring in the system or not. If V flag is set to 1 that means an overflow has occurred, and if v flag is set to 0 that means no overflow is occurred.

The implementation of the Status bit conditions in the hardware circuit is given below. Here we are considering an 8 – bit ALU unit which is getting two data A and B. by performing different operations, we are deciding the type of the flag bits generated.

Conditional Branch Instructions: In the following table we will see different types of branch conditions along with the set of testing conditions on the status bits. Mnemonic Branch condition Tested Condition BZ Branch if Zero Z=0 BNZ Branch if not zero Z=1 BC Branch if carry C=1 BNC Branch if no carry C=0 BP Branch if positive S=0 BM Branch if Negative S=1 BV Branch if overflow V=1 BNV Branch if no overflow V=0 Unsigned Compare conditions (A-B) BHI Branch if higher A>B

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 11 Computer Organization Unit-II Final part

BHE Branch if Higher and equal A>=B BLO Branch if lower AB BGE Branch if greater and equal A>=B BLT Branch if less than A

Subroutine Call and Return: Subroutine indicates a set of instructions which execute separately from the main execution program. We can call a subroutine at any point of the program execution using a simple CALL micro operation known as “Call Subroutine”, or using JMP micro operation known as “Jump to Subroutine”, or using BRANCH micro operation known as “Branch to Subroutine”,or using BSA micro operation known as “Branch and Save the address”. Mainly there are two types of calling a subroutine. First one when we are executing a subroutine and we will not return to the main program execution, we will simply exit from the subroutine, the second one is that after the subroutine execution is completed successfully we will be returning to the original state of execution in the main program. When we are returning to the main program, we need to store the address value of the location where the execution has to be resumed. This can be achieved using the BSA command or using the combination of CALL and RET commands. The subroutine call is implemented using stack operation is done in the following micro operations: SP ← SP -1 Decrement the stack pointer M[SP] ← PC Push content of PC onto the stack PC ← effective address Transfer control to the subroutine

The returning from the subroutine is implemented again using the stack operations as depicted below: PC ← M[SP] Pop stack and transfer to PC SP ← SP+1 Increment the stack pointer.

Program : The purpose of interrupts is to handle some exceptional data at any given time as per the requirements. Consider a critical clock cycle which cannot wait until all the operations are completed by the CPU. Then the process of the CPU will be temporarily suspended and finally after finishing the critical process, CPU will be resuming the original process. Interrupts can be generated by any device which can be either internal or external.

After a program has been interrupted and the service routine been executed, the CPU must return to exactly the same state that it was when the interrupt occurred. Only if this happens will the interrupted program be able to resume exactly as if nothing had happened. The state of the CPU at the

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 12 Computer Organization Unit-II Final part end of the execute cycle is determined from • The content of the . • The content of all processor registers. • The content of certain status conditions. The collection of all status bit conditions in the CPU is sometimes called a Program Status Word (PSW). The PSW is stored in a separate hardware register and contains the status information that characterizes the state of the CPU. CPU is executing a program that is part of the operating system, it is said to be in the supervisor mode or system mode. Generally CPU will be executing in user mode, where it executes the user programs. Certain instructions are privileged and can be executed in supervisor mode only.

Types of Interrupts: External Interrupts Internal Interrupts Interrupts

Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 13