Computer Organization Unit-II Final part Central Processing Unit CPU – Central processing unit is the main component of the computer, which is used for data processing. When a data comes in the system from the outside world through a user using an input device, the data has to be first converted into the digital form and then it will be processed using the CPU. The control unit will be coordinating all the devices using the control signals. The main components of the CPU are “ALU – Arithmetic and Logic Unit”, “ CU - Control unit” and “Register Set”. ALU unit will be taking the data stored in the register sets and will be processing the data using arithmetic, logic or shift operations. The data will be moving to and fro from register sets to ALU device. The major of the computers are designed using a single bus structure, in which the same bus line has to be shared among all the devices. Therefore there must be a device which will coordinate this data transfer through a single bus structure. This device is called as a Control Unit. The below diagram depicts the important parts of the CPU. General Register Organization: In the previous details we discussed that when a data is to be processed, it has to be first fetched from the memory and then the data processing will begin. But if every time we continuously fetching the data from the memory, then many time cycles will be wasted. Instead we can store the repeatedly used data in the processor general purpose registers, such that we can retrieve it very fast without any time delays or processor cycles being wasted. CPU will be having a large no of Registers which are used for the above purpose. Since the registers are present, they have to be connected an incoming connection and outgoing connection, so that they can store and share the data. But the type of the bus system available in the computer is the Single bus system. Therefore the registers are also to be connected using this type of organization only. This is called as CPU General Register Organization. The following diagram represents the CPU General Registers organization. Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 1 Computer Organization Unit-II Final part In this structure, we can see that the general purpose registers R1 to R7 are connected to the 8x1 Multiplexers pins from 1 to 7 and the input signal which is the external inputs or else simply the other input signal will be connected at the multiplexer input pin 0. Each multiplexer has a set of input select signals such as SELA for Multiplexer A which is connected to A Bus and SELB for Multiplexer B which is connected to B Bus. Basing on the select signal combinations the different registers are selected at a time. After acquiring the data from the A bus and B Bus, the data will be transferred to ALU to perform a data transformation. So in-order to select what type of data transformation to perform, the ALU itself has another set of select signals called as OPR codes ( Operational Codes or Operation selector). OPR codes are of 5 bits length and each combination is used to control a different type of operation which an ALU will be performing. After the data transformation is complete, the resultant data will be stored in the AC accumulator and it can take two paths. The first path is that the resultant can be redirected to the output devices using the OUTR register. The second path is that the resultant can again be stored in the cpu registers for quick retrieval for another operation.(Ex: in loops). So if we consider the second part, then the data has to be stored in the general purpose registers again, therefore any one register should be having a load command. This will be decided as per the 3x8 Decoder signals generated using the set of select signals SELD. The seven signals generated will be used to control seven registers in which the data will be stored. This is the method of general register organization in the cpu. Control unit will be generating this all select signals in a format called as CONTROL WORD. The control word format is as follows. SELA is used to control the A Multiplexer inputs SELB is used to control the B Multiplexer inputs SELC is used to indicate the register in which the resultant will be stored OPR is used to specify the type of the operation that will be executed by a ALU Unit. The select signals combination table is given below Binary Code SELA SELB SELD “000” Input Input None “001” R1 R1 R1 “010” R2 R2 R2 “011” R3 R3 R3 “100” R4 R4 R4 “101” R5 R5 R5 “110” R6 R6 R6 “111” R7 R7 R7 The above table represents the different possibilities of a multiplexer selecting the input signals basing on the set of select signals. The following table gives the OPR codes using which the CPU will be performing the different operations. These OPR Codes are derived by using the combination circuits of Arithmetic circuit, Logic circuit, and Shift Circuit. When all the above circuits are combined the different select signals used to run the complete circuit is nothing but the OPR Codes. The combination of S 0,S1,S2,S3 and Default carry in C0 signals. OPR Code Operation Symbol “00000” Transfer A TSFA “00001” Increment A INCA Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 2 Computer Organization Unit-II Final part “00010” Add A+B ADD “00101” Subtract A – B SUB “00110” Decrement A DECA “01000” AND A and B AND “01010” OR A and B OR “01100” XOR A and B XOR “01110” Complement A COMA “10000” Shift Right A SHRA “11000” Shift Left A SHLA The following table indicates the several examples of micro operations performed by the ALU Unit. Micro Operation Symbolic Designation Control Word SELA SELB SELD OPR R1 ← R2 – R3 R2 R3 R1 SUB “010 011 001 00101” R4 ← R4 V R5 R4 R5 R4 OR “100 101 100 01010” R6 ← R6 + 1 R6 – R6 INCA “110 000 110 00001” These are some examples of the control words that are generated to perform an operation. The conrol unit will only generate the output in the form of Control Words. The control words are interpreted by the devices to perform an operation. Stack Organization: In the following topics we will be discussing the different types of stack implementation in the system. Before proceeding to the stack implementation, we will be knowing what is a stack. Stack is a data structure in which the data is stored and retrieved in a organized format. The operations of the stack are simply called as LIFO – Last In First Out. This means the element which is entered last in the stack will be the element first to be retrieved. There are different operations performed on stack in-order to implement the above operations. PUSH is an operation which is used to enter an element on to the top of the stack. POP is an operation which is used to delete or pop the top most element. Now we will see different implementations of stack in different scenarios. Register Stack: The register stack is implemented using registers in the cpu. The different other things which are used to control this stack are the following. SP → Stack Pointer Register which keeps track of the current location in which an element has to be stored. FULL → This Register is used to indicate whether a stack is FULL or not. If FULL =1 then the stack is full. If FULL=0 then the stack is not full.(This doesn't mean the stack is empty) EMTY → This register is used to indicate whether a stack is EMPTY or not. If EMTY=1 then the stack is empty or if EMTY =0 that means the stack is not empty. (Again this doesn't mean that the stack is full, only some elements might be present in the stack.) The implementation of the stack is as follows. First we will consider the size of the stack, we will consider the size of the stack as 64 of each 16 bits. That means each memory location of the register will be storing 16 bits of data and there are 64 registers for implementation of the stack. First the stack pointer will be pointing to the “0” location. If you are performing a PUSH operation, then the stack pointer SP will be incremented to the next location and then the 16 bit data will be entered into Computer Organization Notes By G.Naveen kumar, Asst Prof, CSE, VITAE 3 Computer Organization Unit-II Final part the register. Again if another element is to be entered then the SP will be again incremented and finally the data will be entered into the register. We will discuss this operation with the help of an example: Consider we are inserting the elements A, B, C, D into the stack. Then the different steps are as follows. • SP → 0, EMTY → 1, FULL → 0. Stack is empty. • PUSH A → SP → SP +1 => SP → 1, EMTY = 0, FULL =0. A entered. • PUSH B → SP → SP +1 => SP → 2, EMTY =0, FULL=0. B entered. • So on.., we will be acquiring some conditions here. First we should check after every insertion whether a stack is empty or not. This will be checked in the following way. After every successful insertion, we will check the following registers.