DOCSLIB.ORG

A Formalism for Visual Query Interface Design

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

A Formalism for Visual Query Interface Design by Jiwen Huo A thesis presented to the University of Waterloo in fulfillment of the thesis requirement for the degree of Doctor of Philosophy in Computer Science Waterloo, Ontario, Canada, 2008 c Jiwen Huo 2008 Library and Archives Bibliothèque et Canada Archives Canada Published Heritage Direction du Branch Patrimoine de l’édition 395 Wellington Street 395, rue Wellington Ottawa ON K1A 0N4 Ottawa ON K1A 0N4 Canada Canada Your file Votre référence ISBN: 978-0-494-55514-9 Our file Notre référence ISBN: 978-0-494-55514-9 NOTICE: AVIS: The author has granted a non- L’auteur a accordé une licence non exclusive exclusive license allowing Library and permettant à la Bibliothèque et Archives Archives Canada to reproduce, Canada de reproduire, publier, archiver, publish, archive, preserve, conserve, sauvegarder, conserver, transmettre au public communicate to the public by par télécommunication ou par l’Internet, prêter, telecommunication or on the Internet, distribuer et vendre des thèses partout dans le loan, distribute and sell theses monde, à des fins commerciales ou autres, sur worldwide, for commercial or non- support microforme, papier, électronique et/ou commercial purposes, in microform, autres formats. paper, electronic and/or any other formats. The author retains copyright L’auteur conserve la propriété du droit d’auteur ownership and moral rights in this et des droits moraux qui protège cette thèse. Ni thesis. Neither the thesis nor la thèse ni des extraits substantiels de celle-ci substantial extracts from it may be ne doivent être imprimés ou autrement printed or otherwise reproduced reproduits sans son autorisation. without the author’s permission. In compliance with the Canadian Conformément à la loi canadienne sur la Privacy Act some supporting forms protection de la vie privée, quelques may have been removed from this formulaires secondaires ont été enlevés de thesis. cette thèse. While these forms may be included Bien que ces formulaires aient inclus dans in the document page count, their la pagination, il n’y aura aucun contenu removal does not represent any loss manquant. of content from the thesis. I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. ii Abstract The massive volumes and the huge variety of large knowledge bases make infor- mation exploration and analysis difficult. An important activity is data filtering and selection, in which both querying and visualization play important roles. Interfaces for data exploration environments normally include both, integrating them as tightly as possible. But many features of information exploration environments, such as visual rep- resentation of queries, visualization of query results, interactive data selection from visualizations, have only been studied separately. The intrinsic connections between them have not been described formally. The lack of formal descriptions inhibits the development of techniques that produce new representations for queries, and natural integration of visual query specification with query result visualization. This thesis describes a formalism that describes the basic components of informa- tion exploration and and their relationships in information exploration environments. The key aspect of the formalism is that it unifies querying and visualization within a single framework, which provides a foundation for designing and analysing visual query interfaces. Various innovative designs of visual query representations can be derived from the formalism. Simply comparing them with existing ones is not enough, it is more im- portant to discover why one visual representation is better or worse than another. To do this it is necessary to understand users’ cognitive activities, and to know how these cognitive activities are enhanced or inhibited by different presentations of a query so that novel interfaces can be created and improved based on user testing. This thesis presents a new experimental methodology for evaluating query repre- sentations, which uses stimulus onset asynchrony to separate different aspects of query comprehension. This methodology was used to evaluate a new visual query represen- tation based on Karnaugh maps, and showing that there are two qualitatively different approaches to comprehension: deductive and inductive. The Karnaugh map represen- tation scales extremely well with query complexity, and the experiment shows that its good scaling properties occur because it strongly facilitates inductive comprehension. iii Acknowledgements There are many people whose support, guidance, and encouragement have made this thesis possible. I am especially grateful to my advisor, William Cowan, for his advice, support, and guidance throughout my study in Waterloo. He has taught me so much and been a great mentor. In addition, I would like to thank my reading committee, Christopher Healey, Catherine Burns, Grant Weddell, and Ric Holt, for the time and effort they spent to read and comment on my work. Also, I would like to thank all of people who participated in my experiments for their time and attention. Special acknowledgement goes to Yi Lin, Jie Xu, and Yinbin Liu, for giving me feedbacks and suggestions on my pilot study to improve the experiment. Most of all, I would like to thank my parents and my husband Chong for always supporting and encouraging me. Without their love and support, the completion of this thesis would not be possible. Finally I’d like to thank my son Ray for the joy he brings to my life. iv Contents List of Tables 1 List of Figures 1 1 Introduction 1 1.1 Contributions . 2 1.2 User Interface Issues in Information Exploration . 3 1.3 A Formalism for Visual Query Interface . 4 1.4 Issues in Evaluating Query Languages . 5 1.5 The Experiment Methodology . 6 1.6 Thesis Organization . 7 2 Related Work on Visual Information Exploration 9 2.1 Information Exploration . 9 2.1.1 Information Exploration Process . 9 2.1.2 Visual Information Exploration . 11 2.2 Information Visualization . 13 2.2.1 The Process of Visualization . 13 2.2.2 Data Model . 14 2.2.3 Visual Mapping . 15 2.2.4 Data Selection and Visualization . 16 2.3 Boolean Query Specification . 17 2.3.1 Boolean Expressions and Truth-Tables . 18 2.3.2 Command Languages and Natural Language for Data Querying 19 2.3.3 Form-Based Query and Dynamic Query Technique . 21 v 2.3.4 Graphical Approaches to Query Specification Based on Boolean Expressions . 21 2.3.5 Graphical Approaches to Query Specification Based on Truth- Table................................. 23 2.4 Query Result Display . 25 2.4.1 Query Preview and Immediate Updates of Query Results . 26 2.4.2 Context Information of Data Distribution along Each Attribute 27 2.4.3 Rank of Query Results . 27 2.4.4 The Relationship of Query Results with Query Terms . 27 2.5 Interactive Data Selection on Visual View . 28 2.6 Formal Models of Visual Information Exploration . 30 3 A Formalism for Visual Query Interfaces 33 3.1 The Table Model . 33 3.1.1 Definition of the Table Model . 34 3.1.2 Applying Tables to Tables . 35 3.1.3 Data Visualization by Tables . 36 3.1.4 Table Model for Queries . 37 3.1.5 Visualizing Queries . 38 3.2 The Transformation Model . 40 3.2.1 Query on Data Space . 41 3.2.2 Visual Query on Visual Representations . 42 3.3 Query Result Visualization . 44 3.3.1 Traditional Method of Query Result Visualization . 44 3.3.2 Example: Enhanced Visualization of Query Result . 45 3.3.3 The Transformation Model of Query Result Visualization . 45 3.3.4 Examples of Query Result Visualization . 47 3.4 Visualizing the Mappings . 48 3.4.1 Visualizing the Visualization Mappings . 48 3.4.2 Visualizing the Query Mappings . 50 3.5 The Recursive Models . 52 3.5.1 Visualizing Visual Representations . 53 3.5.2 Querying on Queries . 54 3.5.3 The Iterative Model . 54 vi 3.6 Summary . 56 4 The Application System KMVQL 58 4.1 Software Design based on the Formalism . 58 4.1.1 User Actions . 59 4.1.2 Software Domain Model . 60 4.1.3 Module Responsibilities . 61 4.1.4 Summary of the Software Model . 63 4.2 Overview of KMVQL . 64 4.2.1 Visualization of Query and Query Results . 64 4.2.2 Visualization of Data Space . 66 4.2.3 Query Device . 67 4.2.4 Information Seeking Nodes . 68 4.2.5 Formulate Boolean Queries in KMVQL . 68 4.2.6 Compound Query based on Intermediate Results . 69 4.3 Example of Exploring Data with KMVQL . 71 4.4 Summary . 75 5 Related Work on Query Language Evaluation 76 5.1 Introduction to Query Language Evaluation . 76 5.1.1 Framework of Variables for Query Language Evaluation . 77 5.1.2 Tasks for Query Language Evaluation . 79 5.1.3 Boolean Concept Complexity . 79 5.2 Review of Related Experiments . 82 5.2.1 Example Analysis: TEBI . 82 5.2.2 Example Analysis: Filter/Flow . 84 5.2.3 Example Analysis: Chui’s User Study on Query Languages . 84 5.2.4 Summary of Previous Experiments . 86 6 A Methodology for Evaluating Visual Query Languages 89 6.1 Introduction . 89 6.2 Method . 90 6.2.1 Query Task . 90 6.2.2 Components of Query Task . 91 vii 6.3 Isolating the Time Components . 91 6.3.1 Manipulating Stimulus Onset Asynchrony . 92 6.3.2 A Possible Experimental Hypothesis . 92 6.3.3 Data Fitting . 94 7 The Experiment 96 7.1 Introduction . 96 7.2 Method . 97 7.2.1 Query Task . 97 7.2.2 Experiment Trials . 98 7.2.3 Queries .
Recommended publications
  • Boolean Algebra

    Boolean Algebra

    Boolean Algebra Definition: A Boolean Algebra is a math construct (B,+, . , ‘, 0,1) where B is a non-empty set, + and . are binary operations in B, ‘ is a unary operation in B, 0 and 1 are special elements of B, such that: a) + and . are communative: for all x and y in B, x+y=y+x, and x.y=y.x b) + and . are associative: for all x, y and z in B, x+(y+z)=(x+y)+z, and x.(y.z)=(x.y).z c) + and . are distributive over one another: x.(y+z)=xy+xz, and x+(y.z)=(x+y).(x+z) d) Identity laws: 1.x=x.1=x and 0+x=x+0=x for all x in B e) Complementation laws: x+x’=1 and x.x’=0 for all x in B Examples: • (B=set of all propositions, or, and, not, T, F) • (B=2A, U, ∩, c, Φ,A) Theorem 1: Let (B,+, . , ‘, 0,1) be a Boolean Algebra. Then the following hold: a) x+x=x and x.x=x for all x in B b) x+1=1 and 0.x=0 for all x in B c) x+(xy)=x and x.(x+y)=x for all x and y in B Proof: a) x = x+0 Identity laws = x+xx’ Complementation laws = (x+x).(x+x’) because + is distributive over . = (x+x).1 Complementation laws = x+x Identity laws x = x.1 Identity laws = x.(x+x’) Complementation laws = x.x +x.x’ because + is distributive over .
  • Algorithm for Two-Level Simplification (Example)

    Algorithm for Two-Level Simplification (Example)

    CSE 370 Spring 2006 Administrivia Introduction to Digital Design Homework 3 due Friday Lecture 8: Introduction to Verilog Last Lecture Design Examples a K-maps Minimization Algorithm Today Introduction to Verilog Algorithm for two-level simplification Algorithm for two-level Algorithm: minimum sum-of-products expression from a Karnaugh map simplification (example) A A A Step 1: choose an element of the ON-set X101 X101 X101 Step 2: find "maximal" groupings of 1s and Xs adjacent to that 0111 0111 0111 element D D D consider top/bottom row, left/right column, and corner 0XX0 0XX0 0XX0 adjacencies C C C this forms prime implicants (number of elements always a power 0101 0101 0101 of 2) B B B 2 primes around A'BC'D' 2 primes around ABC'D Repeat Steps 1 and 2 to find all prime implicants A A A Step 3: revisit the 1s in the K-map X101 X101 X101 if covered by single prime implicant, it is essential, and 0111 0111 0111 participates in final cover D D D 1s covered by essential prime implicant do not need to be 0XX0 0XX0 0XX0 revisited C C C Step 4: if there remain 1s not covered by essential prime implicants 0101 0101 0101 B B B select the smallest number of prime implicants that cover the 3 primes around AB'C'D' 2 essential primes minimum cover (3 primes) remaining 1s Visit All in the On Set? Activity List all prime implicants for the following K-map: A A 00X001X0 X0X0 0111X1 01X1 CD’ D BC BD AB AC’D D CD’ BC BD AB AC’D 010X11X0 0XX0 C C 00X10111 X111 B B CD’ BD AC’D CD’ BD AC’D Which are essential prime implicants? CD’ BD AC’D CD’ BD AC’D What
  • Combinational Logic Circuits

    Combinational Logic Circuits

    CHAPTER 4 COMBINATIONAL LOGIC CIRCUITS ■ OUTLINE 4-1 Sum-of-Products Form 4-10 Troubleshooting Digital 4-2 Simplifying Logic Circuits Systems 4-3 Algebraic Simplification 4-11 Internal Digital IC Faults 4-4 Designing Combinational 4-12 External Faults Logic Circuits 4-13 Troubleshooting Prototyped 4-5 Karnaugh Map Method Circuits 4-6 Exclusive-OR and 4-14 Programmable Logic Devices Exclusive-NOR Circuits 4-15 Representing Data in HDL 4-7 Parity Generator and Checker 4-16 Truth Tables Using HDL 4-8 Enable/Disable Circuits 4-17 Decision Control Structures 4-9 Basic Characteristics of in HDL Digital ICs M04_WIDM0130_12_SE_C04.indd 136 1/8/16 8:38 PM ■ CHAPTER OUTCOMES Upon completion of this chapter, you will be able to: ■■ Convert a logic expression into a sum-of-products expression. ■■ Perform the necessary steps to reduce a sum-of-products expression to its simplest form. ■■ Use Boolean algebra and the Karnaugh map as tools to simplify and design logic circuits. ■■ Explain the operation of both exclusive-OR and exclusive-NOR circuits. ■■ Design simple logic circuits without the help of a truth table. ■■ Describe how to implement enable circuits. ■■ Cite the basic characteristics of TTL and CMOS digital ICs. ■■ Use the basic troubleshooting rules of digital systems. ■■ Deduce from observed results the faults of malfunctioning combina- tional logic circuits. ■■ Describe the fundamental idea of programmable logic devices (PLDs). ■■ Describe the steps involved in programming a PLD to perform a simple combinational logic function. ■■ Describe hierarchical design methods. ■■ Identify proper data types for single-bit, bit array, and numeric value variables.
  • Final Book -Architecture.Pdf

    Final Book -Architecture.Pdf

    1 BHARATHIDASAN UNIVERSITY (Re-accredited with ‘A’ Grade by NAAC) CENTRE FOR DISTANCE EDUCATION PALKALAIPERUR, TIRUCHIRAPPALLI – 24 MCA / PGDCA I - Semester Computer Organization and Architecture CORE COURSE III (Full Package) Copy right reserved For Private Circulation only 2 Chairman: Dr. V.M Muthukumar Vice-Chancellor Bharathidasan University Tiruchirappalli – 620 024. Co-Ordinator: Dr. R.Babu Rajendren Registrar i/c Centre for Distance Education Bharathidasan University Tiruchirappalli – 620 024. Course Director: Dr.V.Vinod Kumar Director i/c Centre for Distance Education Bharathidasan University Tiruchirappalli – 620 024. The Syllabus Revised from 2017-18 onwards Lesson Writer: Dr. J.Sai Geetha Asst. Professor Department of Computer Science Nehru Memorial College Puthanampatti Tituchirappalli – 621 007. 3 CORE COURSE III COMPUTER ORGANIZATION AND ARCHITECTURE Objective: To understand the principles of digital computer logic circuits and their design. To understand the working of a central processing unit architecture of a computer Unit I Number Systems – Decimal, Binary, Octal and Hexadecimal Systems – Conversion from one system to another – Binary Addition, Subtraction, Multiplication and Division – Binary Codes– 8421, 2421, Excess-3, Gray, BCD – Alphanumeric Codes – Error Detection Codes. Unit II Basic Logic Gates – Universal Logic – Boolean Laws and Theorems – Boolean Expressions – Sum of Products – Product of Sums – Simplification of Boolean Expressions –Karnaugh Map Method (up to 4 Variables) – Implementation of Boolean Expressions using Gate Networks. Unit III Combinational Circuits – Multiplexers – Demultiplexers – Decoders – Encoders – Arithmetic Building Blocks – Half and Full Adders – Half and Full Subtractors – Parallel adder –2’s Complement Adder – Subtractor – BCD Adder. Unit IV Sequential Circuits – Flip Flops – RS, Clocked RS, D, JK, T and Master- Slave Flip Flops –Shift Register – Counters – Asynchronous, MOD-n and Synchronous Counters – BCD Counter –Ring Counter.
  • 'N' VARIABLES - a NOVEL APPROACH Dr.V.D.Ambeth Kumar1 and Gokul Amuthan .S2 1

    'N' VARIABLES - a NOVEL APPROACH Dr.V.D.Ambeth Kumar1 and Gokul Amuthan .S2 1

    STATIC STRUCTURE SIMPLIFICATION OF BOOLEAN FUNCTION FOR 'N' VARIABLES - A NOVEL APPROACH Dr.V.D.Ambeth Kumar1 and Gokul Amuthan .S2 1. Asso.Professor, Department of CSE, Panimalar Engineering College, Chennai, India-600123. 2. UG Student, Department of CSE, Panimalar Engineering College, Chennai, India-600123. Email: [email protected] ABSTRACT Digital Systems have a prominent role in everyday life that we refer to the present technological period as the digital age.[1] Digital Systems implement digital circuits which are mostly combination of digital gates. These gates can be represented in an understandable form called Boolean expressions. These expressions formed vary for each circuit. Hence for building an efficient circuit the Boolean expression should be minimized. To achieve this, we use, Karnaugh map (K-map) and Quine-McCluskey (QM) methods which are well known methods to simplify Boolean expression. The K-map until now is introduced to solve up to 6 variable and QM which can solve ‘n’ variables, yet it involve a serious of steps and does not provide a visual way to minimising the expression. The following paper implements the idea of K-map to reduce the expression except that it could solve ‘n’ variables as QM method. The method Divide and Conquer Karnaugh map (DC-K-map) implements 4 variable K-map in a redundant way to reduce the expression for variables greater than 7. Keywords: Karnaugh map, Boolean functions, Quine-McCluskey Method, Grouping and Simplification. 1. INTRODUCTION In 1854, George Boole introduced a systematic treatment of logic and developed for this purpose an algebraic system now called as Boolean Algebra[12].
  • Static Structure Simplification of Boolean Function for 'N' Variables

    Static Structure Simplification of Boolean Function for 'N' Variables

    VISVAM DEVADOSS AMBETH KUMAR AND S. GOKUL AMUTHAN: STATIC STRUCTURE SIMPLIFICATION OF BOOLEAN FUNCTION FOR ‘N’ VARIABLES - A NOVEL APPROACH DOI: 10.21917/ijme.2016.0024 STATIC STRUCTURE SIMPLIFICATION OF BOOLEAN FUNCTION FOR ‘N’ VARIABLES - A NOVEL APPROACH Visvam Devadoss Ambeth Kumar1 and S. Gokul Amuthan2 Department of Computer Science and Engineering, Panimalar Engineering College, India E-mail: [email protected], [email protected] Abstract referred to as tabulation method. This method was best suited for Digital Systems have a prominent role in everyday life that we refer to computer algorithms yet it has limited range of use as it solves the the present technological period as the digital age. Digital Systems problem in NP-Hard way. [5] This paper uses K-map method, implement digital circuits which are mostly combination of digital with slight modification to solve greater than 7 variables. gates. These gates can be represented in an understandable form called Boolean expressions. These expressions formed vary for each circuit. Hence for building an efficient circuit the Boolean expression should 2. SYMBOLIZING THE BOOLEAN FUNCTION be minimized. To achieve this, we use, Karnaugh map (K-map) and Quine-McCluskey (QM) methods which are well known methods to To represent the Boolean functions we use four golden simplify Boolean expression. The K-map until now is introduced to representations. solve up to 6 variable and QM which can solve ‘n’ variables, yet it involve a serious of steps and does not provide a visual way to 2.1 TRUTH TABLE minimising the expression. The following paper implements the idea of K-map to reduce the expression except that it could solve ‘n’ variables The common way of representing the Boolean function.
  • Digital Electronics

    Digital Electronics

    LECTURE NOTES ON DIGITAL ELECTRONICS 4th semester Branch-Electrical Engineering DEPT. OF ELECTRONICS AND TELECOMMUNICATIONS ENGINEERING PADMASHREE KRUTARTHA ACHARYA COLLEGE OF ENGINEERING DISTRICT-BARGARH, PIN 768028 MODULE - 1 Number Systems Understanding Decimal Numbers ° Decimal numbers are made of decimal digits: (0,1,2,3,4,5,6,7,8,9) ° Decimal number representation: • 8653 = 8x103 + 6x102 + 5x101 + 3x100 ° What about fractions? • 97654.35 = 9x104 + 7x103 + 6x102 + 5x101 + 4x100 + 3x10-1 + 5x10-2 • In formal notation -> (97654.35)10 ° Why do we use 10 digits? Understanding Binary Numbers ° Binary numbers are made of binary digits (bits): • 0 and 1 ° How many items does an binary number represent? 3 2 + 1 + 0 • (1011)2 = 1x2 + 0x2 1x2 1x2 = (11)10 ° What about fractions? 2 + 1 + 0 -1 + -2 • (110.10)2 = 1x2 1x2 0x2 + 1x2 0x2 ° Groups of eight bits are called a byte • (11001001) 2 ° Groups of four bits are called a nibble. • (1101) 2 Why Use Binary Numbers? ° Easy to represent 0 and 1 using electrical values. ° Possible to tolerate noise. ° Easy to transmit data ° Easy to build binary circuits. AND Gate 1 0 0 Conversion Between Number Bases Octal(base 8) Decimal(base 10) Binary(base 2) Hexadecimal (base16) ° Learn to convert between bases. ° Conversion demonstrated in next slides Convert an Integer from Decimal to Another Base For each digit position: 1. Divide decimal number by the base (e.g. 2) 2. The remainder is the lowest-order digit 3. Repeat first two steps until no divisor remains. Example for (13)10: Integer Remainder Coefficient Quotient 13/2 = 6 + ½ a0 = 1 6/2 = 3 + 0 a1 = 0 3/2 = 1 + ½ a2 = 1 1/2 = 0 + ½ a3 = 1 Answer (13)10 = (a3 a2 a1 a0)2 = (1101)2 Convert an Fraction from Decimal to Another Base For each digit position: 1.
  • A Simplification Method of Polymorphic Boolean Functions Wenjian Luo and Zhifang Li

    A Simplification Method of Polymorphic Boolean Functions Wenjian Luo and Zhifang Li

    1 A Simplification Method of Polymorphic Boolean Functions Wenjian Luo and Zhifang Li Abstract—Polymorphic circuits are a special kind of circuits adopted [4, 10, 11]. The evolutionary methods could design which possess multiple build-in functions, and these functions are area-efficient polymorphic circuits, but the Evolutionary activated by environment parameters, like temperature, light and Algorithms face the scalability problem. Therefore, only small VDD. The behavior of a polymorphic circuit can be described by scale circuits can be generated. Up to now, “3×4 multiplier / 7 a polymorphic Boolean function. For the first time, this brief presents a simplification method of the polymorphic Boolean bit sorting-net” reported in [4] is the biggest polymorphic function. circuits designed by evolutionary methods. In [12, 13], Sekanina and his colleagues proposed the Poly-BDD and Index Terms—Polymorphic electronics, polymorphic circuit, polymorphic multiplex methods for designing polymorphic polymorphic Boolean function, Karnaugh Map circuits. It is noted that polymorphic multiplex method is firstly proposed in [11], and also adopted in [14], but they are I. INTRODUCTION somewhat different. the In [15], the Poly_Bi_Decomposition ompared with the traditional electronics, the polymorphic method is proposed to synthesize polymorphic circuits. C electronic components possess multiple build-in functions The behavior of a polymorphic circuit can be described by a which are activated by environmental signals. For instance, polymorphic Boolean function. The simplification of a the AND/OR polymorphic logic gate controlled by Boolean function is common, and its importance stems from temperature perform the AND function when the temperature the fact that “the simpler the function is, the easier it is to is 27°C and perform the OR function when the temperature is realize” [16].
  • 2 Combinational Logic Circuits

    2 Combinational Logic Circuits

    www.getmyuni.com 10CS 33 LOGIC DESIGN UNIT – 2 Combinational Logic Circuits Unit – 2 Combinational Logic Circuits Objectives • Understand what are combinational logic circuits • Use the sum-of-products method to design a logic circuit based on a design truth table • Be able to make Karnaugh maps and use them to simplify Boolean expressions Introduction Logic Circuits are categorized into 2 types (based on whether they contain memory or not): • Combinational Logic Circuits o Circuits without memory • Sequential Logic Circuits o Circuits with memory Combinational Logic Circuits The output of combinational logic circuit depends only on the current inputs. A combinational logic circuit block is as shown below: There are two fundamental approaches in logic design. They are: • The Sum-of-Products (SOP) Method – Solution results in an AND-OR or NAND-NAND network Page 1 www.getmyuni.com 10CS 33 LOGIC DESIGN UNIT – 2 Combinational Logic Circuits • The Product-of-Sums (POS) Method – Solution results in an OR-AND or NOR-NOR network We select a simpler circuit because it costs less and is more reliable. The Sum-of-Products (SOP) Method Product term A product term is a conjunction of literals, where each literal is either a Boolean variable or its complement. Examples: A . B A’ . B. C’ A Fundamental product or Minterm For a function of n variables, a product term in which each of the n variables appears once (in uncomplemented or complemented form) is called a fundamental product or minterm Fundamental Products for Two inputs Consider two inputs A and B. The fundamental products or minterms are listed below: Inputs Fundamental products or A B minterms 0 0 m0 = A’ .
  • Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions

    Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions

    128 IEEE TRANSACTIONS ON COMPUTERS, VOL. 70, NO. 1, JANUARY 2021 Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions Vaibhav Vyas , Lucian Jiang-Wei, Peng Zhou, Student Member, IEEE, Xuan Hu , Student Member, IEEE, and Joseph S. Friedman , Senior Member, IEEE Abstract—The development of beyond-CMOS technologies with alternative basis logic functions necessitates the introduction of novel design automation techniques. In particular, recently proposed computing systems based on memristors and bilayer avalanche spin-diodes both provide asymmetric functions as basis logic gates - the implication and inverted-input AND, respectively. This article therefore proposes a method by which Karnaugh maps can be directly applied to systems with asymmetric basis logic functions. A set of identities is defined for these memristor and spintronic logic functions, enabling the formal demonstration of the Karnaugh map method and an explanation of the proposed technique. This method thus, enables the direct minimization of spintronic and memristive logic circuits without translation to conventional Boolean algebra, facilitating the further development of these novel computing paradigms. Preliminary analyses demonstrate that this Karnaugh map minimization approach can provide a 28 percent reduction in step count as compared to previous manual optimization. Index Terms—Boolean algebra, beyond-CMOS computing, asymmetric logic, emerging technologies, memristors, spintronics Ç 1INTRODUCTION MERGING computing technologies provide unconven-
  • Simplifying the Boolean Equation Based on Simulation System Using Karnaugh Mapping Tool in Digital Circuit Design

    Simplifying the Boolean Equation Based on Simulation System Using Karnaugh Mapping Tool in Digital Circuit Design

    Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design Md. Jahidul Islam , Md. Gulzar Hussain, Babe Sultana, Mahmuda Rahman , Md. Saidur Rahman and Muhammad Aminur Rahaman Abstract—In computerized integrated circuits, the Logic (PAL) and Programmable Logic Array (PLA) fundamental principle intends to avoid the multifaceted [1], and here the amount of logic circuits are to be nature of the circuitry by making it as brief as attainable maintained in a minimal form, the production costs and minimize the expenditure. Techniques like Quine- of such devices will be decreased. The K map is McCluskey (QM) and Karnaugh Map (K-Map) are often the graphical procedure to optimize Boolean function used approaches of simplifying Boolean functions. This study presents a recreation framework of simplification throughout the format of a minimal SOP form. Logic of the Boolean capacities by the utilize of the K- Gate-wise, these observations resulted such a two- Map definition for beginner-level learners. It uses the tier minimal system. It’s used mostly for many small algebraic expression of the Boolean function to decrease design problems. It is obvious that several larger mod- the number of terms, generates a circuit, and does els are carrying out using various computer method not use any redundant sets. In this way, it gets to be implementations, and so we can obtain a pretty good competent to deal with lots of parameters and minimize insight in to digital logic gate circuit after learning K the computational cost. The result of the assessment is performed in this paper by contrasting it with the C- map.
  • A Thesis Submitted in Conformity with the Requirements for the Degree Of

    A Thesis Submitted in Conformity with the Requirements for the Degree Of

    SECRET SHARING FOR COLOR IMAGES by Mohsen Heidarinejad A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto Copyright © 2008 by Mohsen Heidarinejad Library and Bibliotheque et 1*1 Archives Canada Archives Canada Published Heritage Direction du Branch Patrimoine de I'edition 395 Wellington Street 395, rue Wellington Ottawa ON K1A0N4 Ottawa ON K1A0N4 Canada Canada Your file Votre reference ISBN: 978-0-494-44991-2 Our file Notre reference ISBN: 978-0-494-44991-2 NOTICE: AVIS: The author has granted a non­ L'auteur a accorde une licence non exclusive exclusive license allowing Library permettant a la Bibliotheque et Archives and Archives Canada to reproduce, Canada de reproduire, publier, archiver, publish, archive, preserve, conserve, sauvegarder, conserver, transmettre au public communicate to the public by par telecommunication ou par Plntemet, prefer, telecommunication or on the Internet, distribuer et vendre des theses partout dans loan, distribute and sell theses le monde, a des fins commerciales ou autres, worldwide, for commercial or non­ sur support microforme, papier, electronique commercial purposes, in microform, et/ou autres formats. paper, electronic and/or any other formats. The author retains copyright L'auteur conserve la propriete du droit d'auteur ownership and moral rights in et des droits moraux qui protege cette these. this thesis. Neither the thesis Ni la these ni des extraits substantiels de nor substantial extracts from it celle-ci ne doivent etre imprimes ou autrement may be printed or otherwise reproduits sans son autorisation. reproduced without the author's permission.