Chapter 11

Differential Circuits ______

11.0 Introduction

Differential amplifier or diff-amp is a multi- amplifier. It is the fundamental building block of analog circuit. It is virtually formed the differential amplifier of the input part of an . It is used to provide high voltage gain and high common mode rejection ratio. It has other characteristics such as very high input impedance, very low offset voltage and very low input bias current.

Differential amplifier can operate in two modes namely common mode and differential mode. Each type will have its output response illustrated in Fig. 11.1. Common mode type would result zero output and differential mode type would result high output. This shall mean the amplifier has high common mode rejection ratio.

Figure 11.1: Differential amplifier shows differential inputs and common-mode inputs

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If two input voltage are equal, the differential amplifier gives output voltage of almost zero volt. If two input voltages are not equal, the differential amplifier gives a high output voltage.

Let’s define differential input voltage V in(d) as V in(d) = V in1 – V in2 and + Vin 1 Vin 2 common-mode input voltage V in(c) = . From these equations, input 2 voltage one and two are respectively equal to

Vin )d( Vin1 = V + (11.1) in )c( 2 and

Vin )d( Vin2 = V − (11.2) in )c( 2

The input voltage represented by common-mode voltage and differential voltage is shown in Fig. 11.2.

Figure 11.2: Small differential and common-mode inputs of a differential amplifier

Let V out1 be the output voltage due to input voltage V in1 and V out2 be the output voltage due to V in2 . The differential-mode output voltage V out(d) be defined as + Vout 1 Vout 2 Vout(d) = V out1 – V out2 and common-mode output is defined V out(c) = . 2 Combining these equations yield V out1 as V out2 respectively as equal to

Vout )d( Vout1 = V + (11.3) out )c( 2

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Vout )d( Vout2 = V − (11.4) out )c( 2

Let A V1 = V out1 /V in1 be the gain of differential amplifier due to input V in1 only and A V2 V out2/V in2 due to input V in2 only. Then from superposition theorem, the output voltage V out is equal to V out = A V1 Vin1 + A V2 Vin2 . After substituting V in1 and V in2 from equation (11.1) and (11.2), the output voltage V out is equal to

 V   V   + in )d(  +  − in )d(  Vout = A V1 Vin )c(  A V2 Vin )c(  (11.5)  2   2 

Equation (11.5) is also equal to V out = A V(dm) Vin(d) +A V(cm) Vin(c) , where the differential voltage gain is A V(dm) = (A V1 – A V2 )/2 and common-mode voltage gain is A V(cm) = (A V1 + A V2 ).

The ability of a differential amplifier to reject common-mode signal depends on its common-mode rejection ratio CMRR, which is defined as

A CMRR = V dm( ) (11.6) A V cm( )

From V out = A V(dm) Vin(d) +A V(cm) Vin(c) , output voltage V out is equal to

 1  Vout = A V + V  (11.7) V dm( )  in )d( CMRR in )c( 

Equation (11.7) clearly indicates that for large CMRR value, the effect of common-mode input is not significant to the output voltage.

Example 11.1 A differential amplifier shown in figure below has differential gain of 2,500 and a CMRR of 30,000. In part A of the figure, a single-ended input of signal 500 µV rms is applied. At the same time a 1V, 50Hz interference signal appears on both inputs as a result of radiated pick-up from ac power system.

In part B of the figure, differential input signal of 500 µV rms each is applied to the inputs. The common-mode interference is the same as in part A.

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1. Determine the common-mode gain. 2. Express CMRR in dB. 3. Determine the rms output signal for part A and B. 4. Determine the rms interface voltage on the output.

Solution 1. The common-mode gain V cm = A V(dm) /CMRR= 2,500/30,000 = 0.083. 2. CMRR = 30,000. Also 20log(30,000) = 89.5dB. 3. The difference input for part A is 500µV - 0V = 500 µV.

Thus, the rms output is A V(d) x 500 µV = 2,500 x 500 µV = 1.25Vrms The difference input for part B is 500 µV - (-500 µV) = 1mV Thus, the rms output is A V(d) x 1mV = 2,500 x 1mV = 2.5Vrms. 4. Since the common-mode gain A cm is 0.083 (from answer 1), then output voltage of interface from 1V 50Hz ac pick-up is A cm x 1V = 0.083V.

11.1 Bipolar Junction Transistor Differential Amplifier

Consider an emitter coupled bipolar junction transistor differential amplifier shown in Fig. 11.3. Assuming that the physical parameters of transistor Q 1 and Q2 are closed to identical. With the modern fabrication technique and fabricating the transistor Q 1 and Q 2 in close approximity in the same wafer slide, close to identical physical parameters for both are achievable. - 296 - 11 Differential Amplifier Circuits

Figure 11.3: A bipolar junction transistor differential amplifier

11.1.1 dc Characteristics

Using Kirchhoff’s voltage law, the voltage at emitter V E1 and V E2 , of the amplifier is V in1 - V BE1 = V in2 - V BE2 . From the theory of semiconductor physics, =[ − ] the collector current I C of a bipolar transistor is equal to IIVVC Sexp( BE / T ) 1 , where I S is the reverse saturation current, which is design dependent. V T is the thermal voltage, which has value approximately equal to 25.0mV at temperature 300K. Under normal operating conditions the term exp(V BE /V T) >> 1, thus, the  I  =  C  base-to-emitter voltage V BE is equal to VVBE1 T ln . The differential input  IS  voltage V in(d) = (V in1 - V in2 ) shall then be equal to

 I I   C1 ⋅ S2  Vin(d) = VT ln (11.8)  IS1 I C2 

For identical transistor pair reverse saturation current is I S1 = I S2 and V in(d) =  I   C1  VT ln   . The ratio of collector current of transistor Q 1 and transistor Q 2 is  IC2  equal to

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I  V  C1 = exp  in() d  (11.9) I C2  VT 

+ IIC1 C2 The emitter current is I E = I E1 + I E2 , which is also equal to I E = α . Using this equation and equation (11.9), the collector current I C1 and I C2 of the transistor are separately derived shown in equation (11.10) and (11.11).

αI I = E (11.10) C1  V  1+ exp  − in() d   VT 

αI I = E (11.11) C2  V  1+ exp  in() d   VT 

The current transfer characteristic curve showing the plot of collector current of transitor Q 1 and Q 2 versus the differential input voltage V in(d) is shown in Fig. 11.4.

Figure 11.4: The current transfer characteristic curve of a bipolar junction transistor differential amplifier

From the characteristic curve, once can notice that for several V T values such as Vin(d) > 4V T, either I C1 >> I C2 or I C1 << I C2 shall be obtained. For V in(d) < 2V T, the collector current is almost linear.

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At the output side, the output voltage are V out1 = V CC - I C1 RC and V out2 = VCC - I C2 RC respectively. The differential output voltage V out(d) shall be V out(d) = RC(I C2 - I C1 ). The differential output voltage V out(d) also equal to

     1 1  = α − VIRout() d E C   (11.12) Vin() d  Vin() d  1+ exp 1+exp  −    VT  VT  

 − V  = α  in() d  This equation is also equal to VIRout() d E C tanh since I C2 =  2VT  ( +) =( −) ( − + ) 1/ 1 exp(VVVVVVVVindT()()()() / exp ind / 2 T /exp( ind / 2 T )exp( ind / 2 T and I C1 ( + −) =( ) ( + − ) =1/ 1 exp(VVVVVVVVind()()()() / T exp ind / 2 T /exp( ind / 2 T )exp( ind / 2 T . The transfer characteristic of the output shall be as shown in Fig. 11.5.

Figure 11.5: Output transfer characteristic curve of a BJT differential amplifier

From the analysis, one can see that to increase the range of input voltage so that it has more linear operating region, a seperate emitter which is termed as emitter-degeneration resistor , can be added to each transistor instead of sharing emitter resistor. This is becasue emitter current of each transistor will be double instead of half. This configuration will also improve the bandwidth of the amplifier.

11.1.2 Differential Mode

The differential input circuit of the amplifier is shown in Fig. 11.6.

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Figure 11.6: Differential input circuit of an emitter couple BJT differential amplifier

Asssuming identical transistor, the increase of emitter voltage by V in1 i.e V in(d) /2 is compensated by the decrease of same value of emitter voltage by V in2 i.e. – Vin(d) /2. Thus, the voltage at emitter E 1 and E 2 remain unchange. Thus, the emitter current I e is approximately zero. As the result the potential at emitter is regards as same potential as ground level and R E is treated as short.

Based on the analysis, the ac differential input circuit of the amplifier can be splitted into two half circuits as one is shown in Fig. 11.7.

Figure 11.7: ac differential mode half circuit of an emitter coupled BJT differential amplifier - 300 - 11 Differential Amplifier Circuits

The corresponding ac circuit of the half circuit amplifier is shown in Fig. 11.8.

Figure 11.8: ac circuit of circuit shown in Fig. 11.7

The output voltage is equal to

V V out )d( = −g ()R r|| in )d( (11.13) 2 m C o 2

Thus, the differential-mode gain A V(dm) is equal to

V = out )d( = − () A V dm( ) g m R C r|| o (11.14) Vin )d(

The differential input impedance R in(d) can be obtained from equation V in (d)/2 = ib1 rπ. Thus, the differential input impedance is equal to

Rin(d) = 2r π (11.15)

The differential output impedance R out(dm) can be obtained from equation Vout(dm) /2 = iC(r o||R C). Thus, the differential output impedance R out(dm) is equal to

Rout(d) = 2(ro||R C) (11.16)

11.1.2 Common Mode

The common input circuit of the amplifier is shown in Fig. 11.9 and its corresponding half circuit is shown in Fig. 11.10. Since emitter voltage at emitter E 1 and E 2 is changing, therefore, the emitter resistance of the half circuit should be 2R E instead of R E after splitting into two half circuits. - 301 - 11 Differential Amplifier Circuits

Figure 11.9: Common input circuit of an emitter couple BJT differential amplifier

Figure 11.10: ac common mode half circuit of an emitter coupled BJT differential amplifier

The corresponding ac circuit of the half circuit amplifier is shown in Fig. 11.11.

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Figure 11.11: ac circuit of circuit shown in Fig. 11.10

At input side, V in(c) = ib1 rπ + ib1 (β+1)2R E. Thus, the common-mode input impedance R in(c) is equal to

Rin(c) = [r π + ( β +1)2R E] (11.17)

The common-mode output impedance R out(c) is equal to (R C||r o).

The output common-mode voltage V out(c) = -βib1 (R C||r o). The common- mode gain A V(cm) is equal to

V βi (R r|| ) g R r|| A = out )c( = − 1b C o = − m C o (11.18) V(cm) []+ β + + + β Vin )c( i 1b rπ 2R E ( )1 1 2g m R E 1( /1 )

11.1.3 Common Mode Rejection Ratio

The common-mode rejection ratio of the emitter coupled BJT differential amplifier is equal to CMRR = A V(dm) /AV(cm) . Thus from equation (11.14) and (11.18), common-mode rejection ration is

− g (R r|| ) CMRR = m C o ⋅[]1+ 2g R 1( + /1 β) =[1+ 2g R 1( + /1 β)] − m E m E (R C r|| o ) (11.19)

For large beta value, the common rejection ratio is approximately equal to = [ + ] CMRR 1 2g m R E . Thus, one can see for high common rejection ratio CMRR,

- 303 - 11 Differential Amplifier Circuits the differential amplfier should be designed with high emitter resistance and high transconductance values.

11.2 JFET Differential Amplifier

A JFET differential amplifier is shown in Fig. 11.12 and its ac equivalent circuit is shown in Fig. 11.4. Since JFET has very high impedance, it satisfies the high impedance and low input bias current requirements for the differential amplifier. Theoretically, the M 1 and M 2 should have same physical parameters. This can be achieved via modern fabrication technique. This shall also mean that close to zero offset voltage is also achievable.

Figure 11.12: A JFET differential amplifier

11.2.1 dc Characteristics

Using Kirchhoff’s voltage law, the voltage at source of the amplifier is -Vin1 + 2  V   − GS  VGS1 + V in2 – V GS2 = 0. Drain current of JFET is ID = I DSS 1  .  VGS (off ) 

VGS 1 I D1 VGS 2 I D2 Therefore, = 1− and = 1− . Since – V in1 + V in2 = V GS2 – VGS (off ) I DSS VGS (off ) I DSS

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I I D2 − D1 VGS1 , V in1 – V in2 = VGS (off ) VGS (off ) . Since V in1 – V in2 = V in(d) , this I DSS I DSS equation becomes

V I I in )d( = D2 − D1 (11.20) VGS (off ) I DSS I DSS

IS current is equal to the sum of ID1 and ID2. Thus, IS is IS = ID1 + ID2. Substituting this equation into equation (11.20) and solve the resultant quadratic, it yields drain current one and two, which are

/1 2  2 2  I I  V   I   V   I  S + S  in )d(   DSS  −  in )d(   DSS   ID1 = 2    (11.21) 2 2  V  I  V  I   GS (off )   S   GS (off )   S   and

2/1  2 2  I I  V   I   V   I  S − S  in )d(   DSS  −  in )d(   DSS   ID2 = 2    (11.22) 2 2  V  I  V  I   GS (off )   S   GS (off )   S  

The equation for drain current is only true for sum of the drain currents less than IDSS current. The plot of drain current versu input differential voltage V in(d) is shown in Fig. 11.13.

Figure 11.13: The current transfer characteristic curve of a JFET differential amplifier

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The output voltage V out1 and V out2 are respectively equal to V DD – I D1 RD and V DD – I D2 RD. The differential output voltage V out(d) = V out1 – v out2 = R D(I D2 – I D1 ). Substuting equation (11.21) and (11.22) yields the differential output voltage Vout(d) as

2/1  2 2  I R  I   V   I  − S D   DSS  −  in )d(   DSS   Vout(d) = Vin )d( 2    (11.23) V  I  V  I  GS (off )   S   GS (off )   S  

11.2.1 Differential Mode

The differential input of the JFET differential amplifier can be analyzed like the way how the anlysis is done for BJT counterpart. The half circuit of the amplifier is shown in Fig. 11.14.

Figure 11.14: ac differential mode half circuit of a JFET differential amplifier

The corresponding ac circuit of the half circuit amplifier is shown in Fig. 11.15.

Figure 11.15: ac circuit of circuit shown in Fig. 11.14 - 306 - 11 Differential Amplifier Circuits

The output voltage V out(d) /2 is equal to

V V out )d( = −g ()R r|| in )d( (11.24) 2 m D o 2

Thus, the differential-mode gain A V(dm) is equal to

V = out )d( = − () A V dm( ) g m R D r|| 0 (11.25) Vin )d(

Normal R D << r o then the differential-mode gain A V(dm) is V = out )d( = − A V dm( ) g m R D . Vin )d(

11.2.2 Common Mode

The common input circuit of the amplifier is shown in Fig. 11.16 and its corresponding half circuit is shown in Fig. 11.17. Since source voltage at emitter S 1 and S 2 is changing, therefore, the emitter resistance of the half circuit should be 2R D instead of R D after splitting into two half circuits.

Figure 11.16: Common input circuit of a JFET differential amplifier - 307 - 11 Differential Amplifier Circuits

Figure 11.17: ac common mode half circuit of a JFET differential amplifier

The corresponding ac circuit of the half circuit amplifier is shown in Fig. 11.18.

Figure 11.18: ac circuit of circuit shown in Fig. 11.17

At input side, common-mode input voltage is V in(c) = Vgs1 + gmVgs12R S. Thus,

Vin )c( the common-mode input impedance R in(c) = is equal to I gate

+ Vgs g m 2Vgs R S Rin(c) = = R in(gate) (1 + 2g mRS) (11.17) I gate

- 308 - 11 Differential Amplifier Circuits where V gs /I gate = R in(gate) . Depending on the value of R in(gate) that can be a infinite value for very small I gate current.

The output common-mode voltage V out(c) = -gmVgs1 (R D||r o). The common-

Vout )d( mode gain A V(cm) = is equal to Vin )d(

g V (R r|| ) g (R r|| ) A = − m gs 1 D o = − m D o (1126) V(cm) + + Vgs 1 2g m Vgs 1R S 1 2g m R S

11.2.3 Common Mode Rejection Ratio

The common-mode rejection ratio of the JFET differential amplifier is equal to CMRR = A V(dm) /AV(cm) . Thus from equation (11.25) and (11.26), common-mode rejection ration is

− g (R r|| ) CMRR = m D o ⋅[]1+ 2g R = [1+ 2g R ] − m S m S g m (R D r|| o ) (11.27)

11.3 MOSFET Differential Amplifier

A JFET differential amplifier is shown in Fig. 11.19. Using Kirchhoff’s voltage law, the voltage at source of the amplifier is -Vin1 + V GS1 + V in2 – V GS2 = 0. µ n Cox W 2 2 Drain current of MOSFET is I D = ()V − V = K (V − V ) , where K n 2L GS tn n GS tn µ n Cox W I D = . This implies that V GS = + V . From equation -Vin1 + V GS1 + 2L K tn Vin2 – V GS2 = 0. The differential input voltage V in(d) is

I D2 I D1 I D2 I D1 Vin(d) = V in1 – V in2 = + V - − V = − K tn K tn K K

(11.28)

From Kirchhoff’s current law, I S = I D1 + I D2 and substituting V in(d) . The drain currents are dound to be

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2/1 I  V  (V )2/ 2  S +  in )d(  − in )d( ID1 = 2K n IS  1  (11.29) 2  2  I( S 2/ K n )  and

2/1 I  V  (V )2/ 2  S −  in )d(  − in )d( ID1 = 2K n IS  1  (11.30) 2  2  I( S 2/ K n ) 

Figure 11.19: A MOSFET differential amplifier

The output voltage V out1 = V DD – I D1 RD and V out2 = V DD – I D2 RD. The differential output voltage is V out(d) = V out1 – V out2 = R D(I D2 – I D1 ). Substituting equation (11.29) and (11.30) into this equation yields the differential output voltage Vout(d) equal to

2/1  K n IS  Vout(d) = − R   V (11.31) D  2  in )d(

Employing the method used in JFET differential amplifier analysis, the common-mode gain A V(cm) and differential-mode gain A V(dm) are found to be

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g (R r|| ) A = − m D o and A = A − g R respectively. Subsequently, the V(cm) + V(dm) V dm( ) m D 1 2g m R S [ + ] common-mode rejection ratio CMRR is found to be CMRR = 1 2g m R S .

11.3.1 Active Load MOSFET Differential Amplifier

Let’s consider an active load MOSFET differential amplifier shown in Fig. 11.20. MOSFET M 1 and M 2 formed the differential pair. They have same design parameters. MOSFET M 5 is current sink, which provides the bias current to the amplifier. MOSFET M 3 and M 4 form a , which is assumed to have same design parameters.

From Kirchhoff’s current law, current I D5 is equal to the sum of current I D1 and I D2 . If the input voltage V in1 and V in2 are equal then current I D1 = I D2 = I D3 = ID4 . This shall mean the output current I out is equal to zero. Thus, output voltage Vout is equal to zero.

If the input voltage V in1 is greater than V in2, which V in1 > V in2, then current ID1 , I D3 , and I D4 are equal. This shall mean current I D1 is greater than I D2 . Therefore, at output node current is I D4 = I D2 + I out . This result implies that the output voltage is a positive value.

If the input voltage V in2 is greater than V in1, which V in2 > V in1, then current I D1 , ID3 , and I D4 are equal. This shall mean current I D1 is less than I D2 . This implies that current I D2 is equal to the sum of current I D4 and I out . i.e. I D2 = I D4 + I out .

The differential input voltage is V in(d) = (V in1 –Vin2). For each input of the differential pair would see a change of (V in1 – V in2)/2 = V in(d)/2. Thus, a change in input V in(d)/2 will result a change of g mVin(d)/2 for the drain current of MOSFET M 1 and M 2. The ac equivalent circuit of output side is shown in Fig. 11.21.

The differential voltage gain A V(dm) of the differential amplifier is found to be

V 1 A = out = − g( + g )( r r|| || R ) (11.32) V(dm) − m2 m4 O2 O4 L Vin 2 Vin 1 2

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Figure 11.20: An active load MOSFET differential amplifier

From Kirchhoff’s voltage law, output voltage is V out = - (g m2 Vin(d)/2 +g m4 Vin(d) /2)(r o1||r o4||R L). Therefore, the differential voltage gain A V(dm) is Av(dm) V 1 = out = − g( + g )( r r|| || R ) . − m2 m4 O2 O4 L Vin 2 Vin 1 2

In normal circumstance transcondctance g m2 is equal to transconductance = − gm4 . i.e. g m2 = g m4 . Thus, the differential gain is A V dm( ) g m2 r( O2 r|| O4 || R L ). Since the output impedance of the MOSFET r o4 and r o2 are large, it can be assumed that they are equal. If the load R L is not connected then the differential gain

g m2 equation A = − r , where r o4 = r o2 = r o. The equation demonstrates that V dm( ) 2 O the differential gain is a large constant for a given MOSFET in active load configuration.

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Figure 11.21: ac model of the half circuit of an active load MOSFET differential amplifier

11.4 BiCMOS Differential Amplifier

The differential mode gain of a BJT differential amplifier is equal to A V(dm) = - I 2V V = − C ⋅ A = − A gmro. It is also equal to A V dm( ) . This result shows that the 2VT IC VT gain is a constant value. For a typical Early voltage V A of 50V and thermal voltage V T of 25mV, the gain is – 2,000V/V. Thus, lowering the collector current I C will improve input impedance but reducing g m, thus, scarifying

g m bandwidth because the unity gain frequency f T of BJT is . The input 2π(Cµ + Cπ ) β VT impedance of the BJT is equal to rπ = = β . g m IC

The differential mode gain A V(dm) of a MOSFET differential amplifier is 2V − ⋅ M = − 2K equal to A V(dm ) = -gmro = 2KI D 2VM , which shall mean gain is I D I D inversely proportional to I D . Since the thermal voltage V M of MOSFET is much lower than the thermal voltage of BJT differential amplifier, the differential gain A V(dm) of BJT is much higher than differential gain of MOSFET differential amplifier. If drain current I D is lower, the bandwidth of the amplifier reduces because the transconductance g m is proportional to I D and the unity gain frequency fT is proportional to transconductance g m. The input impedance of the MOSFET has infinite value. Combining the high gain of BJT and infinite impedance of MOSFET will lead to BiCMOS differential amplifier design that

- 313 - 11 Differential Amplifier Circuits can be a basic configuration, cascade configuration, active load configuration, etc. The circuit of active load BiCMOS differential amplifier is shown in Fig. 11.22.

Figure 11.22: An active load BiCMOS differential amplifier

The differential voltage gain A V(dm) of the BiCMOS differential amplifier is equal to V 1 A = out = − g( + g )( r r|| || R ) (11.33) v(dm) − m2 m4 O2 O4 L Vin 2 Vin 1 2

2V 2V 2V 2V = M = M = M = M whereby g m2 , g m4 , rO4 , and rO2 . In normal I D5 I D5 I D5 I D5 circumstance g m2 = g m4 . Thus, the differential gain is AV(dm) = V out = −g r( r|| || R ) . − m2 O2 O4 L Vin 2 Vin 1

Example 11.2

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A BiCMOS differential amplifier as shown in Fig. 11.21 has I D5 = 10 µA, identical BJT with V A = 50V and β = 40, identical MOSFET with V M = 20V, K 2 = 25 µA/V , W = 30 µm, L = 10 µm, V GS = 1.0V, V DD = 10 V and V SS = 10V Determine the differential gain of the amplifier without the load R L and V bias voltage.

Solution The output impedance of the BJT is 2V A/I D5 = 2x50/10 µA = 4MΩ. The output impedance of the MOSFET is 2V M/I D5 = 2x20/10 µA = 10MΩ. The overall output impedance R O of differential amplifier is 4MΩ||10MΩ = 2.86MΩ.

= µ 2 µ The transconductance g m2 of MOSFET is 2KI D5 2x25 A / V 10x A = 22.36 µA/V.

Thus, the differential voltage gain A V(dm) is -gm2 RO = - 22.36x2.86MΩ = - 63.9.

The gate-to-source voltage of MOSFET M 5 is 1.5V. The current I D5 is ID5 = µ COX n  W  2 -5 2  ()V − V = 2.5x10 x3/2(VGS – 1.0) = 10 µA. This implies that V GS 2  L  GS tn is equal to 1.51V.

Since V S = - 10V and V GS = V bias - V S, V bias is equal to -8.49 V.

11.5 Differential Amplifier

Let’s discuss one type of cascade differential amplifier, which is bipolar junction transistor type.

Consider a BJT cascode differential amplifier shown in Fig. 11.23. This configuration is usually to improve the output resistance for the gain and frequency response. Transistor Q 5 and Q 6 are connected as amplifier.

The half circuit of the amplifier is shown in Fig. 11.24. The ac circuit of the half circuit amplifier is shown in Fig. 11.25.

From the ac circuit r π6/( β+1) is parallel to r o2 i.e. r π6/( β+1) || r o2 . All r o2 , r o4 , and r o6 are the same because the collector current flows in them are the same r o. The transconductance g m2 , g m4 , and g m6 should be equal to g m. - 315 - 11 Differential Amplifier Circuits

Figure 11.23: A BJT cascode differential amplifier

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Figure 11.24: Half circuit of a BJT cascade differential amplifier − The output voltage is equal to V out = g m Vin )d( r( o || R L ) . Thus, the differential- − mode gain is equal to A V(dm) = g m r( o || R L ) .

Figure 11.25: ac circuit of the half circuit differential amplifier

11.6 Effect of Device Mismatch

An ideal BJT differential amplifier has identical transistor pair and bias . This shall mean that if the differential input voltage V in(d) is zero then the differential output voltage V out(d) should be zero. In reality, there should have some mismatch in the bias resistor and the transistor pair should have offset difference.

The offset voltage of a differential amplifier Vos is defined the input differential voltage V in(d) required to drive the output differential voltage V out(d) to zero voltage. From Fig. 11.2, the offset voltage V os shall be V os = V be1 - V be2 , which is also equal to

 I I   C1 ⋅ S2  Vos = VT ln (11.34)  IS1 I C2 

Offset voltage can also be expressed as the change of collector resistance and reverse saturation current of the transistors in which it follows equation (11.35).

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 ∆R ∆I  −C − S  Vos = VT (11.35)  R C IS 

RR+ II+ where ∆R = R - R , ∆I = I - I , R = C1 C2 , and I = SS1 2 . C C1 C2 S S1 S2 C 2 C 2

11.7 Frequency Response of Differential Amplifier

If the base resistor R B is added to the bipolar junction transistor differential amplifier circuit shown in Fig. 11.2, then the differential mode voltage gain

rπ − g R AV(dm) shall be A v(dm) = m C + . From the earlier analysis of high rπ R B frequency response of the common-emitter configuration, the differential mode voltage gain transfer function is A v(dm) (s) =

rπ 1 1 − g R ⋅ ⋅ , where C is Miller's m C + + ()+ + + M rπ R B 1 s rπ || R B (Cπ CM ) 1 sR C (Cµ Cce ) capacitance, which is equal to C µ(1 + g mRC) and C µ is the collector-to-base capacitance. From the function, it shows there are two critical frequency fH and 1 f determined by 1 and . However, due to H1 π[]+ 2 rπ || R (Cπ C ) π[]+ B M 2 RCCB()µ ce very small value of C ce and C µ, and small R C, the critical frequency is extremely high, which can be infinite. Since there is no coupling capacitor in the circuit, the bandwidth different mode gain shall be from zero Hz frequency to fH. The frequency response is shown in Fig. 11.26.

The frequency response for the common mode voltage gain of the amplifier can be analyzed using small signal equivalent half circuit shown in Fig. 11.27 and the emitter is replaced with a capacitor C o and a resistor R o.

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Figure 11.26: Frequency response of differential mode gain

Figure 11.27: ac equivalent circuit of the common mode differential amplifier

The common mode output voltage V out(c) is -gmVπRC. At base-to-emitter loop, from Kirchhoff’s voltage law, it produces V in(c)(s) =  V  R   V  1   π  B  + +  π +    Vπ  2g m Vπ R o ||  or V in(c)(s) =  rπ 2/  2   rπ 2/  sC o    + β   R B 1 R o Vπ  +1+ 2   . Substituting V π from V (s) equation, the   +  out(c)  rπ  rπ 1 sR o Co  commom mode voltage gain A V(cm) (s) shall be

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− + gm R C()1 sR o C o AV(cm) (s) = (11.36)  R  2() 1+ β R  + B ()+ + o 1 1 sRo C o  rπ r π

The gain equation shows that there is a zero and a pole. From the zero, the ( π ) critical frequency fZ shall be 1/ 2 RCo o . The zero also explains why C o parallel with R o. At low frequency, C o is a open circuit and the common signal see impedance R o. As frequency increase, the impedance C o decreases and R o becomes bypassed. Since the current source can has very high resistance R o and small capacitance C o, the critical frequency can be very small. Soon the operating frequency is more than the critical frequency, the gain of the amplifier increases at the rate 20 dB/decade or 6 dB/octave. Figure 11.28 illustrates the freqeuncy response.

Figure 11.28: Frequency response of the common mode gain

From equation (11.36), the critical frequency of the pole is

1 f = P π (11.37) 2 RCeq o

 R   + B  R o 1  rπ  where R = . The denominator of this resistance R is very eq R 2() 1+ β R eq 1+B + o rπr π large due to (1 + β)R o term. This shall mean that R eq is very small. Therefore, the critical frequency is very high. - 320 - 11 Differential Amplifier Circuits

If the ratio of the frequency response for differential mode gain and common mode gain is plotted, then the frequency response of common mode rejection ratio shall be obtained and it is shown in Fig. 11.29.

Figure 11.29: Frequency response of the common mode rejection ratio

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Exercises

11.1. An active load emitter coupled BJT differential amplifier is shown in the Fig.

i. Draw differential half circuit for the amplifier. − ii. Show that the differential-mode gain A V(dm) = g m r( o2 r|| o4 || R L ).

iii. If r o2 = r o4 = r o, prove that the differential-mode gain is equal to V = − A A V dm( ) . 2VT iv. Calculate the room temperature differential-mode gain of the amplifier if the Early voltage of the transistor is 80V and express the result in decibel. v. Comment the result.

11.2. An n-channel MOSFET differential amplifier is shown below. Both 2 MOSFETs have aspect ratio W/L = 25 µm/1.0 µm, µnCox = 50 µA/V , threshold voltage V T = 0.6V, and V DD = 3.0V. You may use equation I D = WCµ 2 =n ox ()VV − for calculation and assume both MOSFET's have 2L GST same design parameters. - 322 - 11 Differential Amplifier Circuits

R / 2 − D i. Prove that the common mode gain of the amplifier is + . 1/() 2gm R S ii. What is the common mode input voltage V in1 = V in2 for the voltage drop across resistor R S to be 0.6V? iii. What should be the value of resistor R S for maintaining 0.6V voltage drops across it?

11.3. An n-channel MOSFET differential amplifier is show below has common R / 2 − D mode gain follow expression + . Both MOSFETs have 1/() 2gm R S 2 aspect ratio W/L = 25 µm/1.0 µm, µnCox = 50 µA/V , threshold voltage V T = 0.6V, R S = 600 Ω, and V DD = 3.0V. You may use equation I D = WCµ 2 =n ox ()VV − for calculation and assume both MOSFET's have 2L GST same design parameters.

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− i. Prove that the differential mode gain of the amplifier is gm R D . ii. Derive the equation for transconductance g m. iii. Derive the formula for the common rejection ratio for the amplifier. State a way to improve this parameter. iv. Calculate the common rejection ratio of this amplifier and express the result in decibel.

11.4. The parameters of the emitter-coupled pair BJT differential amplifier are β = 100, R E = 50 k Ω, I E = 1mA, V CC = 15V, R C = 10 k Ω .

i. Calculate the dc collector current of V in(d) = 5mV. ii. Calculate the CMRR of the amplifier.

11.5. The design of JFET differential amplifier is shown in the Fig. with one input terminal is grounded. The dc biasing current I S = 10mA, V DD = – VSS = 15V. The JFETs are identical and have V GS(off) = - 4.0V and I DSS = 20mA. A small signal voltage of A 1 = -10 is required. Calculate the design values of A V(dm) , A V(cm) , and CMRR.

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11.6. Calculate the differential gain of the given MOSFET amplifier circuit -5 2 shown in the in figure. Given that V bias = - 3.5V, µnCox = 5.2x10 A/V , -5 2 µpCox = 2.1x10 A/V , V tn = 0.7V, V tp = - 0.7V, (W/L) 1,2 = 40, (W/L) 3,4 = 20, (W/L) 5 = 40, (1/ λ)1,2 = 0.01, (1/ λ)3,4 = 0.02, and R L = 5.0kΩ.

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Bibliography

1. Jacob Millman and Arvin Grabel, " Microelectronics ", second edition, McGraw-Hill International Editions, 1987. 2. Muhammad H. Rashid, " Microelectronic Circuits: Analysis and Design ", PWS Publishing Company, 1999. 3. Robert T. Paynter, " Electronic Devices and Circuits ", fifth edition, McGraw-Hill, 1997. 4. Adel S. Sedra and Kenneth C. Smith, "Microelectronic Circuits ", fourth edition, Oxford University Press, 1998. 5. Theodore F. Bogart Jr., Jeffrey S. Beasley, and Guillermo Rico, “Electronic Devices and Circuit ”, sixth edition, Prentice Hall, 2004.

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