INFO 51 APPEARS QUARTERLY | JULY 2017

Inside: your HiPEAC Jobs poster

Team Europe: A workforce for the digital age

Martin Kersten’s forgetful databases

Made in Croatia: the world’s fastest electric car contents

4 12 15 Digital skills for a ‘Data will rot away like Team Europe. competitive Europe everything in nature’ Getting the brains to power the digital revolution

3 Welcome 26 Innovation Europe Koen De Bosschere The Heterogeneous Hardware and Software Alliance 4 Policy corner Karim Djemame and Oliver Barreto Digital skills for a competitive Europe 28 Peac performance Heidi Cigan Parallelizing Python codes using the superscalar paradigm 12 HiPEAC voices ‘Data will rot away like everything in nature’ Rosa Badia Martin Kersten 30 Technology opinion Neuromorphic Computing: low-power systems, 14 HiPEAC Jobs the brainy way Trends in computing systems jobs Kemal Delic and Dave Penkler Xavier Salazar and Anna Molinet 31 Technology entrepreneurship 15 Recruitment special Keep the revolution going Team Europe: Getting the brains to power the digital revolution Colin Adams Sabri Pllana, Marisa Gil, Dionisios Pnevmatikatos, 33 Industry focus Alexey Cheptsov, Marc Gonzalez Vidal, Bev Bachmayer, Cache-aware Roofline Model in Intel® Advisor Graham Mudd, Angela Bradfield, Meenakshi Ravindran Leonel Sousa, Aleksandar Ilić and Frederico Pratas and Karon Davis 35 SME snapshot 22 Inside the box Rimac Automobili: The drive to succeed Well hello, AXIOM board! Aco Momčilović, Matija Gracin and Marta Longin Maurizio Caporali, Davide Catani and Xavier Martorell 24 Innovation Europe 36 HiPEAC futures UpScale framework for real-time HPC applications Career talk: Michael Hübner, Ruhr-Universität Bochum HiPEAC collaboration grants: When Manchester met Luis Miguel Pinho ‘Silicon Island’, Crete 25 Innovation Europe HiPEAC internships: Transport safety as standard InnoHPC brings HPC to the Danube region Three-minute thesis: Memory access control which is Karina Pešatová right on time

2 HiPEACINFO 51 welcome

28 31 35 Parallelizing Python Keep the revolution going The drive to succeed

This issue is about digital skills. As the director of the computer engineering degree of Ghent University for more than 10 years, this subject is close to my heart. Two large ICT companies in Belgium have more open positions every year for computer engineers than the total number of graduates in one year in Ghent. That is painful for them, but they can still recruit internationally. Startup companies that do not find local talent face more serious issues. Every month I receive emails from desperate startup founders who have the money to hire computer engineers, but simply cannot find them. Hence, the lack of qualitied ICT workers is slowing down innovation. In 2016, Google published a report titled ‘Digitizing Belgium’, concluding that digiti­ zation could lead to more than 300,000 jobs by 2020, or 100,000 per year from now on. Yet we know how many computing experts will graduate in 2020 from the numbers currently at university: at master’s level, there will be less than 1,000 for Belgium as a HiPEAC is the European network on whole. At best, taking into account all business-related ICT degrees and STEM degrees high performance and embedded architecture that include decent software development skills, we might end up with 10 times more, and compilation. not 100 times more. All well-intended digitization plans (the internet of things, Industrie 4.0, Smart Anything Everywhere, etc.) will fail to deliver their full potential if we do not fix the workforce issue first. Structurally increasing the number of graduates will take up to 10 years hipeac.net because we have to start by sparking interest for computing at high-school level. Retraining people could help in the short term, but a six-month training course will @hipeac hipeac.net/linkedin never be a substitute for a four- to five-year university degree. This is particularly HiPEAC has received funding important given the complexity of modern information processing systems. Producing from the European Union’s inefficient and incorrect software leads to the accumulation of technical debt, to failing Horizon 2020 research and systems, to security, safety and privacy issues. innovation programme under Many of you will be reading this issue at the HiPEAC summer school, ACACES, which grant agreement no. 687698. is our contribution to training the crème de la crème of computing experts in Europe. You will find a HiPEAC Jobs poster inside: by posting this at your organization, you will Design: www.magelaan.be also help ensure the best candidates find their ideal jobs. Editor: Madeleine Gray We wish you a relaxing summer, and we hope to see you again after the summer Email: [email protected] holiday in good health, and full of plans for the year to come.

Koen De Bosschere, HiPEAC coordinator

HiPEACINFO 51 3 Policy corner Digital skills for a competitive Europe

In a special guest piece for HiPEACinfo, Heidi Cigan of the Directorate- General for Communications Networks, Content and Technology at the European Commission gives us the latest on the digital transformation, the need for new skills and the Digital Skills and Jobs Coalition.

Digital technologies are advancing and Schools still lag behind in terms of digital leading to the development of everything education. Equipment is still lacking in from digital medical diagnosis and auto­ many places and teachers, though often nomous vehicles to drones and smart willing, lack the skills and confidence to fridges. Where digital was once a sector, it make the most out of digital tools for is increasingly spreading to the whole learning and teaching the next generation economy as society undergoes a digital how to use them. Digital tools are under­ transformation. used in the classroom and most students are still not taught the basics of computer This digital transformation of the economy science and how to code – skills and com­ and society is also accelerating. The pace petences that are increasingly becoming of technological adoption is speeding up. essential for an understanding of the New technologies enter the market and world we live in. In higher education, are being taken up more quickly than ever graduations in computer science have before. For example, while it took decades fallen substantially over the past 10 years for the telephone to reach 50 % of house­ and those students who do graduate are holds, it took mobile phones less than five often not considered work ready by years to reach the same penetration rate. employers. Today in Europe, there are 137 mobile phone subscriptions for every 100 people. It is hardly surprising, then, that we do Smart phones reached 40 % penetration not have enough of the skilled technology in just 10 years. New technologies such as experts – big data experts, cloud deve­ cloud services and social networks are lopers and cyber-security experts – we also being rapidly taken up. Indeed, in need for the new jobs emerging in the 2016, 62 % of internet users and 45 % of economy. In fact, Europe already has a enterprises in the European Union used large and growing deficit of digital experts. social networks. From 373,000 in 2015, this gap could grow to around half a million by 2020. To use these new technologies and ensure individuals, companies, regions and coun­ Digitally skilled workers are lacking at all tries get the benefit from them, people levels and in all sectors. For industry, and need to be able to use and work with the economy more broadly, to digitize, them. However, while technological workers in all sectors need to develop new develop­ment and adoption is speeding up, skills to work in the digitized workplace people’s skills and the education and and to remain employable. However, 37 % training systems that are there to develop of the labour force in the EU lacks basic them are slower to adapt. skills for the use of digital technologies. Furthermore, while most companies are aware that lacking digital skills in their

4 HiPEACINFO 51 Policy corner Digital skills for a competitive Europe

workforces negatively affect business per­ The Commission is also working with in Rome, the Commission announced the formance, most do not provide oppor­ Member States, through an expert group, launch of a new multi-million euro ‘Digital tunities for their employees to re-skill. to support the development of national Opportunity’ pilot scheme to provide digital skills strategies. The group has put intern­ships for current and recent To support the development of digital together a joint strategy document which graduates of all disciplines in digital skills in Europe, on 1 December 2016 the collects the main challenges faced and domains. It is envisaged that these intern­ European Commission launched the solutions found by Member States in the ships should focus on ‘deep tech’ skills Digital Skills and Jobs Coalition. The area of digital skills. A selection of best such as such as cybersecurity, big data, Coalition brings together stakeholders practices has been linked to it and quantum or artificial intelligence, as well from, for example, industry, education, published online as a tool to be used for as on more horizontal activities such as government and social partners to share the development of digital skills strategies web design, digital marketing, software best practices and make ‘pledges’ to and replication of solutions that work. development, coding or graphic design. provide training and carry out other The pilot scheme will initially run for two activities, such as awareness-raising activi­ Since its launch, the Coalition has attracted­ years from 2018-2020 and will support up ties, to increase the digital skills of over 200 member organisations and around to 6,000 paid internships. European citizens. 70 pledges. Sixteen National Coalitions are in operation or being developed. To achieve our goals, we need to get all Member States have been asked to develop stakeholders on board, and the HiPEAC comprehensive digital skills strategies and The aim of the Coalition is to train over a community can play an important role. You to set up national digital skills coalitions million people over the next two years, to are a large group of skilled professionals involving a broad range of stakeholders in ensure Europe has a pool of digital experts, with a wealth of knowledge in all areas of order to support the implementation of and that workers and citizens more broadly digital technology, and you can potentially these strategies. The Commission has set have the skills they need to succeed in the make a huge contribution to the dissemi­ up a Coalition secretariat to support the digital transformation. nation of digital skills across Europe. For setup of national coalitions – for which a many of you teaching is a primary activity, small amount of ‘seed funding’ has been As a concrete contribution to this goal, on so you know the challen­ges ahead. We provided – and other activities. 23 March 2017, as part of the Digital Day invite you to join the Coalition and make your own contribution to securing our digital future.

MORE INFORMATION: https://ec.europa.eu/digital-single-market/en/ digital-skills-jobs-coalition https://ec.europa.eu/digital-single-market/en/ european-digital-progress-report http://bit.ly/EC_Digital_Skills_Report https://ec.europa.eu/digital-single-market/en/ digital-scoreboard

HiPEACINFO 51 5 HiPEAC news

Hvala Zagreb! HiPEAC on the road Digital health, the future of HPC and preparing new generations of computer scientists

A warm Croatian welcome awaited Com­ to find out more about different aspects of puting Systems Week in Zagreb on 27 and their future in computing. 28 April, which brought together over 130 participants from academia and industry. Meanwhile, the second edition of the The event featured keynote talks on how Student Heterogeneous Programming Rimac Automobili went from a hobby Challenge gave students free reign to find project to building the world’s fastest the best solutions for k-means clustering, a electric car and from Martin Kersten on popular approach for big data analytics and Over the last few months, HiPEAC has been at database management systems. machine learning. Marcos Canales, of the a number of key events in the computing 'Heterogeniuses' team, commented­ that the calen­dar, spreading the word about HiPEAC In his policy briefing, the European challenge provided 'a unique opportunity to services and research by the HiPEAC community. Commission’s Panagiotis Tsarchopoulos set work with different people from the super­ out the direction of public HPC research computing area’, resulting in an experience At Embedded World in March, HiPEAC hosted over the next few years. Advances in HPC which was ‘truly enriching and represents a session on high-performance and embedded spurred by the European projects MANGO, the spark of what may become future colla­ architectures, and at DATE 2017 (Design, ExaNeSt, EcoScale and ExaNoDe were boration'. He added: 'The HiPEAC Student Automation and Test in Europe) HiPEAC presented, while EuroLab-4-HPC presented Heterogeneous Programming Challenge is a organized a special session focusing on Euro­ HPC roadmapping­ work and chaired a panel must for any student starting a career in pean research. Meanwhile, HiPEAC’s exhibition session on open-source software for data supercomputing.' booths at DATE and ISC High Performance centres and HPC. 2017 featured presentations by European With the aim of helping researchers get projects and the HiPEAC mobile careers unit, The event also featured a session focusing their message across, HiPEAC also organized displaying computing systems vacancies from on digital health – a key topic for the a media skills workshop at the event. across Europe. HiPEAC community, given that health is the Learning from good (and bad) examples, second biggest market for embedded participants learned the basics of working HiPEAC also hosted a booth at the Digital systems in Europe. Representatives from with the media, drafted press releases, and Innovation Forum in May, providing the oppor­ Ericsson Nikola Tesla, Xsensio and Bluebee gave mock interviews for radio and tunity to speak to business leaders about how identified challenges and highlighted the television. HiPEAC’s members can help digitize European latest innovations in this field. industry. Thanks to local host Mario Kovacˇ and his This Computing Systems Week also sought team at the University of Zagreb for their to help early career computer scientists hospitality in the stunning Croatian capital. develop their skills and explore career oppor­ tunities. With career advice and com­pany See our interview with Martin Kersten on pitches, the ‘Inspiring futures! Researchers’ p.12. For more on Rimac Automobili, see careers’ session offered students the chance p.25.

The HiPEAC Jobs mobile careers unit at DATE 2017 Photo: Eneko Illarramendi

6 HiPEACINFO 51 HiPEAC news

European cooperation on connected mobility and digital industry

Digital Day, which formed part of the 60th anniversary celebrations of the Treaties of Rome, also saw 29 European countries sign a Letter of Intent to intensify cooperation on testing of automated road transport in cross-border test sites. The initiative aims to drive for- ward plans in the European Data Economy strategy.

National elected representatives and industry leaders also pledged to collaborate in the European platform on digitizing industry. The EU states to work together platform will trigger collaboration and joint investments, provide a for world-class HPC forum to explore common approaches to regulatory problems and help industries and countries exchange the means for workforce On 23 March, during Digital Day in Rome, ministers from seven re-skilling. European countries (France, Germany, Italy, Luxembourg, the Nether­ lands, Portugal and Spain) signed a declaration to support the next The event also saw the launch of the European Interoperability generation of computing and data infrastructures. The states will Framework (EIF), which gives specific guidance on setting up inter- work towards the establishment of a multi-government cooperation operable digital public services. framework for acquiring and deploying an integrated supercomputing infrastructure for the exascale computing generation. Named Digital Day website: http://bit.ly/DigitalDay_EU EuroHPC, the European Commission says that this project will be the size of Airbus in the 1990s and of Galileo in the 2000s. It will provide a major role for leading supercomputing centres and scientists in Europe. In June, Belgium also joined the agreement. Imec launches self-learning chip HiPEAC co-founder and coordinator of HiPEAC 1, Mateo Valero, who The Belgian innovation hub imec has demonstrated a self-learning neu- is the director of Barcelona Supercomputing Center, represented the romorphic chip. The chip, which imec says is a world first, is based on view from the supercomputing sector in a panel discussion on ‘How OxRAM technology and has been shown to be able to compose music. Europe can regain leadership in HPC’. In his talk, Valero stressed the By co-optimizing the hardware and software, the chip concentrates importance of investing in hardware design in Europe to complement machine-learning characteristics in a small area, while consuming very existing strengths in software, mentioning how HiPEAC performs a little power. key role in promoting collaboration across the computing systems spectrum. ‘If we don’t produce our own hardware, we won’t have Ultimately, imec aims to achieve low-power, high-performance, intelli- security […] and we also need to protect our companies,’ he gent chips for a range of applications. commented. For several years, Valero has been calling for the establishment of an ‘Airbus-type consortium’ for HPC and big data, Visit the imec website for further information: http://bit.ly/imec_chip in order to develop a full domestic exascale stack in Europe.

With a view to creating the chips of the future here in Europe, the Commission included a challenge to develop a working prototype of a low-power processor design in the ICT-05-2017 call for project proposals (as reported in HiPEACinfo no.48). Successful projects will be announced in the autumn.

Further information and a video of the panel discussion are available on the European Commission website: http://bit.ly/Digital-Day_HPC. See http://bit.ly/EuroHPC for more details about EuroHPC.

HiPEACINFO 51 7 HiPEAC news

TETRACOM evolves into TETRAMAX

Rainer Leupers, RWTH Aachen University, We are excited to announce that this success story will be continued at TETRAMAX project coordinator a much larger scale and with even higher ambitions during 2017-2021 thanks to the TETRAMAX project (www.tetramax.eu). Enabled by a total Many HiPEACinfo readers will have heard budget of €7 million and 22 partners from all over Europe, this new about, or even participated in, the TETRACOM Horizon2020 Innovation Action will provide an implementation of the FP7 Coordination Action (www.tetracom.eu) European Smart Anything Everywhere (SAE) initiative in the domain of during 2013-2016. Its focus was on small to customized and low-energy computing for cyber-physical systems and medium scale academia-to-industry technology transfer projects (TTPs), the internet of things. each one revolving around industrial uptake of specific software or hardware intellectual property (IP) generated in research projects. The project builds on three major activity lines: 1. Stimulating, organizing, co-funding, and evaluating different types of TETRACOM coordinated and sponsored 50 TTPs in total and had a cross-border technology transfer experiments, providing ‘EU added tangible impact on the European ICT landscape, as indicated by the value’ via innovative technologies to first-time users and broad numbers given below. markets in European ICT-related industries. 2. Building and leveraging a new European competence centre network, offering technology brokerage, one-stop shop assistance and training in customized/low-power computing to small and medium-sized enterprises (SMEs) and mid-caps. This will have a clear evolution path towards new regional digital innovation hubs where needed. 3. Paving the way towards self-sustainability based on pragmatic and customized long-term business plans.

The project impact will be measured based on well-defined, goal- oriented performance indicators. The immediate aim is to support 50+ industry clients and third parties across the entire European Union with innovative technologies. This will lead to an estimated revenue increase of € 25 million based on 50+ new or improved customized, low-power com­puting products, the creation of at least 10 entirely new businesses/ SMEs, over 30 new permanent jobs and significant cost and energy savings in product manufacturing. Moreover, in the long term, TETRAMAX will be the trailblazer towards a reinforced, profitable, and sustainable ecosystem infrastructure, providing competence, services and a continuous innovation stream in customized/low-power com­ puting at European scale, yet with strong regional presence, as preferred by SMEs.

Just like TETRACOM, TETRAMAX will work closely with HiPEAC via joint event organization and dissemination. We also expect that the HiPEAC community will be particularly interested in participating in our open calls for co-funded technology transfer experiments.

Stay tuned for further announcements and pass this news on to your European technology transfer partners, so as to be ready for the first open calls to be published soon after the project kickoff in September.

www.tetramax.eu TETRACOM’s vital statistics in tech transfer

8 HiPEACINFO 51 HiPEAC news

New TaPaSCo tool composes Turbo-charge accelerators into bitstreams your code with for FPGAs POP’s webinar Jens Korinth, Technische Universität Darmstadt series

The Embedded Systems and Applications Group (ESA) at TU Darmstadt is pleased to announce Want to maximize your code’s performance? the public release of TaPaSCo (Task Parallel System Composer), the successor to ThreadPool- POP, the EU-funded Centre of Excellence in Composer, an open-source toolchain for creating task-parallel system-on-chip architectures Performance Optimisation and Productivity, is for hardware accelerators on FPGAs. TaPaSCo composes accelerators formulated in Verilog/ offering a series of webinars focusing on how VHDL, or by high-level synthesis (HLS) in C/C++, into ready-to-use bitstreams for a range of to optimize parallel codes for research and Xilinx FPGAs. industry. The webinars provide expert guid- ance on code optimization, with practical The tool can automatically scale the number of accelerator instances, aiming for the ideal demonstrations and implementations on real trade-off between area utilization and operating frequency. On the software side, the accel- applications. erators in the bitstreams generated by TaPaSCo are accessible using a universal easy-to-use C/C++ API across multiple FPGA platforms. TaPaSCo currently supports PyNQ and ZedBoard, Coordinated by Barcelona Supercomputing Xilinx ZC706 Zynq and VC709 FPGA platforms, thus spanning the embedded, desktop, and Center, POP brings together expertise from high-performance computing domains. across Europe. It offers services to provide greater awareness of issues affecting comput- The tool is open source and has been designed with easy extensibility and modifiability in ing performance, help manage the complexity mind. It is the result of three years of development in the EU FP7 project REPARA and is cur- of modern computing and maximize the effi- rently being used by a number of academic and industrial partners outside of TU Darmstadt. ciency of compute-intensive applications.

The tool has proven especially useful in conjunction with HLS, since it easily closes the gap For further information, visit the POP website: between the hardware of individual accelerators and their integration into a hardware/soft- https://pop-coe.eu ware system.

With the 2017.1 release of TaPaSCo, we cordially invite the research community to make use “POP webinars provide of and participate in this project. Both the tool as well as introductory materials are available expert guidance on code from a dedicated GitLab site. We highly appreciate feedback, questions and contributions - anyone is invited to contribute to the toolchain, be it extensions, modifications, bugfixes, optimization” benchmarks, or other results. A bugtracker is available to request new features, or report bugs; also, do not hesitate to contact us when you run into problems. Judging from the feed- back of our existing users, TaPaSCo has significantly reduced their engineering efforts required to make reconfigurable computing actually usable and avoided the need to reinvent the wheel for the different computing platforms.

REPARA project: http://repara-project.eu TaPaSCo GitLab site: http://bit.ly/TaPaSCo_GitLab

HiPEACINFO 51 9 HiPEAC news

Silexica reach German What the F-OMP is Entrepreneur Award finals going on in OpenMP? F-OMP: A Feedback monitoring infrastruc- Congratulations to Silexica, the RWTH Aachen • The SLX Mapper has a new set of visuali- ture for OpenMP on embedded systems University spin-off specializing in multicore zation capabilities providing deeper Giacomo Valente, University of L'Aquila software design automation, on being named insights into application runtime behav- one of three finalists for the German Entrepre- iour of computed/simulated mappings. neur Award 2017 in the StartUp category. At • The SLX Generator now features added the time of going to press the winners had support for additional processor cores not been announced. such as 32-bit ARMv7 and 64-bit ARMv8, Embedded systems normally execute appli- as well as Linux-based Power-PC 32-bit cations with both functional and non-func- In April, the company released the latest ver- and 64-bit processors. tional constraints, and the underlying hard- sion (2017.4) of its SLX Tool Suite. This • The SLX Automotive Development pack- ware and software can be very complex and release provides many new features to age is now available with the rest of the heterogeneous. Different techniques are improve the efficiency of multicore program- SLX tools. used to manage the complexity of develop- ming and code distribution. These include: ing a system which meets the necessary • The SLX Parallelizer now has a powerful silexica.com constraints. Among them is the use of reconfigurable cache analyser that simu­ Find out who was named German Entrepre- OpenMP, which supports designers in paral- lates cache behaviour and estimates usage neur 2017 on the awards website: lelizing applications written in C/C++ and statistics. www.deutscher-gruenderpreis.de/en Fortran code.

As OpenMP allows implicit parallelism, it is harder to control all the factors involved in the performance, such as memory accesses, cache behaviour and thread mutual exclu- sions. To solve this, F-OMP proposes a moni- toring infrastructure which provides feed- back about the use of OpenMP in an embedded platform, developed on FPGA. Specifically, it uses metrics to organize data collected at runtime into useful information (estimated speed-up, load balancing and false sharing), providing feedback to the designer without inserting software overhead.

We have implemented F-OMP on a Zynq7000 SoC, with a dual-core ARM processor as the master processing element and four-core Leon3 SMP as an isle of computational ele- Silexica’s Maximilian Odendahl and Johannes Emigholz ments. This isle executes a Linux operating system, which provides support for OpenMP applications, and it executes two OpenMP benchmarks with data provided by the master processing element. The F-OMP system was inserted in the platform, provid- ing the metrics listed above.

10 HiPEACINFO 51 HiPEAC news

Roger Needham Award presented to Alastair Donaldson

Mateo Valero wins IEEE-CS Charles Babbage Award Mateo Valero, professor in the Computer Archi­ numerous awards over his career. These tecture Department at the Universitat Poli­ include the 2007 IEEE/ACM Eckert-Mauchly Congratulations to HiPEAC member tècnica de Catalunya – Barcelona Tech and Award, the 2015 IEEE-CS Seymour Cray Award, Alastair Donaldson, who has been pre- director of Barcelona Supercomputing Center, the 2009 IEEE Harry Goode Award, the 2012 sented the BCS Academy of Computing has been awarded the 2017 IEEE Computer ACM Distinguished Service Award and the Roger Needham Award 2017. The award, Society Charles Babbage Award. According to 2015 Euro-Par Achievement Award, in addition which is sponsored by Microsoft Research the IEEE, this award recognizes Valero’s ‘contri­ to multiple awards in his home country of Cambridge, was given to Donaldson ‘in rec- butions to parallel computation through brilliant Spain. He has been given honorary doctorates ognition of his outstanding work in the area technical work, mentoring PhD students, and by nine universities and was admitted to the of many-core programming’. building an incredibly productive European European Union’s ICT (Innovate, Connect, research environment’. The award was presented Transform) Hall of Fame in 2008 as one of the According to BCS, Dr Donaldson, from the at the annual IEEE-CS Interna­ tional­ Parallel and 25 most influential information technology Department of Computing at Imperial Col- Distributed Processing Symposium (IPDPS researchers in Europe. He is a member of five lege London, has ‘made a distinguished 2017), where Valero presented­ a keynote academies and the school in his hometown, contribution through his design and appli- speech on runtime-aware architectures. Alfamén, has been named after him. cation of rigorous program analysis meth- ods to the emerging field of many-core Valero, who co-founded HiPEAC and coordi­ Congratulations from the HiPEAC community programming. His techniques and case nated the first phase of the project, has won on this award! studies have also made a major contribu- tion to fundamental Computer Science research’. Dr Donaldson’s work centres Amir Ashouri wins Italian IEEE around formal verification, systematic test- ing, programming language design and Computer Society PhD Thesis Award compiler technology. HiPEAC student Amir Ashouri’s PhD thesis has been selected as the winner of the 2016 IEEE Computer On receiving the award, Dr Donaldson said: Society Italy Section Chapter PhD Thesis Award. His ‘I'm incredibly honoured to be receiving winning thesis, titled 'Compiler Autotuning Using the 2017 Roger Needham Award. It's really Machine Learning Techniques', was written under exciting to have my work recognized via the supervision of professors Cristina Silvano and the award, and more generally the award Gianluca Palermo at the Politecnico di Milano, as emphasizes the importance and potential well as John Cavazos of the University of Delaware. of research in programming languages and analysis and verification.’ Congratulations to Amir on winning this award! Further information can be found on the Further information can be found on the IEEE Computer Society website: BCS website: http://bit.ly/ http://bit.ly/IEEE_CS_Italy_PhD RogerNeedham_AlastairDonaldson

HiPEACINFO 51 11 HiPEAC news

Is it time to rethink our approach to data storage? In this interview, Martin Kersten (Centrum Wiskunde & Informatica) gives us the lowdown on Monet DB, how to deliver the memory for exascale computing and why we should think about whether we really need to keep data forever. ‘Data will rot away like everything in nature’

What does Monet DB offer that other What is your favourite application of database technologies don’t? MonetDB? Monet DB was developed over a period of Actually, it’s the product itself. I’m really twenty years, and its origin was the proud that we were able to build Monet decision to change the storage format DB: we worked for it for about 20 years from a record-oriented mechanism to a and I’m really pleased that for all those column structure. When we started the years I had a team of very strong hackers project in the 90s, this was a no-go area dedicated to making it a viable product. proven by science. It took us seven years to prove that it was in fact possible. An What’s the most challenging database enormous field opened up called data project you’ve ever had to work on? analytics, where this was the perfect A milestone was in 2005, when we solution. Since around 2010, all major thought we had a finished product which database founders have incorporated we could ship to the outside world. We column-oriented technology, which we found an example in a big catalogue of pioneered, into their product lines. astronomical data that was developed by Jim Gray and Alex Szalay. It was a pivotal example because it showed that astro­

The astronomy field generates huge amounts of data Photo: ESA/ATG medialab; background: ESO/S. Brunier

12 HiPEACINFO 51 HiPEAC news

‘Data will rot away like everything in nature’

nomers could actually do their research on The second aspect of the system is that the nity itself is to stop keeping data around a database. As a database was available in execution method used in Monet DB is forever and ever. Rather, we should start public, we thought, ‘if Microsoft SQL completely different from other database out from the other end of the spectrum and server can do it, so can we’. So we systems. It is much more attainable for say, ‘data will actually lose its value, it will re-implemented the existing application parallel processing. For the details, see the rot away like everything in nature will rot using our technology. literature. away’. So we should design a system using a fundamentally different mechanism. In the end, we were the only ones who How is ExaNeSt (European Exascale successfully mimicked that approach, and System Interconnect and Storage) What this will lead to is that we ask our there were some major hurdles along the paving the way to exascale computers? users to be more concerned about how way; but the outcome was that all the Exascale storage is already there; in fact, long the data should be maintained, or to technology was available in Monet DB, my own lab alone probably has a couple of distil it into summarized information. A open source, even if you did have to pay petabytes of storage. In ExaNeSt, our good example is to go back to the Microsoft for the SQL server licences. vision is that we can have hundreds of astronomers: in the astronomy world, thousands of processors with limited they collect years of the light intensity of Over the last five years, Monet DB has memory. This allows us to give people a stars. You can store that – but every star opened up the whole software ecosystem. small slice of that machinery to do can actually be approximated with a The database system is not a black box, database processing without any concern Gaussian distribution. This can be stored where you have to use poor APIs to store about others trying to use the same in just a few bytes. and retrieve data. Instead, we have machinery, meaning that you don’t have achieved the blending of your favourite competition for resources. Now, wouldn’t it be nice if we took that programming languages, your favourite enormous catalogue of observations and libraries, inside the kernel. This signifi­­ The underlying technology for that is turned it into a collection of Gaussian cantly improves the effectiveness and the elasticity of the system, so that it is easy to models? This actually requires less than performance of your application/database repartition your data, your storage plat­ one per cent of the storage, but an combination. form and your compute platform for astronomer could no longer distinguish particular uses. This is not something you whether they were looking at the actual Why is column-store important? do every week, or every night – you may data or at models of the data. That would Going from a row-oriented representation have to do it every minute while your sys­ be my dream for the future: can we to a column-oriented representation, you tem is running. So ExaNeSt is about pro­ somehow compress the data into much get leaner files of data, which gives you viding extreme elasticity, with a focus on smaller, manageable and more valuable many more opportunities to compress providing the user the amount of resources pieces of information. In fact, as your data. Compression in a column store they need to do their job – quickly. individuals we don’t want our personal is often better than you would see in data to be retained forever, so having a traditional compression structures. This is What’s the biggest challenge in the data­ database system which starts forgetting by relevant because if you can make things base world over the next 10 years? itself would be a bright future. small they require less storage and less There are many; we’ve published a couple communication to get the data from the of vision papers on the topic. The latest one www.monetdb.org disk into the memory for processing. I put on the table for the database commu­ www.exanest.eu

HiPEACINFO 51 13 HiPEAC jobs Trends in computing systems jobs

With 10, 000 visitors every month, a number that continues to grow, in demand may be in short supply and provides an indication of the the HiPEAC Jobs portal is an indispensable resource for anyone looking time needed to find the right candidate. To help spread the word about for a new opportunity or seeking high-quality staff for specialist com- the portal, we invite you to display the HiPEAC Jobs poster in this issue puting roles. Over the years it's become a key tool to take European on information boards at universities and schools. research forward: in total, 411 jobs related to European projects have been published on the portal. The vacancies are published on the web- Numbers provided indicate total number of vacancies posted on site for an average of 65 days, which indicates that the technical skills the portal

Number of vacancies Vacancy locations 450 800

700 600

600 525 500

400 351

300 1 198 200 176 134 100 65 9 4 14 17 15 23 0 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017

Levels of experience Application areas

Machine Learning (114) IoT (77) Computer Deep Learning (28) Automotive (75) Avionics (16) CPS (33) Vision (50) Other Artificial Intelligence (16) Master

PhD Student Software Engineer

Bioinformatics (31) Energy (378) Healthcare (46) Climate (52) Space (144)

Engineer PostDoc

Big Data (93) Timing Analysis Cloud (229) Fintech (1) Smart Cities (6) Company Professor Data Analytics (46) (14) Researcher Associate Research Professor Associate Lecturer Assistant Senior Assistant Researcher Researcher Professor

Technical skills Technological Expertise

SYCL C++ Python Javascript

OmpSs Hadoop Caffe MPI OpenCL VHDL JAVA Tensor LLVM flow OpenMP CUDA Verilog OpenGL

14 HiPEACINFO 51 hipeac.net/jobs Recruitment special Team Europe Getting the brains to power the digital revolution As Heidi Cigan indicates in her article (pp.4-5), the digital skills education here. However, many skilled graduates leave for gap is approaching crisis levels in Europe. In A New Skills Agenda opportunities outside of Europe, perhaps due to the lack of a for Europe (2016), the European Commission estimates that digital ecosystem, with major ICT companies being located unfilled vacancies for ICT professionals could almost double to outside of Europe. An absence of high-profile industry 756,000 by 2020. Yet, as the HiPEAC Vision 2017 notes, from spokespeople may also contribute to computer science being less 2007-2013 the number of European graduates in computing only attractive as a career choice in Europe. grew by about 0.5% per year, and even declined in several major European states. In this article, HiPEAC experts give their opinion on everything from getting children interested in computer science, to university Europe boasts 42 of the world’s top 100 universities. Although curricula, to the unique advantages of working at a smaller the quality of education provision varies across the region and company or a global brand. We also explore European initiatives education providers struggle to keep up with the rapid pace of promoting excellence in human resources and discuss how to get technological change, many have access to a high-quality more women on board.

A CHALLENGE FOR THE FUTURE

Sabri Pllana, Associate Professor, Department of Computer Science, Linnaeus University

Europe is already doing well in terms of computer science education, but we lack prominent role models. We need to do more to promote entrepreneurs who have studied computer science in Europe and achieved global success in ICT through the mainstream media.

To attract children’s interest in computer science, it is important to establish a link between theoretical knowledge and its application in solving real-world problems early in the learning experience. We believe that appropriate pedagogical methods can increase children’s motivation. For instance, competitions can promote computer science and discover talent among young people.

SciChallenge aims to boost children’s interest in education and SciChallenge is inspiring young learners in STEM subjects careers in science, technology, engineering and mathematics Photo on top © Kinderbüro Universität Wien (Barbara Mair)

HiPEACINFO 51 15 Recruitment special

(STEM) through a pan-European contest. Contestants were asked to submit a poster, presentation or video on any STEM- related topic, although SciChallenge suggested 50 topics as inspiration. Many of these are related to computer science, including the internet, robotics, cryptography, 3D printing, or e-health.

The contest is designed with gender equality in mind and, interestingly, more than 50% of the contestants are female. One presentation created by a group of girls for SciChallenge has attracted over a million views (http://bit.ly/SciChallenge_ ImmortalGirls). The success of female contestants in SciChallenge will inspire other girls in future. Tadej Strah built a motorized gimbal to stabilize cameras The results have been inspirational, and there also some potential future HiPEAC members among the candidates, such as: The full list of finalists is available on the SciChallenge website: • the creators of a device to transport industrial components www.scichallenge.eu using sensors, vacuum grippers and a programmable logic controller: http://bit.ly/SciChallenge_SLO_SRB SciChallenge is funded by the European Commission’s Horizon 2020 • a group which used machine learning and data analytics to research and innovation programme under grant agreement no predict a musician’s future popularity: http://bit.ly/ 665868. SciChallenge_Huemer_Jetzinger • a contestant who developed an Arduino-based motorized gimbal for camera stabilization: http://bit.ly/ SciChallenge_TadejStrah

TRAINING THE NEXT GENERATION

Marisa Gil, Associate Professor, encourage students to be aware that people and their needs Department of Computer Architecture,­ come before solving technical problems which won’t make the Universitat Politècnica de Catalunya world simpler and better for everyone. They should be agile and – Barcelona Tech unafraid of the effort required to effect real change and create new ways of thinking. We need a well-trained workforce in high-performance computing (HPC) and To push their career forwards, students should first undertake a embedded systems here in Europe because the problems we face thorough and personal examination of how they can make the and the continent’s particular characteristics are different to most of their studies and the opportunities available to them. those of the United States or Asia, for example. Having Next, they should share their experiences with students and homegrown technology professionals helps ensure that the senior staff. Finally, they shouldn’t be afraid of being a bit short objectives, challenges and solutions are appropriate and are of money or not knowing exactly what they will do in the future; those which will really lead Europe to advance. they will certainly achieve great things.

As a network of computer scientists, within HiPEAC we have a Marisa Gil organizes the Student Programming Challenge at responsibility to train and nurture future generations, leaving Computing Systems Week with Chris Fensch of Heriot-Watt successors who will continue the work in this area. Educators University and Georgios Goumas of the National Technical need to be capable of training students to be open minded and University of Athens (see p.6). able to identify the main issues and objectives. We should

16 HiPEACINFO 51 Recruitment special

CURRICULUM MATTERS: EUROLAB-4-HPC

Dionisios Pnevmatikatos, Affiliated Researcher, Foundation for Research and Technology – Hellas (FORTH) and Alexey Cheptsov, Research Scientist, High Performance Computing Center Stuttgart (HLRS)

We have also used a questionnaire to find out the opinion of experts and educators in the field, with their feedback being used to better focus the direction of the proposed curriculum. In Since the introduction of cloud technology, high-performance addition, we collected information about existing courses at computing (HPC) is no longer limited to a small set of experts institutions around Europe. but is visible to and affects even everyday users of desktop PCs and mobile devices. In recent years, HPC has gone beyond The major educational targets we have set for the curriculum traditional application areas such as climate analysis, weather are: prediction, astrophysics, etc., to new applications in social media, • to promote parallel thinking big data, biomedicine and many more. Many of these new • to develop the ability to program parallel systems applications are being pioneered by small and medium • to promote understanding of performance (in processors, enterprises, facilitated by European Commission initiatives such compilers, code, communication, etc.) as the FORTISSIMO project (www.fortissimo-project.eu). • to evaluate and debug performance • to promote knowledge of parallel algorithms Research, science and education are the main pillars to ensure • to promote programming and use of heterogeneous systems that leading-edge services are delivered in all areas of HPC provisioning. While HPC is well positioned in terms of research Our aim is for the proposed curriculum to act as a reference point and science, the educational HPC horizon remains limited. both for educators and institutions that would like to extend their course inventory into HPC. We also hope it will allow Unfortunately, there is currently no common view among leading students to select courses, either within their institutions or via European educational institutions on the process of expanding distance learning, to build their knowledge and skills in parallel curricula to include HPC-specific topics. Standardi­zation in HPC and HPC programming. curricula in Europe should start at the basic level, so that the foundational set of ideas, terminology, skills, and tools are taught HPC experts! Want to help shape the HPC curriculum? Complete to all students. the online survey here: http://bit.ly/2n5Pvy7

Most current higher education curricula do not stress parallel EuroLab-4-HPC is funded by the European Commission’s Horizon thinking from the beginning and more advanced topics are 2020 research and innovation programme under grant agreement usually only included in specialized programmes. We need to no 671610. increase understanding of parallel programming and algorithms in the general student population. A good starting point would be to present parallel computing using students’ mobile phones, which are usually built with manycore technologies, then gradually moving out to the scale of modern supercomputers. ‘Think parallel’ should be the main message communicated to students of computer science and related subjects.

To help address this issue, EuroLab-4-HPC has been working on a model HPC curriculum. We have been collecting material from existing educational programmes around Europe and beyond.

HiPEACINFO 51 17 Recruitment special

DEVELOPING THE SKILLS FOR SUCCESS

Marc Gonzalez Vidal, Head of Human Resources, Barcelona Supercomputing Center (BSC)

Being a senior researcher at an institution like BSC offers the opportunity to work on international projects in a unique environment with top-level facilities and interdisciplinary teams. To progress to research management level, candidates need a range of skills and experience.

In terms of research, an international reputation based on research excellence in their field is fundamental, as is critical judgement in the identification and execution of activities. Researchers need to have made a substantial contribution (breakthrough) in their field or across multiple areas. They will have published and presented influential papers and books, served on workshop and conference organizing committees and delivered invited talks. They should recognize the broader need to be excellent communicators and networkers in the implications and applications of their research and develop a research community and beyond, and to act as professional role strategic vision on the future of their research field. models.

However, the skills to progress go beyond the research itself. At BSC we use a tool to help identify each individual’s develop­ Senior researchers are increasingly required to secure funding ment needs and use the information gained via this tool to and to manage and lead research projects. As team leaders, they shape our development programme. Researchers, with the will need skills in managing and developing others. In addition support of their managers, can choose from an extensive to team building, they will need to focus on long-term team programme of training and development actions including planning, such as career positions for researchers and securing project management, leadership, scientific writing and time funding for team positions. Creative and innovative, they will management, among others.

18 HiPEACINFO 51 Recruitment special

POWERING A GLOBAL ELECTRONICS LEADER

Graham Mudd, Senior Technology Manager, and Angela Bradfield, example. We’re a hugely diverse bunch, with over 30 nationalities Head of Human Resources, Samsung Research UK (SRUK) represented in the SRUK office, so specific experience, personality and professional formation are of less importance. The more niche and specific a skill-set is for a particular role, the more challenging it can be to find candidates who meet the To get the best employees, the three watchwords are edu­cation, particular requirements. Meeting talented engineers is therefore environment and enterprise, with commercial organizations, one of our highest priorities and greatest challenges: we know policy makers and private individuals and associations all having the right people are out there and we cast our net far and wide to their part to play. Our strength lies mainly in the area of find them. Another challenge we face is communicating exter­ enterprise, but we also need access to high-quality technology nally the fact that, while we benefit from the strength of the education for all and for there to be healthy, sustainable and global Samsung brand, our UK R&D site is just over 200 strong, welcoming local environments in which to live and work. so we have the advantage of a boutique, family-feel environment. Keeping people happy and engaged is one of the keys to It’s a bit of a cliché, but we really look for talented people who Samsung’s global success. Some of the ways we try to achieve love solving problems and having their solutions show up in this at SRUK include good compensation, a great working actual products. We often hear employees describe the pride they environment, continuous learning and development opportunities felt when purchasing a Samsung device from our staff shop for a – whether you decide to focus on the technical or management family member or friend and being able to brag that ‘I helped route – and the ability to work on game-changing projects that build that’. Our core domains are embedded graphics, computer will most likely show up in a multi-million unit device. vision, augmented reality, machine learning, digital TV and the internet of things. At SRUK, you could be working on projects More detailed information about roles at Samsung can be found such as machine learning for power management, stabilizing on the Samsung Careers page virtual reality video or creating a low-level graphics API, for http://bit.ly/SamsungUK_Careers

SERIOUS FUN AT CODEPLAY

Meenakshi Ravindran, Staff Software Engineer, Compilers, from all over the world. We also have very good relationships and Karon Davis, VP Operations, Codeplay with universities and organizations like HiPEAC; our internship programme is well respected, with internships available at both We work on cutting-edge tech­ undergraduate and postgraduate level. nologies revolving around hetero­geneous com­puting, Specific policy measures could boost the number of candidates. parallel computing, providing These could include fast tracking visa applications for the people a high-perfor­mance platform we need to build our company, encouraging students to study for machine learning, artificial science and technology at school and supporting girls to succeed intelli­gence, computer vision in these areas. It might be worth introducing financial incentives and other computationally intensive graphics applications. These for students to study relevant subjects. require technical skills including a strong core knowledge of modern C++ (11/14), coupled with understanding of close-to- The single biggest advantage of working at a smaller company the-metal software design, for example how hardware is like Codeplay is that, as an individual, your voice and opinion are programmed at low level for optimized performance. That could always considered and taken into account. You therefore have include areas such as compiler debuggers, programming the ability to contribute and truly feel part of the company rather language design, memory management, graphics programming, than getting lost in a corporate conglomerate. There are oppor­ or parallel software design. tunities to take on interesting projects and advance your career by continuously increasing your knowledge and expertise. Operating in such a highly specialized field, it is quite challenging to find candidates with the required skills. These skills are in To help settle new colleagues, Codeplay offers a three-month short supply so we have a global reach: we are very proud of the mentoring programme to all interns and new starters, whatever international diversity of our team and encourage applications their experience level. We have a robust knowledge-sharing

HiPEACINFO 51 19 Recruitment special

programme and strongly encourage all staff to participate in For the latest career opportunities, visit the Codeplay website local and international communities and events. We also organize http://bit.ly/Codeplay_Careers. regular social events, from games over lunch and weekly movie nights to annual company gatherings. We’re very proud of our Find Codeplay, SRUK and many more vacancies on the HiPEAC record in welcoming staff from over 18 different countries and Jobs Portal: hipeac.net/jobs helping them to settle in quickly to their new country and role.

The HR Strategy for Researchers at BSC BSC is the leading supercomputing center in Spain, hosting MareNostrum, one of the most powerful super­ computers in Europe. With over 500 members of staff from 45 countries, BSC combines HPC service provision and research and develop­ment (R&D) activities under one roof.

BSC is committed to the principles of the EURAXESS European Charter for Researchers and the Code of Conduct for the Recruitment of Researchers. Via the HR Strategy for Researchers, BSC aims to maintain the best environment for research excellence, continuously improving through the adoption of In April 2015, BSC was awarded the HR Excellence in Research international best practices and high-quality standards. logo, recognizing BSC’s commitment to the principles of the Charter and Code. This commits the centre to an action plan, The HR Strategy for Researchers supports organizations to developed in-house and approved by the European Commission, implement the Charter and Code in their policies and practices. to improve its capabilities and performance across a wide range Concretely implementing the Charter and Code makes research of training, recruitment and gender issues. The plan has since institutions more attractive to candidates looking for a new been revised by the HRS4R steering group based on an analysis employer or a host for their research project. Funding organi­ of the results from 2015-2016, and a new plan for 2017-2020 zations which implement the Charter and Code principles has been created and approved. contribute to the attractiveness of their national research systems and of the European Research Area more generally. As Highlights of this ambitious project include: a result, the HR Excellence in Research logo identifies • the creation of advisory committees organizations which either provide or support a stimulating • boosting equal opportunities and gender policies and favourable working environment. • strengthening activities in outreach and public engagement • improving the BSC career development system • incorporating the EURAXESS Open, Transparent and Merit- based Recruitment of Researchers (OTM-R) practices

European Charter for Researchers https://euraxess.ec.europa.eu/jobs/charter

The HR team at BSC

20 HiPEACINFO 51 Recruitment special

Finding Nema: breaching the ICT gender gap We caught up with Bev Bachmayer, Vice may hold, thereby making it difficult for another colleague to Chair of ACM-Women Europe (ACM-W), excel. By joining the discussion and supporting such initiatives to find out how we can help get more people will see that the unconscious bias exists. women in ICT. Is there a danger that such initiatives unfairly promote What are some of the reasons behind women? the lack of gender balance? As soon as 50% of working ICT experts are women, conferences There are hundreds of studies attempting to explain this have 50% women technical experts on the programme and phenomenon. People point out factors such as the difficulty in 50% of computer science/engineering degrees are earned by achieving work/life balance, problems arising from the male- women, then we can worry about whether we are unfairly dominated work environment or blatant bias where companies promoting women. do not enforce gender equality regulations. However, it’s not just the front of the pipeline but the leaky pipeline which finds What practical action can organizations take? us in this predicament. To recruit: 1. Participate in Celebrations of Women in Computing and To combat the problem, we need to focus on the barriers. One careers fairs (see below). is unconscious bias, which is the perception that women are not 2. Bring your engineers to these events to network with the engineers or scientists. A second barrier is the lack of role participants. models: young impressionable women need to see people like 3. Offer internships. them doing the job, so that they can identify that they could do 4. Provide mentors for students. that too. Lastly, a major problem is when qualified women end up leaving the field because of a multitude of problems. To retain: 1. Promote work/life balance, flexible working hours, working Why is it important to provide support specifically aimed at from home. women? 2. Improve maternity leave. Networking helps women attain higher levels of achievement. 3. Provide child daycare. Women often feel isolated when they are the only female in a 4. Proactively build the team with social activities that are group. Bringing technical women together gives them inclusive for all at work. opportunities to see that they are not alone. Additionally, seeing successful women talk about issues that are part of many ACM-W organizes regular Celebrations of Women in Computing. women’s daily life inspires young women to continue in the In addition to keynote speeches, panel discussions, workshops field. Feedback from womENcourage events shows that 89% of and hackathons, these events feature a careers fair where the attendees are more committed to their careers after they supporters can recruit students and professionals. Supporters attend womENcourage. this year include HP, Google, Bloomberg, Oracle, Accenture, Intel, Amazon, Informatics Europe, Inria and Microsoft. Why should men support initiatives to increase the number of women in computing systems jobs? womENcourage 2017, 6-8 September, Barcelona, Spain We need to change the culture and men are needed to help https://womencourage.acm.org/ make that change. Many people are unaware of some bias they

HiPEACINFO 51 21 Inside the box

Last year (issue 47) we caught up with Maurizio Caporali (Università di Siena) and Xavier Martorell (Universitat Politècnica de Catalunya – Barcelona Tech) to find out about the AXIOM project’s plan to build a European single-board computer. We were very excited when the board finally arrived this year. Along with Davide Catani (SECO), Maurizio and Xavi offer us a peek under the hood to show why this board is so special. Well hello, AXIOM board!

After almost two years, we’re delighted to model, OmpSs, allowing straightforward present the AXIOM Board, Serial Number: FPGA programming. It’s designed to be 000000000001. It is the initial result of the perfect combination of high- thorough research funded by the European performance computing, embedded Commission and involving seven different computing and cyber-physical systems. As entities across Europe: three research such, it aims to provide the ideal platform groups/universities – the University of for real-time data analysis of a huge Siena, Barcelona Supercomputing Center amount of data in a short time frame, and the Foundation for Research and machine learning, neural networks, server Techno­logy-Hellas (FORTH) – and four farms, bitcoin miners – you name it. enter­prises – SECO, Vimar, Evidence and Herta Security. Take a look at the image on the opposite page to see what marks the AXIOM board This is the first version of the AXIOM out from the competition. Board, but we truly think we’re on to something. AXIOM is the first board that AXIOM is funded by the European combines three worlds in one: Arduino, Commission under the H2020 Framework ARM computing and FPGA. It runs a Programme for Research and Innovation version of BSC’s flagship programming under grant agreement no. 645496.

The AXIOM board was debuted at Embedded World 2017

22 HiPEACINFO 51 Inside the box

HiPEACINFO 51 23 In this issue we find out about a design framework for applications with strict timing and high-performance requirements, a project to bring HPC to the Danube region and the Heterogeneous Hardware and Software Alliance. Innovation Europe

NEW UPSCALE FRAMEWORK processing response times. Such systems may be used in ALLOWS DEVELOPMENT OF REAL- applications ranging from avionics to traffic management to the TIME HPC APPLICATIONS stock exchange. Manycore processor architectures allow these performance requirements to be achieved by integrating up to hundreds of cores, interconnected with complex networks on chip, paving the way for parallel computing.

Unfortunately, parallelization brings many challenges, by drastically affecting the system’s timing behaviour. Providing P-SOCRATES, a project co-funded by the European Commission, guarantees becomes harder, because the behaviour of the system has created the UpScale Software Development Kit (UpScale running on a multicore processor depends on interactions that SDK) for the development of applications with strict timing and are not usually known by the system designer. This causes system high-performance requirements. The project members designed analysts to struggle to provide timing guarantees for such and implemented an entirely new design framework, from platforms. conceptual design of the system functionality to its physical implementation, to facilitate the deployment of standardized UpScale tackles this challenge by combining technologies from parallel applications in all kinds of real-time systems. different computing segments. These allow developers to successfully exploit both the performance opportunities brought The UpScale SDK targets systems that demand more and more by parallel programming models used in the high-performance computational performance to process large amounts of data domain and timing analysis from the embedded real-time from multiple data sources, while requiring guarantees on domain, for the newest manycore embedded processors available.

24 HiPEACINFO 51 Innovation Europe

The UpScale SDK includes the following components: INNOHPC BRINGS HPC TO SMES • Source-to source compiler – enabling the analysis of source- IN THE DANUBE REGION code OpenMP parallelism annotations, extracting the required information to allow for efficient and predictable mapping and Launched on 1 January 2017, InnoHPC will enable enterprises as scheduling of parallel computations. well as academic and research institutions to cooperate more • Lightweight OpenMP tasking runtime – a small-footprint, low- closely in the field of supercomputing across national borders. In overhead implementation of the tasking model of the latest the first stage, project partners will evaluate the current level of OpenMP specification, which uses the information extracted by exploitation of the regional high-performance computing (HPC) the compiler to map OpenMP tasks to operating systems infrastructures by small and medium enterprises. In the second threads. stage, they will design and establish a transnational InnoHPC • Embedded manycore operating system – a small kernel imple­ laboratory whose main purpose is to provide SMEs with remote mentation which efficiently handles parallel threads in many­ access to the HPC infrastructures. The third stage will involve a core platforms, supporting both static assignment of threads to pilot in which a number of SMEs from the electrotechnical and cores as well as global scheduling approaches. automotive industry use the InnoHPC laboratory and web • Analysis tools – an integrated toolset for the timing and platform. schedulability analysis of real-time parallel applications. The project runs until June 2019 and is supported by the Interreg The SDK framework is flexible and applicable to different use Danube Transnational Programme, whose priority is to promote cases, as demonstrated by the project results. Initially released innovations and social responsibility in the Danube region. The for the Kalray MPPA processor, it is possible to port to different lead project partner is the Faculty of Information Studies in Novo hardware architectures as also demonstrated by the project. mesto (Slovenia). The focus is mainly on the eastern part of the Danube region represented by the other partners in the project. After a first showcase at the project’s Industrial Workshop which took place in Porto in November 2016, the final results of the NAME: InnoHPC - High-Performance Computing for Effective project and the UpScale SDK were presented at Embedded World, Innovation in the Danube Region the international gathering for the embedded system technology START/END DATE: 01/01/2017-30/06/2019 sector, which took place in Nuremberg in March 2017. KEY THEMES: high-performance computing, industrial optimization COORDINATOR: Faculty of Information Studies Novo Mesto (Slovenia) UpScale is openly available and released under commercially PARTNERS: Czech Republic: IT4Innovations National Supercomputing friendly open source licences. It is available to download from Center; Austria: RISC Software GmbH; Croatia: University of Rijeka; www.upscale-sdk.com. Slovakia: Technical University of Košice; Romania: West University of Timisoara, Executive Agency for Higher Education, Research, Contacts Development and Innovation Funding; Slovenia: University of Dr Luis Miguel Pinho, Project Coordinador ([email protected]) Ljubljana, Electronic and Electrical Engineering Association – Chamber Dr Sandra Almeida, Project Manager ([email protected]) of Commerce and Industry; Bulgaria: Research Centre for Regional and Global Development; Hungary: Budapest Chamber of Commerce PROJECT: P-SOCRATES (Parallel Software Framework for Time-Critical and Industry Many-core Systems) BUDGET: €2.05M START/END DATE: 01/10/2013-31/12/2016 (completed project) WEBSITE: http://bit.ly/Interreg_InnoHPC KEY THEMES: high-performance, embedded, real-time, predictability COORDINATOR: Instituto Superior de Engenharia do Porto (Portugal) Project co-funded by the European Union. PARTNERS: Spain: Barcelona Supercomputing Centre, ATOS; Italy: University of Modena and Reggio Emilia, Evidence SRL, Active Technologies SRL; Switzerland: Swiss Federal Institute of Technology Zurich (ETH Zurich) BUDGET: €3.62M WEBSITE: www.p-socrates.eu

P-SOCRATES received funding as part of the European Union's Seventh Framework Programme (FP7/2007-2013) under grant agreement no. 611016.

HiPEACINFO 51 25 Innovation Europe

INTRODUCING THE Complex engineering simulations often come to mind when HETEROGENEOUS HARDWARE AND identifying families of applications that benefit most from SOFTWARE ALLIANCE heterogeneous parallel architectures. However, in the upcoming era of the IoT and big data there is significant interest in exploiting the capabilities offered by customized heterogeneous hardware, Karim Djemame, University of Leeds and Oliver Barreto, Atos all of which have various memory hierarchies, size and access performance properties.

Examples of customized heterogeneous hardware FPGA – field-programmable gate array ASIP –application-specific instruction set processor MPSoC – multiprocessor system-on-chip Heterogenous CPU (central processing unit) and GPU (graphics processing unit) chips Heterogeneous multi-processor clusters

In fact, online big data with nearly instantaneous results demand massive parallelism and well-devised divide-and-conquer approaches in order to exploit heterogeneous hardware, both client-side and server-side, to its fullest extent. Heterogeneous systems can handle workloads with fewer and/or smaller servers, In recent years we’ve seen the emergence of cyber-physical thereby saving costs. They can also slash the energy used to run systems (CPS) and the internet of things (IoT), promoted by certain applications, which provides clear benefits in addressing initiatives such as the European Commission’s Smart Anything the growing interest in ‘green’ solutions and the pressure to Everywhere, which have the potential to transform the way we reduce the environmental impact of data centres, for example. As live and work. For example, the transformational impact of the the HiPEAC Vision notes, a common theme across all scenarios is IoT in the long term is expected to increase significantly with the need for low-power computing systems that are fully mass adoption and tens of billions of things being connected, interconnected, self-aware, context-aware and self-optimizing generating multi-trillions of dollars in economic value. It will act within application boundaries. as a key driver behind new development platforms, analytics applied to things and distributed/parallel architectures, as Because the impact of hardware heterogeneity is rapidly Gartner highlighted in a 2015 report. increasing, innovative architectures, algorithms and specialized programming environments and tools are needed to efficiently As the range of applications grows within CPS, the IoT, high- use these new and mixed/diversified architectures. For example, performance computing (HPC), mobile computing, wearable the transitions to multicore processors, GPU computing and computing, etc., there is an urgent need to design more flexible hardware-as-a-service (HaaS) cloud computing should be viewed software abstractions and improved system architectures to fully as a single trend. As the market for heterogeneous architectures/ exploit the benefits of the heterogeneous platforms on which multicore processors in embedded applications begins to move they operate. Heterogeneous parallel architectures have received into the product deployment stage, the need for software and the considerable attention for their ability to improve absolute underlying programming methodologies is also increasing in performance, minimize power consumption and/or lower costs parallel. by combining different processor types in one system.

However, to put it bluntly, programming directly with this kind of New platforms incorporating multicore CPUs, manycore GPUs heterogeneity is a nightmare. We need to take action so that we and a range of additional devices into a single solution are can rapidly develop solutions that help companies exploit increasingly being introduced. These platforms are emerging in a heterogeneous architectures to create richer experiences and wide range of environments, from supercomputers to personal innovative business models. Those of us who are software smartphones. One of the challenges for future application engineers need a mediator to help us deal with the heterogeneity performance lies not only with efficient node-level execution but and take advantage of high-level abstractions, as happened in also with power consumption, a key focal point. the past with traditional computing. We need to develop innovative architectures, algorithms and even specialized

26 HiPEACINFO 51 Innovation Europe

programming environments and tools to efficiently deal with founding a common, open-source and extendable set of very different architectures in order to be more productive, obtain technologies and tools around the development for heterogeneous rapid learning curves and to build solutions that are more general hardware. These should be viable for mass adoption utilizing purpose. technologies created by the alliance members, as well as being attractive, easy to use and broader in scope and value. The The TANGO project is creating a toolbox to provide the tools to alliance is currently working on the establishment of a reference deal with this reality. However, we recognize that there are others architecture and is creating an online catalogue of tools and in the market and research arena who are also working towards technologies. this direction. Our vision is to avoid creating yet more heterogeneity in the tools and approaches that will lead this Interested in finding out more? Contact us: market in the upcoming years. Therefore, instead of simply www.heterogeneityalliance.eu/contact pushing our own tools, TANGO aims to encourage collaboration. We want to create something that will also create a link between research and the market and exploit potential synergies. TANGO is funded by the European Commission under the H2020 Framework Programme for Research and Innovation under grant To drive this forward, we have initiated the Heterogeneous agreement no 68758. Hardware & Software Alliance (H-HW&SW Alliance). The initiative aims to unite the efforts of organizations interested in Further reading the development of future technologies and tools to advance and TANGO: Transparent heterogeneous hardware Architecture exploit computing and applications using heterogeneous deployment for eNergy Gain in Operation hardware. The alliance will focus on all phases of heterogeneous www.tango-project.eu hardware and software, from design time to enhanced execution, Smart Anything Everywhere parallel programming and optimized runtime. It will consider a http://bit.ly/smart-anything-everywhere number of factors such as energy, performance, real-time, data Survey Analysis: The Internet of Things Is a Revolution Waiting locality and security. This will enable a new way of developing to Happen. Gartner report, January 2015 and executing next-generation applications. http://bit.ly/Gartner_Report15 HiPEAC Vision The main aim of the alliance is to establish an organization in www.hipeac.net/publications/vision which anyone interested in related technological areas can collaborate. Participants will work towards a common objective:

HiPEACINFO 51 27 Peac performance

Rosa Badia of Barcelona Supercomputing Center explains how PyCOMPSs takes inspiration from computer architecture to enable execution in parallel at the software level. Parallelizing Python codes using the superscalar paradigm Rosa M Badia, Barcelona Traditionally, computer architecture instructions are programmed Supercomputing Center (BSC) sequentially, and a program is an ordered list of instructions. However, designs such as the superscalar processor allow parallel Superscalar architectures became execution, with several instructions being executed at the same popular in the early 1990s and are time. What is more, the data dependencies between instructions still in use in most processors. A are dynamically detected by the CPU. This means that out-of- superscalar processor implements order execution and even speculative execution – where some instruction-level parallelism and can instructions are executed that may not actually be needed – are execute several instructions in a possible. All these techniques help make the most of the clock cycle by trying to feed all the instruction cycle and hence minimize delays in processing. execution units on the processor. In the superscalar programming model we follow the same strategy, but implemented at software level. PyCOMPSs is a task- based programming model that offers an interface based on Python sequential code, but that enables execution in parallel by building a data-dependency graph of the application tasks at execution time. A task in PyCOMPSs is a method or a function, annotated with a Python decorator which also describes the directionality of the task parameters.

The directionality of a parameter can be ‘in’ when a parameter is read, ‘out’ when a parameter is written, and ‘inout’ when a parameter is both read and written by the task.

Tasks in PyCOMPSs are equivalent to the instructions in super­ scalar processors, and the objects or files exchanged by the tasks are equivalent to the registers in the processor. The directionality of the parameters is used to derive data dependencies between instances of tasks at execution time. Another idea borrowed from the computer architecture world is register renaming, which we apply to the objects/files exchanged by the tasks.

The syntax of PyCOMPSs is minimal, using decorators to annotate tasks and a small API for synchronization. PyCOMPSs relies on a runtime that is able to exploit the inherent parallelism at task level and to execute the application on a distributed parallel platform (clusters and clouds) while the code remains agnostic of the existing hardware. The runtime is responsible for scheduling the tasks on the available computation resources, performing the necessary data transfers between distributed memory spaces, synchronizing all activities and interoperating with heterogeneous computing resources including cloud middlewares, etc.

28 HiPEACINFO 51 Peac performance

Parallelizing Python codes using the superscalar paradigm Python was chosen rather than other programming languages due to its popularity in several scientific communities. The high level of adoption is not only due to the language features, but also because of the large number of third-party libraries available for the community. Examples of very popular libraries are NumPy or SciPy, which offer data structures and numerical routines. Example of how objects can be persisted with the storage API. NumPy automatically maps operations on vectors and matrices The object X is created and made persistent. Later, it is to the functions of BLAS and LAPACK numerical libraries, which accessed normally in the loop are highly optimized and in many cases parallelized at thread-level. Two backend solutions to store the persistent storage are currently supported: Hecuba and dataClay. Hecuba is a set of tools and With this approach, in PyCOMPSs we can exploit two levels of interfaces that aims to provide programmers with an efficient parallelism: task-level, between nodes of a distributed computing and easy interaction with non-relational databases. More platform, and thread-level, inside the nodes. Results with specifically, Hecuba implements an interface to access data stored numerical kernels such as matrix multiplication, Cholesky or QR in Cassandra databases, such as regular Python memory objects. factorizations show that we can get performances of up to 60% of The object-oriented approach is focused by dataClay, a data store the peak in one node and very good scalabilities up to thousands that offers novel techniques for sharing structured data in a of cores. In all cases, it is important to take into account that the multi-provider ecosystem. user application is a sequential annotated Python code that is executed in parallel by the PyCOMPSs runtime. While the PyCOMPSs runtime operates well with clusters and clouds, up until now it has not been enabled for GPUs, FPGAs or other types of accelerator. To support these types of architecture, a hybrid programming model that combines PyCOMPSs, to deal with coarse-grain tasks, and the BSC programming model OmpSs, to deal with finer granularity, is under research. This and other challenges of task-based programming models will be described and discussed in my lectures at the ACACES summer school this year.

With the objective of giving support to new storage technologies COMPSs is open source. Code, compiled packages and documentation such as NVRAMs or SSDs, PyCOMPSs has been enabled to are available at compss.bsc.es support persistent storage. The programmer is able to define which objects of their program will remain persistent after the Rosa Badia is delivering the course ‘Application programming on execution of the code, although access to these objects by the parallel/distributed computing platforms’ at ACACES17. Further program remains unchanged. Similarly, programs can access information: http://bit.ly/ACACES17_Rosa_Badia objects that were made persistent before. This enables very easy support of producer-consumer sets of applications, or in-situ processing, visualization, etc. This support has been made “Tasks in PyCOMPSs are equivalent possible by the definition of a Storage API with a set of methods, some accessed by the PyCOMPSs runtime and others offered to the instructions in superscalar directly to the programmer. The interface for the programmer is processors, and the objects or files minimal, with a method to make the objects persistent and with are equivalent to the registers” constructors to access data that is already persistent.

HiPEACINFO 51 29 Tech opinion

Attempts to recreate the human brain in silico have sparked fears that artificial systems will replace the human brain. This is a misconception, argue Kemal Delic and Dave Penkler of Hewlett Packard Enterprise. Instead, the human brain – the original computer – is the inspiration for next-generation computing systems. Neuromorphic Computing: low-power systems, the brainy way Neuromorphic computing explores largely Traditional digital computer technology is uncharted territory in several sciences of slated to deliver an exascale machine living and artificial systems. The idea of (1018 FLOPs with 1018 bytes of memory), different kind of computing was driven by but delivering an order of magnitude more the extraordinary capabilities of human performance will require a radical change brain to perform on very low levels of of computing paradigm. This change will energy consumption. As physical limita­ have an impact on the entire chip- tions began to reach barriers which cannot hardware-software stack (figure 2) and be exceeded without drastically changing imply not only novel neuromorphic Figure 3: Different problems may the underlying architecture, some 30 years devices but also different types of software require different approaches ago scientists and engineers started thinking running new types of algorithm. In short, about how to emulate human brain an entirely new technology landscape and In conclusion, as we witness huge invest­ performances with neuromorphic­ chips. architecture. ment in human brain research in the Euro­ pean Union and the United States, Looking at the big picture of computation amounting­ to the investment of one billion vs. communication types of signals (see dollars/euros over the next decade, one figure 1), one should think about neuro­ should not make the mistake of thinking morphic computing as digital communi­ that the human brain will be replaced with cation and analogue computation­ – very artificial systems. The big challenges will be: much as the human brain works. Analogue 1. To construct systems which consume computing preceded digital computing, watts instead of megawatts of electricity. which is dominant today and reaching its Figure 2: Exascale calls for the 2. To reinvent fault tolerance so that it limits. The objective is to achieve the reinvention of the full stack resembles that of the human brain, energy efficiency of the human brain, which is constantly improving while which consumes only 20 watts as com­ An interesting consequence of this will be losing neurons daily. pared with contemporary HPC systems that the different types of problem can be 3. To construct systems that can learn from which consume megawatts of electricity. addressed in a different way and exhibit massive interactions instead of being superior performances (figure 3). For programmed. example, the use of quantum computing and high-performance computing to New computing paradigm(s) will open up design effective neuromorphic computer splendid opportunities for the next gene­ architectures is being investigated. It is ration of scientists and engineers con­ not beyond the realms of imagination that structing entirely new systems and an entire new age of computing might deploying novel devices across the entire open up. architecture stack.

Figures in this article are adapted from the following sources: Rebooting Computing: The Road Ahead by T.M. Conte et al https://www.computer.org/csdl/mags/cs/2017/02/mcs2017020014.html Figure 1: Computation vs A Neuromorph’s Prospectus by K. Boahen communication signals https://www.computer.org/csdl/mags/co/2017/01/mco2017010020.html

30 HiPEACINFO 51 Tech Entrepreneur

Thinking about converting your research results into market-ready products and services? As Director of Commercialisation at the University of Edinburgh from 2006 to 2016, Colin Adams presided over the creation of 70 spin-outs and start-ups which collectively raised over e 250 million in equity investment. Here he explains why and how you should be a technology entrepreneur. Keep the revolution going

Technological innovation has a history of Europe has a very good record of making changing the world in major ways and scientific breakthroughs and though we making a real impact on society. Just think have made great strides in turning these of the British Agricultural Revolution of into products people and companies find 1700 and the Industrial Revolution of useful, it is an area in which we ought, 1780 – they were all about changing the and need, to do better. We have tended to basic way in which people worked and lag behind the USA in this dimension. A produced things by innovatively applying number of reasons have been put forward and scaling the technology breakthroughs as to why this has been the case: of the time. We have been in a compu­ tation-driven revolution for some decades; We do not have as large a single market it drives much of the modern economy as the USA and compe­titiveness for the countries in That ought not to be true if we take the which we live. How do we keep the European Union (EU) single market into revolution going? account. In the digital domain a global market is accessible instantly through the For those currently doing interesting internet. As we look at the geographic scientific research, it is a good idea to take addressable market we do need to some time to look at how their findings consider the wider global market – not might be used by companies and indivi­ just our individual country. dual consumers: seeing someone using the results of your labours and insights is The USA has easier access to venture just as satisfying as getting a best paper capital and investment award. It can be a lot of fun, evange­lizing This is no longer the case with a number the technology area you enjoy and having venture funds and angel investment a wider group of people understand and groups now active throughout Europe. As appreciate it more. It can also be financially of the end of 2016 we have 47 unicorns rewarding. (start-up companies with a valuation >$ 1 billion) in Europe, with an average investment of some $ 260 million each. So A vision in silicon there is investment capital available to be Tech entrepreneur Peter Denyer invented won. the silicon optical sensor, now used in most digital cameras. He founded VLSI The USA has more technical talent and Vision and sold it to ST Microelectronics, knowhow before founding a number of other Europe has a huge talent pool both in the companies. technical and entre­preneurial domain.

HiPEACINFO 51 31 Tech Entrepreneur

The strength of our research and univers­ If you do have some technology you think business experience and contacts, so you ities is key. There is also a growing band of you would like to commercialize, first have people to provide feedback on your seasoned technical entrepreneurs who work up a very simple working prototype ideas for a business plan and how to already have at least one success under of what you think people would use. Find develop the commercial side. their belt and are available to mentor and a couple of potential customers (preferably help new comers. not co-researchers) and try it on them so An interesting thought in the space we you get some feedback. Listen to their address in the HIPEAC community is what So there is no reason why we should not input and modify your approach based on happens next to keep Moore’s law – and make even more headway in turning the that. The prototype can also be used to with that the technology revolution – world-leading research that this show potential investors what you have in moving forward. I had an interesting community has been carrying out into mind, and to people you may want to conversation with Steve Jurvetson recently. innovative products. recruit onto your team. He is one of Silicon Valley’s most successful investors and he came up with the 120 The other area to think through is how year view of Moore’s Law shown below. Improbable sums you protect the intellectual property in Now, does your research give guidance to The founders of the UK virtual reality your invention, e.g. by patenting some how that curve continues? If so, you could start-up Improbable Worlds, Herman element of it, so others don’t capitalize on have something very valuable – so start Narula, Rob Whitehead and Peter Lipka, your efforts without you gaining anything thinking about how to commercialize it. recently raised $520 million from Softbank. from it. The company is now reported to be valued Colin Adams is delivering the Technology at over $1 billion. Between them, the three If you are looking at seriously pursuing Innovation and Entrepreneurship course at founders hold more than 50% of the equity. this route, I would advise seeking out the HiPEAC summer school ACACES17. some business mentors who have solid http://bit.ly/ACACES17_ColinAdams

32 HiPEACINFO 51 Industry focus

Leonel Sousa, Aleksandar Ilic’ and Frederico Pratas of the University of Lisbon describe how they developed a simple way to visualize the limits of parallel processing, which has been integrated into Intel® Advisor. Cache-aware Roofline Model in Intel® Advisor A bird’s eye view for parallel processing

As computing systems evolve towards In 2017, a team of Intel software deve­ complex multicore designs with deep and lopers (leaded by Zakhar Matveev, Roman diverse memory hierarchies, improving Belenov and Philippe Thierry) successfully the performance and optimizing the exe­ integrated the performance Cache-aware cution of real-world applications become Roofline model as an official feature of of fundamental importance. In high- Intel® Advisor, which is part of the Parallel performance computing environments,­ it Studio XE suite (Intel’s main application is crucial, but not trivial, to determine development frame­work). Within Intel® which hardware resources represent the Advisor, the process of building the roof­ main execution bottlenecks that limit the line plots and in-depth application charac­ application performance, especially when te­rization are fully automatized with deciding on the most adequate software res­pect to the hardware platform where optimization technique to be applied. the applications are executed. The support for a wide range of Intel devices is also To support this decision process, Aleksandar provided, which covers all contempo­rary Ilic, Frederico Pratas and Leonel Sousa, Intel CPU micro-archi­tectures (from researchers from INESC-ID, Instituto Nehalem to Skylake) up to massively “The models evaluate Superior Técnico, University of Lisbon, and parallel devices (e.g., Intel Xeon Phi how key micro- members of HiPEAC, proposed a set of Knights Landing). fundamental Cache-aware Roof­line architectural aspects models, which provide a simple and affect upper-bounds for intuitive way of visually representing the performance” limits of parallel processing on contem­ porary multicore processors.

These models evaluate how key micro- archi­tectural aspects, such as accessing different­ functional units or different memory hierarchy levels, affect realistically achievable­ upper-bounds for performance, power consumption and energy-efficiency on a given multicore architecture. They have been used to characterize the behaviour and improve the efficiency of several real-world applications, e.g. in the A brief overview of the Cache- areas of scientific computations and aware Roofline in Intel® Advisor bioinformatics.­ The performance Cache-aware Roofline is plotted with the X axis as Arithmetic

HiPEACINFO 51 33 Industry focus

Cache-aware Roofline in Intel® Advisor

Intensity (measured in FLOPs/Byte) and time, so are likely not worth optimizing; the Y axis as the performance in GFLOPs/ large, red dots take up the most time, so Second, both in logarithmic scale. Before they are the best candidates for optimi­ collecting data of a specific application, zation, especially the ones with a large Intel® Advisor automatically runs a set of gap to the topmost attainable roofs. In quick benchmarks to measure the hard­ general, the farther a dot is from the ware limitations of the used processor, topmost roofs, the more room for improve­ which it then plots as lines on the chart, ment there is. For example, the Scalar Add called roofs (see Figure 1). The horizontal Peak represents the maximum possible lines represent the number of floating performance without taking advantage of point computations (of a given type) that vectorization, as indicated by the next ‘The Intel Advisor offers the underlying hardware can perform in a roof up being the Vector Add Peak. given span of time. The diagonal lines are a great step forward in representative of how many bytes of data Where can I get Intel® Advisor memory performance a given memory hierarchy level can with Cache-aware Roofline? optimization with deliver per second. As stated in the Intel early access pro­ gramme, ‘the Intel Advisor offers a great a new vivid Advisor Each dot represents a loop or function in step forward in memory performance opti­ “Roofline” bounds and the program, and its position in the mization­ with a new vivid Advisor bottlenecks analysis’ Roofline plot indicates performance and “Roofline” bounds and bottlenecks ana­ Arithmetic Intensity. The size and colour lysis’. Cache-aware Roofline is currently a of the dots in Intel® Advisor’s Roofline feature of Intel® Advisor beginning chart indicate how much of the total officially with version 2017 Update 2, program time a loop or function takes. which is part of the Parallel Studio XE suite Small, green dots take up relatively little (Cluster Edition and Professional Edition).

Further reading A. Ilic, F. Pratas, and L. Sousa. ‘Cache-aware Roofline model: Upgrading the loft.’ IEEE Computer Architecture Letters, vol. 13, n. 1, pp. 21-24, 2014. ‘Beyond the Roofline: Cache-aware Power and Energy-Efficiency Modeling for Multi-cores.’ IEEE Transactions on Computers, vol. 66, n. 1, pp. 52-58, 2017. Intel. (2017) Intel® Advisor Roofline http://bit.ly/Intel_Advisor_Roofline Intel. (2017) Intel Parallel Studio XE http://bit.ly/Intel_Parallel_Studio_XE

34 HiPEACINFO 51 SME snapshot

From hobby project to building the world’s fastest electric car, Rimac Automobili is a high-octane success story. Here, Chief Human Resources Officer Aco Momcˇilovic’, Director of Components Matija Gracin and Marketing Assistant Marta Longin show how this company punches above its weight and give an insight into why it is a great place to work. The drive to succeed COMPANY: Rimac Automobili Accelerating from 0-100km/h in just 2.5 seconds, the cars have MAIN BUSINESS: Creating next generation beaten even top supercars in test races. electric hypercars; providing full solutions Check out the Concept_One beating LaFerrari in this video: to global original equipment manufacturers, http://bit.ly/Rimac_ConceptOne-LaFerrari. from high-performance electric vehicle components to turnkey solutions LOCATION: Sveta Nedelja, Croatia WEBSITE: www.rimac-automobili.com

The seeds for the company were first planted back in 2007, when Mate Rimac started tinkering with his BMW E30 as a hobby, after the car’s engine blew up during a race. When he managed to give it an electric powertrain – the engine and transmission – the project soon attracted press interest. In total, Mate broke five Fédération Internationale de l’Automobile and Guinness World Records for the fastest accelerating electric car with this The Rimac Concept One has beaten LaFerrari prototype, affectionately known as the ‘Green Monster’. Wanting to develop a more powerful version, Rimac brought together a Rimac is fortunate to benefit from a great team and we’ve been team of experts to develop their own components, in order to working with the education system in Croatia to help prepare deliver genuinely high-performance electric propulsion. Thanks engineers with the requisite skills. As a smaller company, at to selling patents and gaining financing from angel investments, Rimac you have the satisfaction of working on the whole lifecycle Rimac Automobili was founded in 2009. of the product, from design, to production, to testing. This is contrast to working at a large multinational where you would likely be working on one small part of the development. Rimac is currently looking for top-quality staff, with roles encompassing everything from battery engineering to embedded engineering.

We are seeking software engineers for embedded systems development, from the initial idea to the final product. Candidates should have C/C++ programming skills, familiarity with basic electronic circuits and basic knowledge of communication protocols. Experience with real-time operating systems and embedded systems projects experience are more than a plus. We are also recruiting an embedded hardware engineer, who should The ‘Green Monster’ was the original Rimac prototype have knowledge of electronic components and systems, the programming language C and communication protocols (UART, Lovingly crafting each car in house – including everything from SPI, I2C, CAN...). the battery to the transmission to the infotainment system – the team built on their knowledge from developing the BMW E30 Interested in working at Rimac Automobili? Check out the vacancies on prototype to create first the Concept_One and then the Concept_S. the HiPEAC Jobs Portal: hipeac.net/jobs

HiPEACINFO 51 35 HiPEAC futures Career talk: Michael Hübner, Ruhr-Universität Bochum

What first got you interested in computer Can you describe some highlights of your science? career so far? My interest began a long time ago. I think my One highlight in my career was my decision to career started with the first computer my father study. I was doing a job in the electronics field bought me. It was a very small Texas Instru­ and came to a point where I needed to choose ments (TI) processor-based system which was to study or stay on the path I was on. It was not programmed with hexadecimal code. Later I easy for me because I gave up a permanent had a TI 99/4A and then of course a Commodore position in order to embark on the ‘adventure’ C64. I was born at a time when computer of studying. What made it even more daunting systems developed very quickly in a very short was that, at the time, there were no guarantees period of time, a phenomenon which has that it would become a job. Later, after finishing continued up to the present day. A fascination my diploma, it was thanks to my former PhD with novel systems, processor system trends advisor believing in me that all other steps and energy optimization has kept my interest were possible. Now, I have the best job I could all this time. wish for as a professor at Ruhr-Universität Bochum . What makes embedded computing an exciting field to work in? What makes Europe a great place to work? I think embedded systems is the most important I think Europe is an excellent place to work, as domain, both for industry and academia. We there is a network of excellent researchers and are seeing trends where embedded technology exchange of knowledge and experience is easily is even entering the realm of high-performance achieved. In my group at Bochum I always computing due to the effectiveness of perfor­ have researchers from Europe, but also from all mance per watt. Trends like cyber-physical over the world. We like to discuss issues with systems (CPS) and the internet of things (IoT) other researchers and Europe is an excellent enable better processor systems in terms of platform to do so. Funding oppor­tunities, ultra-low power and normally high real-time mostly the European Commission ICT calls, are capability. This is leading to changes in many often an especially good way to collaborate. fields. Embedded systems form the ‘motor’ which drives megatrends in machine learning, What advice would you have for researchers CPS and IoT. embarking on their careers now? I think the most important thing is to stay curious and open minded, and never be restrictive with sharing knowledge. Teamwork is important, as is supporting activities like EUROPRACTICE (www.europractice-ic.com) which offers microelectronic and micro­system design, prototyping, production and test services. EUROPRACTICE is an extremely important source of support for researchers in Europe and I hope it continues for a long time.

The TI 99/4A was one of Michael’s first Michael Hübner is delivering a course titled computers ‘Reconfigurable Hardware, Tools and Applica­ Photo credit: Manolis Klaglas, Flickr tions’ at ACACES 2017 creativecommons.org/licenses/by-nc-sa/2.0 http://bit.ly/ACACES17_MichaelHuebner

36 HiPEACINFO 51 HiPEAC futures

Collaboration grants allow PhD students and junior post-doctoral researchers within the HiPEAC network to work jointly with a new research group to work on key challenges for computing systems. For further information about how to apply, visit www.hipeac.net/mobility/collaborations. Creating the future through international exchange: HiPEAC collaboration grants

NAME: Joshua Lant This collaboration resulted in documentation on the details of RESEARCH CENTRE: University of Manchester UNIMEM, with particular focus on the ways in which the memory HOST INSTITUTION: Foundation for Research model affects the programmability of the hardware and the and Technology Hellas differences between the ideal UNIMEM model and the current DATES OF COLLABORATION: implementation. Using the Vivado toolchain, we also created 26/07/2016 - 28/10/2016 hardware designs which measure the performance of the custom Epic memories: When Manchester AXI interconnect with traffic generators. This has been met ‘Silicon Island’, Crete implemented and run successfully on the Ultrascale+ hardware.

Real performance metrics can now be gathered and the design The Horizon2020 ExaNeSt project is developing and prototyping improved to meet higher performance constraints, with more network, storage and cooling solutions to make exascale com­ interesting features of the interconnect design being added and puters – those capable of a billion billion calculations per second tested. The aim is to publish the results of the implementation – feasible. To help achieve this, ExaNeSt uses UNIMEM: a form of and performance characteristics of these more advanced features. global address space that allows multiple boards to share memory regions between them and to communicate at low overhead and The scope for future collaboration is very wide, considering that low energy consumption. UNIMEM was developed during the ExaNeSt works closely together with the ExaNoDe and EcoScale EU-funded EUROSERVER project, which ended earlier this year. projects, which will all run until late 2018, and then the new EuroEXA project will continue along the same lines until early I spent three months at FORTH to learn about the technical 2021. Developing networks with the people at FORTH has been details of the UNIMEM memory model, its limitations and its highly beneficial. Now that I’ve spent time with specific members implementation on the Xilinx Ultrascale+ architecture. During of the team with specific skills at FORTH, it will be much simpler this time I also investigated the requirements of the interconnect to find avenues where FORTH and Manchester may assist one to properly allow the use of UNIMEM. In addition, I worked to another on specific parts of the project as work progresses. advance the design on FPGA of a custom AXI-based interconnect for use in the ExaNeSt project at the daughtercard level, and Manolis Katevenis of FORTH commented: ‘Joshua’s visit was an implementation and testing of this design on Ultrascale+ important step in furthering our collaboration with the University hardware at FORTH. of Manchester, especially on Interprocessor Communication protocols – a key component for the Modularity of Silicon that future technologies demand.’

He added: ‘This collaboration builds on FORTH’s strong tradition of working with colleagues across Europe in R&D projects, which has already yielded great results. Last year, for example, FORTH attracted to Crete a Development Lab of the start-up KALEAO, co-founded by University of Manchester professor John Goodacre. Dubbed ‘Silicon Island’, Crete offers great opportunities for We look forward to continue this strong relationship to help young computer scientists deliver the exascale machines that Europe desperately needs.’

HiPEACINFO 51 37 HiPEAC futures

Every year, HiPEAC company members propose topics for internships, which are then funded or part funded by the project. This year, there was a record number of internships and applicants. For further information, visit the HiPEAC website: hipeac.net/mobility/internships. In his internship, Hamzeh Ahangari helped Embedded Computing Specialists lay the groundwork for a safety-qualified embedded system in the transport domain. HiPEAC internships: your career starts here

NAME: Hamzeh Ahangari During this internship, we did a prelimi­ for reaching the standards’ safety levels. RESEARCH CENTRE: Bilkent nary study of the required standards for We also implemented a draft version of a University implementing safety-critical electronic compact printed circuit board for Xilinx HOST COMPANY: Embedded systems. There are several such standards, Zynq FPGA. Computing Specialists including IEC61508, DO-178, etc, each of DATES OF INTERNSHIP: which addresses a particular domain. From The main aim was to assess the feasibility 06/11/2016 - 03/02/2017 these documents, the main parameters­ of designing and manufacturing a safety- addressed were identified and investigated. qualified embedded system for the Transport safety as standard These include component failure rates, transportation industry. With the prelimi­ common cause failure rate, diagnostic nary study phase and part of the FPGA Safety-critical computers are used exten­ coverage factor, repair rate and so on. system implementation complete, I hope sively in many civil domains, such as the that we will be able to continue working automotive sector, rail transport and The second step was to focus on choosing together on such systems in future. avionics. While general, safe microcon­­ the platform. Unlike existing systems, trollers with limited processing capabi­ which are usually implemented in Embedded Computing Specialists co-foun­ lities are available on the market, safe commer­cial-off-the-shelf processors, like der Philippe Manet commented: ‘This processors with intensive processing capa­ those from Texas Instruments or NXP, we HIPEAC internship allowed us to quickly bilities should be designed and tailored to wanted to check the feasibility of imple­ understand key aspects of certification in the specific application requirements. menting such systems on high-perfor­ our business, thanks to the expertise and Such designs are always based on com­ wwmance FPGAs like Xilinx Zynq. We previous experience of Hamzeh. It allowed ponent-level or system-level redundancies. undertook a thorough investigation of the us find the right strategy to handle this facilities that FPGA manufacturers provide complex issue.’

“The main aim was to assess the feasibility of designing and manufacturing a safety-qualified embedded system for the transportation industry”

38 HiPEACINFO 51 HiPEAC futures

Continuing our series highlighting the work of HiPEAC’s 800-strong network of PhD students, in this issue we focus on memory controller architecture for real-time applications.

Three-minute thesis

NAME: Yonghui Li serve the variable-sized requests by dynamically scheduling the RESEARCH CENTRE: Eindhoven University of proper number of memory commands to SDRAM at run-time Technology (Run-DMC). Thanks to the dynamic scheduling scheme, the ADVISERS: Professor Kees Goossens and memory commands for successive requests are pipelined, Dr Benny Akesson resulting in higher efficiency than static command schedules for THESIS TITLE: Design and Formal Analysis of requests. To guarantee the worst-case response time and Real-time Memory Controllers bandwidth, three analysis approaches are presented, including a mathematical formalization, a dataflow model, and a timed Featured research: Memory access control automata model, respectively. These models have different which is right on time properties that support the simulation, validation and verification of the memory controller. Heterogeneous multicore computing platforms are becoming increasingly popular to achieve the necessary computational This dissertation is the first to explore and compare different power without using too much energy. These platforms analysis approaches to obtain the worst-case response time and simultaneously execute multiple applications that interact with bandwidth of real-time memory controllers. The experimental the physical world. The applications typically have real-time results demonstrate that the proposed dynamically-scheduled requirements, such as a time deadline or a throughput constraint, memory controller is more efficient than existing (semi-)static which must be satisfied to ensure the safety or performance of controllers for requests with variable sizes, and the derived the applications. worst-case results are tightly bounded.

However, it is very challenging to satisfy the real-time Models Worst-Case Analyses Tools requirements of each application because of the complex Timed Automata TA interference caused by resource sharing in the platform. In model (TA) analysis particular, synchronous dynamic random-access memory (SDRAM) stores the data and instructions in the platform and is Mode-controlled MCDF Ericsson accessed by other resources issuing read or write memory dataflow model Analysis Heracles (MCDF) (Collision) requests. It is one of the most shared resources and hence has Scheduled great impact on the timing behavior of applications. approach (ALAP) Mathematical RTMemCtrl: model Open source This dissertation addresses two critical issues: 1) how to Analytical efficiently serve memory requests with variable sizes, which are approach (ALAP & generated by heterogeneous resources in the platform, and 2) Cycle-accurate Collision) SystemC model how to guarantee the worst-case response time and bandwidth Simulator when accessing SDRAM, such that application requirements can low high equal Worst-case Correspondence be satisfied. A new memory controller architecture is proposed to Validation Accuracy witness

HiPEACINFO 51 39 Dates for your diary

2017

25 July 2017 HPCA 2018 (Vienna) abstract submissions HiPEAC Paper Award conference 4 August 2017 hpca2018.ece.ucsb.edu ASPLOS 2018 (Williamsburg, VA, USA) abstract submissions HiPEAC Paper Award conference asplos2018.org/calls

2017 A Photo: JL Cernadas, Flickr creativecommons.org/licenses/by/2.0 28 August - 1 September 2017 Euro-Par 2017 Santiago de Compostela, Spain europar2017.usc.es

4 - 8 September 2017 FPL 2017 Ghent, Belgium fpl2017.org

11 - 13 September 2017 2017 ARM Research Summit

Photo: Zaprittsky, Flickr Photo: Zaprittsky, creativecommons.org/licenses/by/2.0 Cambridge, UK 6 - 8 September 2017 developer.arm.com/research/summit ACM Europe Conference 2017 ft. HiPEAC Barcelona, Spain 2017 EPEE acmeurope-conference.acm.org Photo: Yuri Virovets Photo: Yuri creativecommons.org/licenses/by/2.0 12 - 15 September 2017 15 September 2017 ParCo 2017 PDP 2018 (Cambridge, UK) Bologna, Italy paper submissions parco.org bioinfo.itb.cnr.it/pdp2018/call.html