Advanced Synthesis Cookbook

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Advanced Synthesis Cookbook Advanced Synthesis Cookbook 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01017-6.0 Document last updated for Altera Complete Design Suite version: 11.0 Document publication date: July 2011 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Advanced Synthesis Cookbook July 2011 Altera Corporation Contents Chapter 1. Introduction Blocks and Techniques . 1–1 Simulating the Examples . 1–1 Using a C Compiler . 1–2 Chapter 2. Arithmetic Introduction . 2–1 Basic Addition . 2–2 Ternary Addition . 2–2 Grouping Ternary Adders . 2–3 Combinational Adders . 2–3 Double Addsub/ Basic Addsub . 2–3 Two’s Complement Arithmetic Review . 2–4 Traditional ADDSUB Unit . 2–4 Compressors (Carry Save Adders) . 2–5 Compressor Width 6:3 . 2–5 Compressor Width 3:2 . 2–5 Compressor Width 12:4 . 2–5 Compressor Width 36:6 . 2–6 Compressor Width 64:7 . 2–6 Combining Compressors (Compressor Width 4:2) . 2–6 Bit Population Count . 2–7 Splitting Adder Chains . 2–7 Pipelined Adder Chains . 2–8 Carry Select Adders . 2–8 Adder Trees . 2–9 Basic Multiplication . 2–10 Multiplication With Rotate and Shift Modes . 2–11 High-Speed LCell-Based Multiplication . 2–11 Multiplication of Large Integers (Karatsuba Algorithm) . 2–13 Division (Unsigned Integer) . 2–15 CORDIC . 2–16 Chapter 3. Floating Point Tricks Floating Point to Fixed Point Conversion . 3–1 Approximate Square Root . 3–1 Approximate Inverse Square Root . 3–2 Approximate Floating Point Divide (Single Precision) . 3–2 Chapter 4. Translation and Format Conversion One-Hot Decoder (Binary to One-Hot) . 4–1 One-Hot to Binary . 4–1 Mask Generation . 4–1 Binary-to-Gray Conversion . 4–2 Gray-To-Binary Conversion . 4–3 Seven Segment Display Driver . 4–3 Binary-to-ASCII Hexadecimal Conversion . 4–4 ASCII to 32 Character Liquid Crystal Display (LCD) . 4–4 July 2011 Altera Corporation Advanced Synthesis Cookbook iv Contents ASCII Hexadecimal-to-Binary Conversion . 4–5 Binary-to-Decimal/Binary-Coded Decimal Adders . 4–5 Chapter 5. Video YCbCr (4:4:4) to RGB Conversion . 5–1 RGB to Hue Conversion . 5–1 Sum of Absolute Difference (SAD) . 5–2 VGA Monitor Control . 5–3 Character Display . 5–4 Chapter 6. Arbitration Bitscan (Priority Masking) . 6–1 Arbiters with Fairness . 6–1 Priority Encoding . 6–2 Channel Arbiter . ..

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