Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation Jean-Christophe Prévotet
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Jean-Christophe Prévotet. Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation. Hardware Architecture [cs.AR]. Université de Rennes1, 2019. tel- 02415974
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Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation
Jean-Christophe Prévotet
Maître de Conférences à l’INSA de Rennes Laboratoire IETR / Équipe de recherche SYSCOM
A soutenir le 07/06/2019 devant le jury composé de
Rapporteurs Diana Göhringer Professeure au TU, Dresden Christophe Jégo Professeur à ENSEIRB-MATMECA, IMS, Bordeaux Gilles Sassatelli Directeur de recherche CNRS, LIRMM, Montpellier Examinateurs Guy Gogniat Professeur à l’université de Bretagne-Sud, Lab-STICC Christophe Moy Professeur à l’université de Rennes 1, IETR Frédéric Pétrot Professeur à l’université de Grenoble, TIMA Fabienne Nouvel Maître de conférences HDR, INSA de Rennes, IETR
Sommaire
Part. II 1 Synthesis of Research Works ...... 1 Preliminaries...... 3 111 Introduction ...... 4 Chap. 1 Summary of studies ...... 4 1.1 OS Modelling ...... 4 1.2 Reconfiguration Management ...... 5 1.3 Power Modelling ...... 6 2 Historical Research Background ...... 7 2.1 PhD Studies ...... 7 2.2 ETIS 2002-2007 ...... 7 2.3 IETR 2007- Today ...... 7 222 From OS Modelling to Implementation ...... 9 Chap. 1 Context and Related Works ...... 9 2 A new Design Methodology for Operating Systems ...... 11 2.1 System Specifications ...... 12 2.2 The Dogme Tool ...... 14 3 OS Model Description ...... 14 3.1 Task Manager Service ...... 15 3.2 Scheduling Service ...... 16 3.3 The IRQ Manager Service ...... 16 3.4 The Communication Service ...... 16 3.5 The Intercommunication Service ...... 16 3.6 The Reconfiguration Management Model ...... 17 3.6.1 The HW Task Concept ...... 18 3.6.2 The Dispatcher ...... 18 3.6.3 The placer ...... 19 3.6.4 The Offloader ...... 19 4 Modelling Evaluation ...... 20 4.1 Description ...... 21 4.2 System Model ...... 22 4.2.1 Application Model ...... 22 4.2.2 Architecture Model ...... 23 4.2.3 Kernel Model ...... 23 4.3 Simulation and results ...... 24 5 OS Code Generation ...... 25 5.1 OS Meta-model ...... 26 5.2 Model to Model Transformation ...... 27 6 From the OS to the Hypervisor ...... 27 6.1 Is virtualization compatible with real time constraints ? ...... 27 6.2 Virtualization Overhead ...... 29 6.3 Overhead aware schedulability analysis ...... 30 6.4 Proposal : Ker-ONE : A lighweight Micro-Hypervisor ...... 33 iii Sommaire
6.4.1 Overview ...... 33 6.4.2 Resource Virtualization ...... 34 6.4.3 Event Management ...... 35 6.5 Performance Evaluation ...... 35 6.5.1 Basic Virtualization Functions Overhead ...... 35 6.5.2 RTOS Virtualization Evaluation ...... 38 7 Summary ...... 39 333 Reconfiguration Management ...... 40 Chap. 1 Context and Related Works ...... 40 2 General Framework ...... 45 3 HW Level ...... 45 3.1 HW Task Model ...... 45 3.2 PRR HW Management ...... 47 3.3 The PRR Monitor ...... 48 4 OS Level ...... 48 4.1 The Configuration Controller (Virtual Device Manager) ...... 48 4.2 Other OS services to handle reconfiguration ...... 49 4.2.1 The Parameters Provider ...... 50 4.2.2 The HW Updater ...... 50 4.3 The particular case of Virtualization : Security Mechanisms ...... 50 5 Application level ...... 51 5.1 Context ...... 51 5.2 Case study : VHA for WI-FI and WiMax heterogeneous networks ...... 52 5.3 The Adaptive Scoring System ...... 52 5.4 Towards a Smart Reconfiguration Management ...... 54 5.4.1 Overview ...... 54 5.4.2 Modules Description ...... 54 5.5 Results ...... 56 6 Performances Evaluation ...... 57 6.1 Overhead Analysis ...... 59 6.2 Experiments and Results ...... 60 6.2.1 Description ...... 60 6.2.2 Results ...... 61 7 Summary ...... 62 444 From Power Modeling to highly Energy-Efficient Devices ...... 64 Chap. 1 Context and Related Works ...... 64 2 The Classic Implementation Approach ...... 67 2.1 Studying New Waveforms ...... 68 2.2 Proposed Offline Hardware Platform ...... 69 2.2.1 System Description ...... 69 2.2.2 Studied configurations ...... 70 2.2.3 Results ...... 71 2.3 Studying the SW limitations ...... 73 2.4 The Receive Spatial Modulation scheme ...... 77 2.4.1 Prototype Description ...... 77 2.4.2 Results ...... 78 3 Evaluation of FPGA-Based Wireless Communications Systems ...... 79 3.1 Proposed approach ...... 80 3.1.1 Scenario Definition ...... 80 3.1.2 IP Characterization ...... 81 3.1.3 Modeling and High Level Simulation ...... 82 iv Sommaire
3.2 Use Case ...... 84 3.2.1 System Description ...... 84 3.2.2 Power Estimation ...... 85 3.2.3 Power Estimation Speed-Up ...... 86 4 Towards Fine grain Modeling ...... 86 4.1 Analytical Modeling ...... 86 4.2 Extension to other FPGA Devices ...... 87 4.3 Neural Networks based Modeling ...... 87 4.3.1 Model Definition ...... 89 4.3.2 Results ...... 90 5 Summary ...... 92 555 Research Perspectives ...... 93 Chap. 1 Embedded Systems Virtualization ...... 93 1.1 Hypervisor structure ...... 93 1.2 Reconfigurable Hardware Resources Sharing ...... 94 1.3 VM Scheduling and Off-Loading Service ...... 94 2 End to End Reconfiguration Management ...... 94 2.1 Multi-standards Reconfiguration ...... 95 2.2 Machine Learning ...... 95 3 Towards Energy-Efficient Communicating Devices ...... 96 3.1 New Waveforms ...... 96 3.2 Hardware Power Models ...... 96 3.3 From Device to Protocol ...... 97 Bibliography...... 99
v Sommaire
vi Partie I
Synthesis of Research Works
1
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PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX hsuecs a ensuidi h otx fteGRII,yugrsace rjc ncollaboration in project researcher young GDR-ISIS, a Laboratory. the Lab-STICC through of the receives context of it the Conde-Canencia signals Laura in with the studied decode been to has is use-case This mission whose terminal (see a channel wireless of consists system proposed The of behaviour The areas. the be all will HwTask among end-time new estimated the estimated earliest in which latest the represented in the is with area is algorithm group) area, the candidate (or an the correspon- area of their Then the thus HwTasks is with . and HwTasks contained placed, group, running the a of all of which group end-time among in a estimated end-time areas comprises The of times. area list end Each running a estimated all placed. furnishes ding among be algorithm end-time can estimated placement HwTask earliest the new the hardware, find the reconfigurable to required of is case it In case, HwTasks processors’ . of set case the HwTasks. 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(in throughput maximum the as defined is nti otx,hg-re ouainshmsadpwru ro-orcigcodes error-correcting powerful and schemes modulation high-order context, this In techniques these hand, one On techniques. special implement systems these of Most shows 2.9 Description T 1 ABLE orsod oaQS ouain( )ad( /)o MCS or 1/2) = (R and 4) = (M modulation QPSK a to corresponds η safnto fSRfrtodcdr n w ye fcanl sn h ACM the using channels of types two and decoders two for SNR of function a as MS nteWMX821msadr.Suc [CCEPO12] Source standard. 802.16m WiMAX the in MCSs – 2.6 ,1,1,12 11, 10, 9, ,6 ,8 7, 6, 5, 4 3, 2, 1, MCS iue61 h agtsystem target The 6.1: Figure F IGURE Modulation 64-QAM 16-QAM η QPSK Tre system. Target – 2.8 R = 21 ∗ 95 log 2 M /,23 /,5/6 3/4, 2/3, 1/2, 5/6 3/4, 2/3, 1/2, 5/6 3/4, 2/3, 1/2, oerate Code Table 7 orsod oa to corresponds hc sto is which 2.6, ffi inyfra for ciency ffi ciency
PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX h sensor The PARCOURS other P In ROFESSIONNEL changes. signals. configuration received the despite the operation decode the continuously interrupt to not able should system is the it words, if paths. guaranteed multiple is e.g. two system channel, of the 10 transmission of last effects the pause side between to this due S in case, is and our This YNTHESISOF frame In required. a is pause to a equivalent frames, is signal each Moreover, RESEARCH WORKS APPENDIX SYSTEM TARGET THE OF DESCRIPTION 6.1. h eaiu ftercie srpeetdi iue63 h orcns fthe of correctness The 6.3. Figure in represented is receiver the of behaviour The iue62 pcrlecec safnto fteSRwt C.Suc [80] Source ACM. with SNR the of function a as efficiency Spectral 6.2: Figure h N.Weee h hne odtoschange, conditions channel the Whenever SNR. the .Nt htteClmsadRw fteMStasks MCS the of Rows and Columns the time. that processing Note frame from [CCLJ12 the ]. extracted FPGA been to have Virtex5 respect sizes bitstream’s a with their as negligible on well as is implementation times task an a execution their this Assuming tasks, systems. of MCS communication the time Regarding of the implementations estimation, previous channel of basic results the to according estimated The The sensor The e side to due 10 is lasts This pause duration. this frames. case, two our of In transmission paths. multiple the between required is pause 4.2.1 Table : following the are system the constitute that tasks The MCS MCS iso.Weee hneo h hne’ odtosi eetd hsts eoe h current the becomes task this detected, is conditions channel’s the MCS. on change a Whenever mission. fec rm,tets ssseddfrteitrfaetm.Atrtepue MCS by pause, indicated the itself. been deletes After has time. change inter-frame channel a the time for by suspended required is is that task MUTEX the frame, each of Afterwards, transmission. change, conditions channel the ver 4.2 F n c IGURE ts a been has task sensor the of time execution The task. system each of attributes the lists 2.7 aki epnil o npcigtetasiso hne n estimating and channel transmission the inspecting for responsible is task plcto Model Application akrpeet h C ceeta sbigue o h urn rnmsin tteend the At transmission. current the for used being is that scheme MCS the represents task akrpeet h C ceeta a encngrdb the by configured been has that scheme MCS the represents task aki epnil o npcigtetasiso hne n siaigteSR Whene- SNR. the estimating and channel transmission the inspecting for responsible is task ytmModel System iue63 tt ahn ftecs td scenario. study case the of machine State 6.3: Figure Seta e Spectral – 2.9 sensor ffi sensor inya ucino h N ihAM ore[CCEPO12 ] Source ACM. with SNR the of function a as ciency µ ,wihi prxmtl 0 ftefaesduration. frame’s the of 10% approximately is which s, ok naMTXutltenx rnmsini started. is transmission next the until MUTEX a on locks oidct htanwtasiso sgigt esatd Every started. be to going is transmission new a that indicate to , sensor hpte2 rmO oeln oImplementation to Modelling OS From 2. Chapitre µ s ofiue h C hti h otsial o h next the for suitable most the is that MCS the configures hc orsod prxmtl o1%o h frame’s the of 10% to approximately corresponds which , 22 sensor the , MCS c ciae h etMSshm and scheme MCS next the activates sensor
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Figure in illustrated as meta-model, RTOS structural the of instance model Af meta-model. a RTOS structural by the used in present entity ”Service” the and model conforms to model- a called is discipline. technique engineering This model-driven the in model. transformation RTOS structural a into model simulation SoC oceey ecet apn ewe h Cmoet niypeeti th in present entity ”Component” the between mapping a create we Concretely, hspoescudb uoaial ple naysmlto oe ntneo th of instance model simulation any on applied automatically be could process This hstcnqerle ntefc htaymt-oe smnaoydfie us defined mandatory is meta-model any that fact the on relies technique This OveRSoC RTOSOveRSoC model n aheeetfo a from element each and meta-model RTOS OveRSoC F rnfrainengine transformation IGURE oatmtclypouetefia xctbeprograms. executable final the produce automatically to A conforms to n aheeetfo meta-model a from element each and Mdlt oe rnfrainprocess. transformation model to Model – 2.14 iue51:Mdlt-oe rnfrainprocess. transformation Model-to-Model 5.11: Figure µ ocnetamdlisac fteOeSCmt-oe noa into meta-model OveRSoC the of instance model a convert to O-I.Ti oicto sncsaybcuetefia source final the because necessary is modification This cOS-II). eamdlB meta-model M Transformation Engine ta transformation conforms to Object FacilityObject mapping mapping ffi 27 122 inyo ita ytm ntrso efrac and performance of terms in systems virtual of ciency rnfrainengine transformation sln sbt eamdl r endusing defined are meta-models both as long as Figure RTOS structuremodel conforms to ffi meta-model RTOS structure 2.14. in ntecs hr hr sonly is there where case the in cient rdc sa upta output an as produce , B sln sbt eamdl are meta-models both as long as e ht hsrl is rule this that, ter vro meta- OverSoC e n h MetaOb- the ing tfo a from nt h developed the e recd of code urce OveRSoC e to-model meta-
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average release-delay in milleseconds average release-delay in milleseconds 1000 1500 2000 2500 1000 1500 2000 2500 500 500 0 0 . 1 1 deadline task4:2400.0ms faproi ak hc stedifference the is which task, periodic a of VM 2 2 2 . VM(160ms,200ms),task3(300ms,1200ms)&task4(400ms,2400ms) Task set2executedonaLinux-PREEMPT_RTusingonekvmVM VM(160ms,200ms),task1(30ms,150ms)&task2(50ms,200ms) 3 3 Task set1testedonaLinux-PREEMPT_RTusingkvmVM d ees delay Release (d) delay Release (b) 4 4 oosretebehavior the observe to r Number ofruns Number ofruns 5 5 DMR w eaaevirtual separate two n ns ie hnwe Then time. finish n ediems in miss deadline any iue41() Fig- 4.12(a), Figure 6 6 erct verify to metric o’ release job’s y 7 7 ia”release tical” task 3[dmr10.0%] task 4[dmr0.0%] task 2[dmr0.0%] task 1[dmr0.0%] deadline task3:1200.0ms deadline task1:1500.0ms deadline task2:2000.0ms ’s 8 8 verhead. release 9 9 10 10
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