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Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation Jean-Christophe Prévotet

To cite this version:

Jean-Christophe Prévotet. Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation. Hardware Architecture [cs.AR]. Université de Rennes1, 2019. ￿tel- 02415974￿

HAL Id: tel-02415974 https://tel.archives-ouvertes.fr/tel-02415974 Submitted on 17 Dec 2019

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Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation

Jean-Christophe Prévotet

Maître de Conférences à l’INSA de Rennes Laboratoire IETR / Équipe de recherche SYSCOM

A soutenir le 07/06/2019 devant le jury composé de

Rapporteurs Diana Göhringer Professeure au TU, Dresden Christophe Jégo Professeur à ENSEIRB-MATMECA, IMS, Bordeaux Gilles Sassatelli Directeur de recherche CNRS, LIRMM, Montpellier Examinateurs Guy Gogniat Professeur à l’université de Bretagne-Sud, Lab-STICC Christophe Moy Professeur à l’université de Rennes 1, IETR Frédéric Pétrot Professeur à l’université de Grenoble, TIMA Fabienne Nouvel Maître de conférences HDR, INSA de Rennes, IETR

Sommaire

Part. II 1 Synthesis of Research Works ...... 1 Preliminaries...... 3 111 Introduction ...... 4 Chap. 1 Summary of studies ...... 4 1.1 OS Modelling ...... 4 1.2 Reconfiguration Management ...... 5 1.3 Power Modelling ...... 6 2 Historical Research Background ...... 7 2.1 PhD Studies ...... 7 2.2 ETIS 2002-2007 ...... 7 2.3 IETR 2007- Today ...... 7 222 From OS Modelling to Implementation ...... 9 Chap. 1 Context and Related Works ...... 9 2 A new Design Methodology for Operating Systems ...... 11 2.1 System Specifications ...... 12 2.2 The Dogme Tool ...... 14 3 OS Model Description ...... 14 3.1 Task Manager Service ...... 15 3.2 Scheduling Service ...... 16 3.3 The IRQ Manager Service ...... 16 3.4 The Communication Service ...... 16 3.5 The Intercommunication Service ...... 16 3.6 The Reconfiguration Management Model ...... 17 3.6.1 The HW Task Concept ...... 18 3.6.2 The Dispatcher ...... 18 3.6.3 The placer ...... 19 3.6.4 The Offloader ...... 19 4 Modelling Evaluation ...... 20 4.1 Description ...... 21 4.2 System Model ...... 22 4.2.1 Application Model ...... 22 4.2.2 Architecture Model ...... 23 4.2.3 Kernel Model ...... 23 4.3 Simulation and results ...... 24 5 OS Code Generation ...... 25 5.1 OS Meta-model ...... 26 5.2 Model to Model Transformation ...... 27 6 From the OS to the ...... 27 6.1 Is compatible with real time constraints ? ...... 27 6.2 Virtualization Overhead ...... 29 6.3 Overhead aware schedulability analysis ...... 30 6.4 Proposal : Ker-ONE : A lighweight Micro-Hypervisor ...... 33 iii Sommaire

6.4.1 Overview ...... 33 6.4.2 Resource Virtualization ...... 34 6.4.3 Event Management ...... 35 6.5 Performance Evaluation ...... 35 6.5.1 Basic Virtualization Functions Overhead ...... 35 6.5.2 RTOS Virtualization Evaluation ...... 38 7 Summary ...... 39 333 Reconfiguration Management ...... 40 Chap. 1 Context and Related Works ...... 40 2 General Framework ...... 45 3 HW Level ...... 45 3.1 HW Task Model ...... 45 3.2 PRR HW Management ...... 47 3.3 The PRR Monitor ...... 48 4 OS Level ...... 48 4.1 The Configuration Controller (Virtual Device Manager) ...... 48 4.2 Other OS services to handle reconfiguration ...... 49 4.2.1 The Parameters Provider ...... 50 4.2.2 The HW Updater ...... 50 4.3 The particular case of Virtualization : Security Mechanisms ...... 50 5 Application level ...... 51 5.1 Context ...... 51 5.2 Case study : VHA for WI-FI and WiMax heterogeneous networks ...... 52 5.3 The Adaptive Scoring System ...... 52 5.4 Towards a Smart Reconfiguration Management ...... 54 5.4.1 Overview ...... 54 5.4.2 Modules Description ...... 54 5.5 Results ...... 56 6 Performances Evaluation ...... 57 6.1 Overhead Analysis ...... 59 6.2 Experiments and Results ...... 60 6.2.1 Description ...... 60 6.2.2 Results ...... 61 7 Summary ...... 62 444 From Power Modeling to highly Energy-Efficient Devices ...... 64 Chap. 1 Context and Related Works ...... 64 2 The Classic Implementation Approach ...... 67 2.1 Studying New Waveforms ...... 68 2.2 Proposed Offline Hardware Platform ...... 69 2.2.1 System Description ...... 69 2.2.2 Studied configurations ...... 70 2.2.3 Results ...... 71 2.3 Studying the SW limitations ...... 73 2.4 The Receive Spatial Modulation scheme ...... 77 2.4.1 Prototype Description ...... 77 2.4.2 Results ...... 78 3 Evaluation of FPGA-Based Wireless Communications Systems ...... 79 3.1 Proposed approach ...... 80 3.1.1 Scenario Definition ...... 80 3.1.2 IP Characterization ...... 81 3.1.3 Modeling and High Level Simulation ...... 82 iv Sommaire

3.2 Use Case ...... 84 3.2.1 System Description ...... 84 3.2.2 Power Estimation ...... 85 3.2.3 Power Estimation Speed-Up ...... 86 4 Towards Fine grain Modeling ...... 86 4.1 Analytical Modeling ...... 86 4.2 Extension to other FPGA Devices ...... 87 4.3 Neural Networks based Modeling ...... 87 4.3.1 Model Definition ...... 89 4.3.2 Results ...... 90 5 Summary ...... 92 555 Research Perspectives ...... 93 Chap. 1 Embedded Systems Virtualization ...... 93 1.1 Hypervisor structure ...... 93 1.2 Reconfigurable Hardware Resources Sharing ...... 94 1.3 VM Scheduling and Off-Loading Service ...... 94 2 End to End Reconfiguration Management ...... 94 2.1 Multi-standards Reconfiguration ...... 95 2.2 Machine Learning ...... 95 3 Towards Energy-Efficient Communicating Devices ...... 96 3.1 New Waveforms ...... 96 3.2 Hardware Power Models ...... 96 3.3 From Device to Protocol ...... 97 Bibliography...... 99

v Sommaire

vi Partie I

Synthesis of Research Works

1

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PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX h sensor The PARCOURS other P In ROFESSIONNEL changes. signals. configuration received the despite the operation decode the continuously interrupt to not able should system is the it words, if paths. guaranteed multiple is e.g. two system channel, of the 10 transmission of last effects the pause side between to this due S in case, is and our This YNTHESISOF frame In required. a is pause to a equivalent frames, is signal each Moreover, RESEARCH WORKS APPENDIX SYSTEM TARGET THE OF DESCRIPTION 6.1. h eaiu ftercie srpeetdi iue63 h orcns fthe of correctness The 6.3. Figure in represented is receiver the of behaviour The iue62 pcrlecec safnto fteSRwt C.Suc [80] Source ACM. with SNR the of function a as efficiency Spectral 6.2: Figure h N.Weee h hne odtoschange, conditions channel the Whenever SNR. the .Nt htteClmsadRw fteMStasks MCS the of Rows and Columns the time. that processing Note frame from [CCLJ12 the ]. extracted FPGA been to have Virtex5 respect sizes bitstream’s a with their as negligible on well as is implementation times task an a execution their this Assuming tasks, systems. of MCS communication the time Regarding of the implementations estimation, previous channel of basic results the to according estimated The The sensor The e side to due 10 is lasts This pause duration. this frames. case, two our of In transmission paths. multiple the between required is pause 4.2.1 Table : following the are system the constitute that tasks The MCS MCS iso.Weee hneo h hne’ odtosi eetd hsts eoe h current the becomes task this detected, is conditions channel’s the MCS. on change a Whenever mission. fec rm,tets ssseddfrteitrfaetm.Atrtepue MCS by pause, indicated the itself. been deletes After has time. change inter-frame channel a the time for by suspended required is is that task MUTEX the frame, each of Afterwards, transmission. change, conditions channel the ver 4.2 F n c IGURE ts a been has task sensor the of time execution The task. system each of attributes the lists 2.7 aki epnil o npcigtetasiso hne n estimating and channel transmission the inspecting for responsible is task plcto Model Application akrpeet h C ceeta sbigue o h urn rnmsin tteend the At transmission. current the for used being is that scheme MCS the represents task akrpeet h C ceeta a encngrdb the by configured been has that scheme MCS the represents task aki epnil o npcigtetasiso hne n siaigteSR Whene- SNR. the estimating and channel transmission the inspecting for responsible is task ytmModel System iue63 tt ahn ftecs td scenario. study case the of machine State 6.3: Figure Seta e Spectral – 2.9 sensor ffi sensor inya ucino h N ihAM ore[CCEPO12 ] Source ACM. with SNR the of function a as ciency µ ,wihi prxmtl 0 ftefaesduration. frame’s the of 10% approximately is which s, ok naMTXutltenx rnmsini started. is transmission next the until MUTEX a on locks oidct htanwtasiso sgigt esatd Every started. be to going is transmission new a that indicate to , sensor hpte2 rmO oeln oImplementation to Modelling OS From 2. Chapitre µ s ofiue h C hti h otsial o h next the for suitable most the is that MCS the configures hc orsod prxmtl o1%o h frame’s the of 10% to approximately corresponds which , 22 sensor the , MCS c ciae h etMSshm and scheme MCS next the activates sensor

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Figure in illustrated as meta-model, RTOS structural the of instance model Af meta-model. a RTOS structural by the used in present entity ”Service” the and model conforms to model- a called is discipline. technique engineering This model-driven the in model. transformation RTOS structural a into model simulation SoC oceey ecet apn ewe h Cmoet niypeeti th in present entity ”Component” the between mapping a create we Concretely, hspoescudb uoaial ple naysmlto oe ntneo th of instance model simulation any on applied automatically be could process This hstcnqerle ntefc htaymt-oe smnaoydfie us defined mandatory is meta-model any that fact the on relies technique This OveRSoC RTOSOveRSoC model n aheeetfo a from element each and meta-model RTOS OveRSoC F rnfrainengine transformation IGURE oatmtclypouetefia xctbeprograms. executable final the produce automatically to A conforms to n aheeetfo meta-model a from element each and Mdlt oe rnfrainprocess. transformation model to Model – 2.14 iue51:Mdlt-oe rnfrainprocess. transformation Model-to-Model 5.11: Figure µ ocnetamdlisac fteOeSCmt-oe noa into meta-model OveRSoC the of instance model a convert to O-I.Ti oicto sncsaybcuetefia source final the because necessary is modification This cOS-II). eamdlB meta-model M Transformation Engine ta transformation conforms to Object FacilityObject mapping mapping ffi 27 122 inyo ita ytm ntrso efrac and performance of terms in systems virtual of ciency rnfrainengine transformation sln sbt eamdl r endusing defined are meta-models both as long as Figure RTOS structuremodel conforms to ffi meta-model RTOS structure 2.14. in ntecs hr hr sonly is there where case the in cient rdc sa upta output an as produce , B sln sbt eamdl are meta-models both as long as e ht hsrl is rule this that, ter vro meta- OverSoC e n h MetaOb- the ing tfo a from nt h developed the e recd of code urce OveRSoC e to-model meta-

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average release-delay in milleseconds average release-delay in milleseconds 1000 1500 2000 2500 1000 1500 2000 2500 500 500 0 0 . 1 1 deadline task4:2400.0ms faproi ak hc stedifference the is which task, periodic a of VM 2 2 2 . VM(160ms,200ms),task3(300ms,1200ms)&task4(400ms,2400ms) Task set2executedonaLinux-PREEMPT_RTusingonekvmVM VM(160ms,200ms),task1(30ms,150ms)&task2(50ms,200ms) 3 3 Task set1testedonaLinux-PREEMPT_RTusingkvmVM d ees delay Release (d) delay Release (b) 4 4 oosretebehavior the observe to r Number ofruns Number ofruns 5 5 DMR w eaaevirtual separate two n ns ie hnwe Then time. finish n ediems in miss deadline any iue41() Fig- 4.12(a), Figure 6 6 erct verify to metric o’ release job’s y 7 7 ia”release tical” task 3[dmr10.0%] task 4[dmr0.0%] task 2[dmr0.0%] task 1[dmr0.0%] deadline task3:1200.0ms deadline task1:1500.0ms deadline task2:2000.0ms ’s 8 8 verhead. release 9 9 10 10

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Chapitre ehiuscnit nmxmzn h hne aaiywiemnmzn h po- adaptive the the minimizing of while goals capacity main channel the the of One maximizing time. in real consists in techniques adapt environment appropriately the and and to decide QoS, system to the allocation, investigated been guarantee resource also to have as used consumption, such power been parameters, have Va- high-level (BER) system. (RSSI), Rate Other wireless Indicator Error adaptability. Strength the Bit Signal (SNR), of Received Ratio part the Signal-to-Noise as recongure such to systems parameters Such low-level decide rious properties. and channel analyze, to learn, according waveforms sense, adapt to systems reless ecient and fast apply to how or Also, made ? state be channel can wireless that new ? decision reconguration the optimal detect parame- the to what Each is analyzed example not. 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PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX

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( − Euvln hne Phase Channel Equivalent (b) 2 k φ 2( z )) B( + s U

2xSPO ∗ ) φ s P }| k i − (4.19) ) P i →

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PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX hc ilb sdb BT oevaluate to Tx BB by used be will which than DL smaller and duration (UL a duration within frame occur time total must coherence frame) the the Therefore than channel. shorter duration the time a on only of estimate the channel complex propagation UL the estimation Channel : transmission UL RASK A. and OFDM of detailed. combination be the will modulation implement to aims 5 the of average the calculating in and n frame pilot per symbols 2. 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Tx Received Power [dBm] Received Power [dBm] F −62 −60 −58 −56 −54 −52 −50 −62 −61 −60 −59 −58 −57 −56 −55 −54 −53 IGURE 0 0

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ff 79 rn itne ewe h eev antennas. receive the between distances erent , 1]T uos .H M. Dubois, T. [14] 1]G .Sih Adrc eiaino igeatnarcpoiyrelation reciprocity single-antenna a of derivation direct “A Smith, S. G. [13] (UWB) ultra-wideband “Time-reversed Qiu, C. R. and Guo, N. Zhou, C. [10] 1]T uos .H M. Dubois, http://warpproject.org T. Available: [Online]. [12] project.” “Warp [11] 8 .Drd,P ox n .Fn,“outaosi iervra with reversal time acoustic “Robust Fink, M. for and Roux, transmission P. Derode, MIMO A. layered [8] “Dual Hanzo, L. and Masouros C. [7] H M. and Phan-Huy T. D. [6] 9 .E-alb,P yis,A ala,adG aaioau “Experimental Papanicolaou, G. and Paulraj, A. Kyritsi, P. El-Sallabi, H. [9] Received Power [dBm] Received Power [dBm] −64 −62 −60 −58 −56 −54 −52 −64 −62 −60 −58 −56 −54 −52 nentoa ypsu nProa,Ido,adMbl ai Com- Radio Mobile and (PIMRC) Indoor, in munications Personal, systems,” on Symposium MISO-OFDM International large to 2004. applied June 1568–1577, pp. 6, no. 52, vol. o h iedomain,” time the for spatial measured on based (MIMO) output multiple channels,” input multiple scattering,” multiple high-order nology efficiency,” bandwidth increased on Conference International IEEE in communications,” wireless reversal 2013. time Nov 4511–4523, pp. 9, no. 62, implementation vol. modulation,” “Practical Haas, H. spatial and Beach, of A. M. Grant, M. P. Wang, FMytm ur nevldsg,dmninn n synchronisation in and aspects,” dimensioning design, interval Guard OFDMsystem: 2009. 2884–2898, pp. in focusing time and Measurement space for communications,” precoding wireless reversal time on investigation 1995. 4206, p. 0 0

b FMsmo oue oadRx toward focused symbol OFDM (b) d FMsmo oue oadRx toward focused symbol OFDM (d) o.P,n.9,p.11 2015. 1–1, pp. 99, no. PP, vol. , 50 50 eiua ehooy EETascin on Transactions IEEE Technology, Vehicular ieesol eerhFrm WWRF-29) Forum, Research WirelessWorld o.5,n.6 p 5714,Jn 2010. June 1537–1543, pp. 6, no. 59, vol. , ∆ ∆ f f 2 4 lr,adM Crussi M. and elard, OFDM SymbolIndex OFDM SymbolIndex ´ 100 100 lr,M Crussi M. elard, ´ EETascin nAtna n Propagation and Antennas on Transactions IEEE et21,p.896–901. pp. 2013, sept , EETascin nVhclrTechnology Vehicular on Transactions IEEE EETascin nIsrmnainand Instrumentation on Transactions IEEE 150 150 lr,“eev nen hf eigfor keying shift antenna “Receive elard, ´ hsclrve letters review Physical EETascin nVhclrTech- Vehicular on Transactions IEEE ue21,p.4852–4856. pp. 2012, June , r,adI az Tm reversal “Time Maaz, I. and ere, ` 200 200 r,“iervra naMISO a in reversal “Time ere, ` omnctos(C) 2012 (ICC), Communications 2 4 Rx4 Rx3 Rx2 Rx1 Rx4 Rx3 Rx2 Rx1 03IE 4hAnnual 24th IEEE 2013 250 250

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PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS PPENDIX A ,

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PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX

Lla ose,GyGgit n an ulsn yaial ofiual euiyfor security configurable Dynamically Burleson. Wayne and Gogniat, Guy Bossuet, Lilian Using Machines Virtual Interactive And Best. Batch Joel Mixing [BGB06] : VSched Dinda. P.A. and Lin Bin [Bes13] [BD05] [BCLK [BBFH [BBC [ARW Je [Arn95] O rod .Rctr .Ftwi,adO lm.Pwrcnupinmdln fdif- of modeling consumption Power Blume. O. and Fettweis, G. Richter, F. Arnold, O. [ARFB10] [APA B ma . .B od n .Mhma.Ie 0.1bsdvria advrin handover vertical based 802.21 Ieee Muhammad. I. and Mohd, B. D. Handbook. A., 2015. 4 Ammar May. introduction, B. builder Dsp Inc. Altera [AMM12] Guide Altera. User 2014. July guide, user [Alt15b] estimator power early Powerplay Incorporation. [Alt15a] Altera 2015. paper. white 5g Alliance. NGMN [Alt14b] Aichouch. [All15b] Mehdi El Mohamed [Aic14a] hetero- in decisions handover vertical Enabling Gaiti. D. [AHK and Boulahia, L.M. Ahmed, A. [ABG14] Nse .Aoab n aiS lael erlntokbsdhnoe management handover based network neural A Alwakeel. S. Sami and Alotaibi M. Nasser [AA16] + + + + BönB rnebr,ArnD lc,Jh .Clnrn,Uaaewr ei Henna- Devi, UmaMaheswari Calandrino, M. John Block, D. Aaron Brandenburg, B. Björn 07] JsnArn elyPc,Ei nesn ai nrw,E op o as Fabrice Sass, Ron Komp, Ed Andrews, David Anderson, Erik Peck, Wesley Agron, Jason 06a] + + AdesAn,Mru ap,AdesKle,En ubr,Brhr ltnr Marco Plattner, Bernhard Lubbers, Enno Keller, Andreas Happe, Markus Agne, Andreas 14] N use,M ihrsn ..Wlig,K idl,adA un.Apyn e schedu- new Applying Burns. A. and Tindell, K. Wellings, A.J. Richardson, M. Audsley, N. 10] H rul .Brte .FüyHrr,J uune,D inle,adH oso.Tcet Tic Boisson. H. and Vignolles, D. Cueugniet, J. Flüry-Hérard, B. Burette, D. Breuil, H. 08] SeaoBzi .Ci-i,TiryE li,H icn or hnagYn,adAlessio and Yang, Chenyang Poor, Vincent H. Klein, E. Thierry Chih-Lin, I. Buzzi, Stefano 16] ieSsesSmoim 06 TS0.2t EEInternational IEEE 27th RTSS’06. 2006. Symposium, Systems Time RMFG bitstreams. FPGA SRAM 2013. Guelph, of Engineering,University of School thesis, PhD 2005. Scheduling. Real-time Periodic Communications in Areas Selected on Journal energy-e IEEE of survey A Zappone. l’Information. de Technologies des du Général et Conseil l’Environnement le de Général et Conseil Durable du Développement Rapport 2008. Déc. durable, 2007. développement report, status A : rt Litmus Anderson. H. James and Leontyev, diy igter osai roiypeepiescheduling. pre-emptive priority static to theory ling 1995. eetbs tto ye nhtrgnosclua ewrs In networks. cellular 2010 heterogeneous Summit, in types station base ferent In chip. on systems cpu/fpga hybrid for services Run-time Stevens. Jim and Baijot, 4–4,Mrh2012. March 140–144, i n ia ewrs In networks. wimax and wifi UG-01070. techniques allocation resources RTOS’s 2014. an May of Rennes, de configuration and system chine classification. a and Tutorials state-of-the-art & A Surveys : networks wireless geneous ltnr n hita lsl eoo noeaigsse prahfrreconfigurable for approach system operating An : computing. Reconos Plessl. Christian and Platzner, ec nMcieLann n plctos CL 2015 ICMLA Applications, and Learning Machine on In rence networks. heterogeneous for strategy ff e .Anl.Tesls otaeenvironment. software 2 splash The Arnold. M. rey yln eieOverview Device V Cyclone elTm prtn ytmHrwr xeso oefrSse-nCi Designs System-on-Chip for Core Extension Hardware System Operating Real-Time ir,IEEE Micro, ae –,Jn 2010. June 1–8, pages , 62 7681 2014. :776–811, 16(2) , 41 6–1 2014. :60–71, 34(1) , nentoa ora fEbde Systems Embedded of Journal International 02IE ypsu nCmuesIfrais(ISCI) Informatics Computers on Symposium IEEE 2012 ffi leaCroain 2015. Corporation, Altera . in ehiusfr5 ewrsadcalne ahead. challenges and networks 5G for techniques cient vlaino utpeciiaiyra-ievrulma- virtual real-time criticality multiple a of Evaluation 99 rceig 05IE 4hItrainlConfe- International 14th IEEE 2015 - Proceedings 2016. , otaeEgneigJournal Engineering Software 2016. , .Supercomput. J. Bibliography uueNtokadMobile and Network Future ae –2 EE 2006. IEEE, 3–12. pages , 2006. , EECommunications IEEE 2720 May :277–290, 9 , hss INSA Theses, . 2010. , pages , Real- .

PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX M euc,D eVle,W oeh n .Mres oeln h oe consumption power the Modelling Martens. L. and Joseph, W. Vulder, De D. Deruyck, M. [DDVJM12] commu- digital for reversal time of use the On Hélard. [DDG M. and Crussière, In M. devices. Dubois, T. connected billion 50 with Life : 2020 Davis. high-level G. [DCH10] for macromodel network Neural Gao. Xun and [Dav18] Yan, Yuanyuan channels. fading Cao, wireless Y. on Q. modulation W. Space Yu. Hong Shi and Chau A. Yawgeng [CYG05] [CY01] Wr rjc."tp://warpproject.org". "http [CWH project. Warp [CPG [Con] [CLC [CHY [BHH YnCe n oiFre.QSrqieet fntokapiain nteInternet. the on applications network of requirements QoS Farley. Toni and Chen Yan coded adaptive Implementing J.C. Pr?votet [CF04] and Y. Eustache L., Conde-Canencia Y. Oliva [CCLJ12] adaptive Modeling Oliva. Yaset and Prévotet, 2011. J-C suite, Eustache, development system Yvan Cadence Conde-Canencia, Laura Cadence. fpga for approach modelling [CCEPO12] power behavioural new A time- Amira. in A. [Cad11] Super-resolution and Chandrasekaran S. Zhao. Hongkai and Papanicolaou, George Blomgren, [CA07]Peter execution seamless Enabling Sudarshan. TSB and [BPZ02] Purnaprajna, Madhura Belwal, Meena [BPS15] + + + + + + KteieCmtn hya i ae oly tpe nl n ct ac.Configu- Hauck. Scott and Knol, Stephen Cooley, James Li, Zhiyuan Compton, Katherine 02] Smri hkaot,Toa Pfeu Thomas Chakraborty, Samarjit 11] Y hn .Hn .H ag .M,Y a,C in,H .Li .Cla D. Lai, Q. H. Jiang, C. Han, Y. Ma, H. Yang, H. Y. Han, F. Chen, Y. 14a] Jre ekr ihe ube,GradHtih anrCntpl oci Eisenmann, Joachim Constapel, Rainer Hettich, Gerhard Huebner, Michael Becker, Jürgen 07b] C est .Dbile .Gann,A ese .Ae,H otap .Wja .Sabella, D. Wajda, W. Holtkamp, H. Auer, G. Fehske, A. Giannini, V. Debaillie, B. Desset, C. 12] Y hn .Wn,Y a,H .Li .Sfr n .J .Lu h iervra o future for reversal time Why Liu. R. J. K. and Safar, Z. Lai, Q. H. Han, Y. Wang, B. Chen, Y. 16] WNW,21 IEEE 2012 In (WCNCW), networks. femtocell in Systems Communication In and Processing waveforms. non-impulsive with nications In Brain circuits. cmos of estimation power .Bue lxbepwrmdln flebs ttos In and Ambrosy, stations. A. base Imran, lte IEEE M.A. 2012 of Olsson, (WCNC), modeling Conference M. Networking power Godor, Flexible I. Klessig, Blume. H. O. Gonzalez, M.J. Richter, F. (ICCE) Electronics Consumer on rence Conference Technology Vehicular gwrls?[perspectives]. wireless? 5g 2011. applications. real-time embedded for schedulers VM Designing Drössler. eyLreSaeItg.Syst. Integr. Scale computing. Large reconfigurable Very run-time for defragmentation and relocation ration .J .Lu iervra ieesprdg o re nento hns:A overview. An : things of internet green for Journal paradigm Things wireless of Time-reversal Internet IEEE Liu. R. J. K. n ügnLk.Dnmcadprilfg exploitation. fpga partial and Dynamic Luka. Jürgen and nomto nweg ytm Management Systems Knowledge Information approach. modelling A (EUSIPCO-2012) Conference : Processing terminals Signal mobile European reconfigurable partially time real in modulation European 20th the In 2012. of Proceedings terminals. 2012 mobile (EUSIPCO), reconfigurable Conference partially sing time real in modulation coded on Conference In cores. custom based acoustics. reversal In on directions. Conference International & 25th Challenges 2015 (FPL), : Applications systems cpu/fpga hybrid on 2007. :438–452, 95(2) oue2 ae 0911,Ot2005. Oct 1009–1014, pages 2, volume , ae 5–5,Ag2007. Aug 350–357, pages , h ora fteAosia oit fAmerica of Society Acoustical the of Journal The ae 03,Arl2012. April 30–35, pages , dpieHrwr n ytm,20.AS20.Scn NASA/ESA Second 2007. AHS 2007. Systems, and Hardware Adaptive ieesCmuiain n ewrigCneec Workshops Conference Networking and Communications Wireless 0:0–2,Jn 2002. June :209–220, 10 , EESga rcsigMagazine Processing Signal IEEE ():19,Fb2014. Feb :81–98, 1(1) , 2001. , 100 ae –,Jn2018. Jan 1–1, pages , ff 05ItrainlCneec nNua ewrsand Networks Neural on Conference International 2005 ae –,Dc2010. Dec 1–6, pages , r atnGir ljnr arr n Sebastian and Masrur, Alejandro Geier, Martin er, ae 8826,Arl2012. April 2858–2862, pages , 2004. , 004hItrainlCneec nSignal on Conference International 4th 2010 2012. , ae –.IE,2015. IEEE, 1–8. pages , 08IE nentoa Confe- International IEEE 2018 32 1–6 ac 2016. March :17–26, 33(2) , il rgambeLgcand Logic Programmable Field ieesCmuiain and Communications Wireless 1():3–4,2002. :230–248, 111(1) , ae 0915.IEEE, 1049–1053. pages , rceig fteIEEE the of Proceedings ff y .Sfr and Safar, Z. ey, Bibliographie inlProces- Signal EETrans. IEEE IEEE , ExpressLogic. [GBB [Exp07] DaaGhigr ihe ünr ten geiZueoo n ügnBce.Opera- [GPH Becker. Jürgen and Zeutebouo, Nguepi Etienne Hübner, Michael Göhringer, Diana [GHZB11] Cap- Becker. Jürgen and Zeutebouo, Nguepi Etienne Hübner, Michael Göhringer, Diana [GHZB10] [GBL mode- ip on based estimation power soc level high A Houzet. D. and Julien, N. Elleouet, D. da- [EJH06] pipelined reconfigurable - Rapid Franklin. Paul d2.3. and deliverable Cronquist, C. earth Darren infso-ict-247733 Ebeling, project Carl Earth modeling behavioral [ECF96] at consumption power of Estimation Stuikys. V [ear] and Damasevicius R. recon- [DS07] Partial Leray. Pierre and Moy, Christophe Palicot, Jacques Delahaye, dyna- Philippe for Jean fpgas of reconfiguration Partial [DPML07b] Leray. P. and Moy, C. Palicot, J. Delahaye, P. J. [DPML07a] [DMN M .DvyadD .C aKy o est aiycekcdsoe fq.In gf(q). over codes check parity density Low MacKay. C. J. D. and Davey C. M. [DM98] [DLC TiryDbi,Mrln éad atiuCusèe n éieGrod Performance Germond. Cécile and Website. Crussière, 2015. Matthieu project, Hélard, ptolemy The Maryline Dubois, Department. Thierry EECS Berkeley UC [DHCG13] [Dep15] Bibliographie + + + + + MraEGnae,Atl igc dmLcoznk,Dca uo,Ei au,adIrv and Matus, Emil Tudor, Dacian Lackorzynski, Adam Bilgic, Attila Gonzalez, E Maria 09] RbnGraut ioasBrzui,Load oe atr icn eg enBaptiste Jean Berg, Vincent Baltar, Gomes Leonardo Bartzoudis, Nikolaos Gerzaguet, Robin 17] Ju-ugDn,CagJn i,Pn-a hn,CihHoTag e-hn Hsu, Wei-Chung Tsang, Chieh-Hao Chang, Ping-Hao Lin, Chang-Jung Ding, Jiun-Hung 12] Sea aetnGerht,Mri akvc unHmr,Anu adcpel,Stelios Vandecappelle, Arnout Hamers, Juan Palkovic, Martin Gheorghita, Valentin Stefan 09] J eom,J atn .Nfh,C o,F lriy .Lry n .Plct fpga A Palicot. J. and Leray, P. Clermidy, F. Moy, C. Nafkha, A. Martin, J. Delorme, J. 08] Verlag. iinRt.Te5 addt aeomrc oprsno opeiyadperfor- and complexity of comparison a : race waveform candidate and 5G Färber, mance. The Michael Payaró, Miquel Roth. Mestre, Xavier Kilian Font-Bach, Oriol Kténas, Dimitri Doré, 2006. April pp.–, 4 pages 01: 13:6 aur 2011. January :16, systems. :1–3 multiprocessor :3 reconfigurable 2011 runtime for system ting on Symposium International IEEE 2010 (IPDPSW), on Forum management Phd resource and and mapping In task architectures. scheduling, multiprocessor runtime reconfigurable for system Operating : os In on Conference phones. International IEEE smart 2009. future ICME for 2009. solution innovative an Ict-emuco. Badr. In ling. Compilers and Paradigms New Applications, In tapath. In systemc. using level In platform. radio Summit Communications software Wireless a and of Mobile reconfiguration IST 16th dynamical for FPGAs of figuration In platform. radio Summit software Communications a of TAISA reconfiguration mical and Systems and Circuits on In Workshop Northeast architecture. IEEE noc Conference on International based 6th radio Joint cognitive 2008 for approach design reconfiguration partial adpte ta.Sse-cnrobsddsg fdnmcebde systems. embedded (TODAES) Systems dynamic Electronic of of Automation design Design System-scenario-based on Transactions Frederik Catthoor, al. Francky et Corporaal, Vandeputte, Henk Eeckhout, Lieven Basten, Twan Mamagkakis, 2007. May Corporation, nomto hoyWrso Ct No.98EX131) (Cat. Workshop Theory Information n e-hn hn.Amio ytmvrulzto o r.In arm. for virtualization System (OLS) : Symposium Linux Armvisor Ottawa Chung. Yeh-Ching and ftm eeslpeoigtcnqefrms-fmsystems. Networking miso-ofdm and for Communications technique precoding reversal time of aalladDsrbtdPoesn ypsu,20.IDS20.2t International 20th 2006. IPDPS 2006. Symposium, Processing Distributed and Parallel uai ora nWrls omnctosadNetworking and Communications Wireless on Journal Eurasip ae 5–5,Jn 2008. June 355–358, pages , rceig fte6hItrainlWrso nFedPormal oi,Smart Logic, Field-Programmable on Workshop International 6th the of Proceedings esrn elTm efrac fA RTOS An Of Performance Real-Time Measuring UAI ora nEbde ytm,2007 Systems, Embedded on Journal EURASIP ae –,Jl 2007. July 1–5, pages , ae 317 2012. 93–107, pages , 031 20 o 2013. Nov :260, 2013(1) , 101 ae 2–3,Lno,U,19.Springer- 1996. UK, London, 126–135, pages , aall&DsrbtdPoesn,Workshops Processing, Distributed & Parallel ae 07,Jn1998. Jun 70–71, pages , ae 8112.IE,2009. IEEE, 1821–1824. pages , 2007. , 071t S oieadWireless and Mobile IST 16th 2007 2007. , UAI ora nWireless on Journal EURASIP ae –.IE,2010. IEEE, 1–8. pages , 41 3 2009. :3, 14(1) , n.J eofi.Comput. Reconfig. J. Int. 2017. , idw Publishing Hindawi . utmdaadExpo, and Multimedia rceig fthe of Proceedings ACM 2007 1998 , ,

PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX Emne Huck. Emmanuel [Huc11] [HSH [HRR Gro esradBnLsi.Teol irvsr:cnegnepito irkresand microkernels of point convergence : microvisor okl4 The Leslie. [HLF Ben and Heiser Gernot [HL10] E Nebel. Wolfgang and Reinkemeier, Philipp Kleen, Henning Hartmann, A. rea- Philipp for services system operating Real-time Huss. [HKRN08] S.A. and Klaus, Stephan Hastono, Prih [HKH04] Cu-sa un n a-n sug adaersuc itaiainfrdynami- for virtualization resource Hardware Hsiung. Pao-Ann and Huang Chun-Hsian [HH09] and In dynamic Fast bother? Becker. why Jürgen and : Noguera, systems Juanjo embedded Göhringer, Virtualizing Diana Hübner, Michael Heiser. Gernot [HGNB10] [Hei] DeHon. Andre and Hauck Scott [HDL defi- software for techniques reconfiguration partial [HD10] dynamic of evaluation Performance Tar- and Generation Automatic Jerraya. Amine Ahmed [Has16] and Yoo, Sungjoo level Gauthier, Lovic system for modeling RTOS Gajski. D. Daniel [GYJ01] and Yu, Haobo Gerstlauer, Andreas [GYG08] [GRE + + + + + Ce-e s,JaL io hnCinFn,Ci-he eg h-uHag Wen-Tsan Huang, Shi-Yu Weng, Chia-Chien Fang, Shan-Chien Liao, Jia-Lu Hsu, Chen-Wei 11] MthwRGtas Je Guthaus, R Matthew 01] J .Hag .B u,S .Ho .J ak .M y,S .Pr,adC .Km e nam: arm on Xen Kim. R. C. and Park, Y. S. Ryu, M. J. Park, J. C. Heo, K. S. Suh, B. S. Hwang, Y. J. 08a] FbaoHse,VtrMRs,Io es vIiag,ProAer,CsrAMMarcon, M A César Alegre, Porto Ipiranga, Av Reis, M Igor Rosa, M Vitor Hessel, Fabiano 04] E ug .J ai,J .Lvn,E .Sot .Y .Cen,adG .Constantinides. A. G. and Cheung, K. Y. P. Stott, A. E. Levine, M. J. Davis, J. J. Hung, E. 16] ytmvrulzto sn e yevsrframbsdscr oiepoe.In Conference phones. Networking mobile and secure Communications arm-based Consumer IEEE for 5th hypervisor xen using virtualization System pc xlrto nhtrgnosMSCarchitectures 2011. November MPSoC toise, heterogeneous in exploration space Systems 2004. Embedded Sul. for do Grande Modeling Rio RTOS do Abstract Federal Universidade Gonçalves. Informática B de Faculdade Av and Susin, A Altamiro se,adJnCihYh oedpt:Itgaigi-ae oe oeigwt esl with modeling In power designs. ip-based ACM/EDAC/IEEE soc Integrating 48th multi-core : for Powerdepot analysis power Yeh. Jen-Chieh and Hsieh, 2010. ACM, 19–24. pages In hypervisors. (FDL’04) Languages systems. Design & embedded Specification of on Forum models simulation SystemC listic oeln n iuaino meddsfwr ut-akn sn ytm n OSSS. and 2008. SystemC using multi-tasking software In embedded of simulation and modelling al atal eofiual systems. reconfigurable partially cally International IEEE In 2010 (IPDPSW), Forum fpgas. Phd xilinx and on on Workshops Symposium overhead Processing, hardware Distributed low & with lel path data reconfiguration partial computation based Systems and In Circuits, Electronics, FPGA. on implementation radio ned Systems and Circuits Integrated Software. of Systems Design Embedded Computer-Aided on and Transactions Systems Operating Application-Specific of geting Date In design. benchmark embedded 2001. representative IEEE, commercially 3–14. pages free, A In : Mibench suite. Brown. B Richard einAtmto Conference Automation Design fpga in (FCCM) estimation Machines power Computing per-module online to In approach designs. identification system A : Kapow rceig 08Frmo pcfiain eicto n einLnugs FDL’08 Languages, Design and Verification Specification, on Forum 2008 - Proceedings 2008. . okodCaatrzto,20.WC4 01IE nentoa okhpon Workshop International IEEE 2001 WWC-4. 2001. Characterization, Workload ein uoain n eti uoe:TeMs nunilPpr f1 Years 10 of Papers Influential Most The : Europe in Test and Automation, Design, 06IE 4hAna nentoa ypsu nFedPormal Custom Field-Programmable on Symposium International Annual 24th IEEE 2016 ae –.IE,2010. IEEE, 1–8. pages , rceig ftefis C sapcfi okhpo okhpo systems on Workshop on workshop asia-pacific ACM first the of Proceedings ognKumn,2010. Kaufmann, Morgan . ihlvlsmlto fdsrbtdra-ieoeaigssesfrdesign for systems operating real-time distributed of simulation High-level ae 75,Jn 2011. June 47–52, pages , ff e igneg a rs,Td utn rvrMde and Mudge, Trevor Austin, M Todd Ernst, Dan Ringenberg, S rey ae 66,My2016. May 56–63, pages , ae 0–0.ACM. 901–905. pages , 2016. , eofiual optn h hoyadpatc fFPGA- of practice and theory the : computing Reconfigurable 102 meddSsesLtes IEEE Letters, Systems Embedded rceig fteIE nentoa ofrneon Conference International IEEE the of Proceedings einAtmto ofrne(A) 2011 (DAC), Conference Automation Design 2004. , hss nvriéd eg Pon- Cergy de Université Theses, . rceig fteInternational the of Proceedings ae 5–6,Jn2008. Jan 257–261, pages , rceig fte48th the of Proceedings ():92,2009. :19–23, 1(1) , 2001. , Bibliographie ffi Paral- 2008 cient IEEE , , , Jce Liedtke. Jochen [Lie95] recon- partially based cordic using implementation transmitter [LAL ofdm An Kumar. A. A. K. reconfigurable for pr using modems [Kum14] qam of implementation Fpga Kumar. Arun A. K. for re-configuration partial using modems psk [Kum13a] 2015. of implementation software, Fpga Kumar. design Arun A. (esl) K. system-level electronic Systemvue Keysight-Technologies. [Kum12] Kontron. [KT15] [Kon12] Kokar. Yvan FPGAs. on reconfiguration Partial Koch. Dirk [Kok18] [Koc13] Xilinx in reconfiguration partial and dynamic Enabling Gohringer. [KJU Diana and Kalb Tobias [KG16] In MPSoCs. Beckho of Christian How Koch, and Why, Dirk What, The Wolf. Wayne and Jerraya Amine Ahmed [KBT08] [JW05] [JPC wire- hybrid in algorithm scanning network adaptive An Hong. data-[JHE for Seokjoon model and estimation Joe power Inwhee dynamic complete A Carreras. Carlos and Jevtic Ruzica [JH09b] [JC12] [HYW Bibliographie + + + + Ahse ua an haDn hm i u,Shi am,adDulsLMaskell. L Douglas and Fahmy, A Suhaib Cui, Jin Pham, Dang Khoa Jain, Kumar Abhishek 14] KzstfJzi,Siy od,Mst dhr,Hryk oiaa n iok Ta- Hiroaki and Tomiyama, Hiroyuki Edahiro, Masato Honda, Shinya Jozwik, Krzysztof 13] M hn .Jn,P .Uo,C hno .Km .Yo,A aem n .Hn En- Han. K. and Nadeem, A. Yoon, Y. Kim, J. Zhenbo, C. Uzoh, C. P. Jung, C. Khan, M. 15] + WzosiAawlLe .Aawl .Le .Sih .Lm .Ahns n .Ghosh. S. and Athanas, P. Lam, E. Smith, A. Lee, T. Agarwal, L. Lee, Agarwal Wazlowski 93] F a,Y .Yn,B ag .W,adK .R i.Tm-eesldvso utpeaccess multiple division Time-reversal Liu. R. J. K. and Wu, Y. Wang, B. Yang, H. Y. Han, F. 12] rs-icmie n rhtcue 1993. architecture, and compiler Prism-ii Systems Communication i figurable Energy Renewable and 2013. Communications June Microelectronics, 1–6, pages on Conference International 2013 In radios. wireless 2012. Dec In applications. cr and sdr Website. 2018. INSA Rennes, Télécommunications et Electronique Maryline OFDM et temporel tournement (IWCMC) wireless heterogeneous in In making decision networks. on based management handover vertical abling 2016 In SDSoC. on Conference In International 2008. 2008. fpgas. IEEE, FPL for 124. 2008. systems Applications, reconfigurable and dynamically Logic and grammable statically build to nique Systems-on-Chips processor NE:–9,2013. :1–295, LNEE platform. arm-fpga hybrid Systems a Processing on Signal tasks of hardware Journal of management and execution Virtualized aa ano noeaigsse o otaehrwr uttsigo dynamically 2013. on multitasking software-hardware fpgas. for reconfigurable system partially operating An : Rainbow kada. 2009 ICUT Applications, and Technologies In networks. less designs. dsp fpga in paths 2012. channels. multi-path over 2016. , ae 5–5,Ag2015. Aug 952–957, pages , oedt h osblte 8 et PAwhitepaper FPGA meets x86 : possibilities the to end No ff 06ItrainlCneec nRcngrbeCmuigadFGs ReConFig FPGAs, and Computing Reconfigurable on Conference International 2016 oue In module. t 05ItrainlWrls omnctosadMbl optn Conference Computing Mobile and Communications Wireless International 2015 td el iee ur aéileduetasiso asfi obnn re- combinant fil sans transmission d’une matérielle œuvre en mise la de Etude nmcokre construction micro-kernel On rceig fte4hItrainlCneec nUiutu Information Ubiquitous on Conference International 4th the of Proceedings 03Ana nentoa ofrneo mrigRsac ra and Areas Research Emerging on Conference International Annual 2013 ae 6–7,Dc2014. Dec 266–270, pages , 043dItrainlCneec nEofinl optn and Computing Eco-friendly on Conference International 3rd 2014 2005. . nerto,teVS Journal VLSI the Integration, 02Ana EEIdaCneec (INDICON) Conference India IEEE Annual 2012 EETascin nCommunications on Transactions IEEE ff h hss 08 hs edcoa iié a Hélard, par dirigée doctorat de Thèse 2018. thesis, PhD . n ügnTih eou-ule- oe oladtech- and tool novel Recobus-builder-a Teich. Jürgen and , nentoa ora fRcngrbeComputing Reconfigurable of Journal International 712 6–6 2014. :61–76, 77(1-2) , 103 2009. , oue2.AM 1995. ACM, 29. volume , etr oe nEetia Engineering Electrical in Notes Lecture 52 12–15 2012. 185, – :172 45(2) , oto,2012. Kontron, . 07 15–95 July :1953–1965, 60(7) , ae 205–209, pages , ae 119– pages , il Pro- Field 03:5, 2013 , Multi- 153 , ,

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Mercury and Virk, Kashif Madsen, Jan innovation. wireless [NIC15] for catalyst a : radio Software Increased Palicot. J. for and Transmission Moy C. MIMO [MVG] Dual-Layered Hanzo. Lajos and Masouros Christos [MP15] In reconfiguration. partial fpga Runtime McDonald. [MH16] J Eric charac- exact 2015. www.mathworks.com, : MathWorks. algorithm scheduling monotonic rate The [McD08] Ding. Y. and Sha, L. systems Lehoczky, real-time [Mat15] J. for model RTOS generic A Calvez. P. J. and [LSD03] Pasquier, O. Moigne, Le R. [LPC04] Lorandel. Jordane [Lor15] reconfigura- partial Run-time Jantsch. Axel and Lu, Zhonghai Kuehn, Wolfgang Liu, Ming [LKLJ09] + + Ln ..Pa,Mn u awoLe nu e,adOe oosy Overhead-aware Sokolsky. Oleg and Lee, Insup Lee, Jaewoo Xu, Meng Phan, T.X. Linh 13] NesPnea,DneisKdnks lsarRwton,BonD utr n Koen and Sutter, De Bjorn Rawsthorne, Alasdair Kudinskas, Danielius Penneman, Niels 13] + SK ehngr,R e ttla,S ir .Sn,adJ eesr yrdsse level system Hybrid Dekeyser. J. and Senn, E. Niar, S. Atitallah, Ben R. Rethinagiri, S.K. 11] a ypsu on Internatio- Symposium 9th In nal 2014 (ReCoSoC), reconfiguration. Systems-on-Chip partial Communication-Centric dynamic and using Reconfigurable accelerators multithread multikernel of gement In on Conference International mpsoc. 29th fpga-based IEEE for estimation consumption power oue2 ae 5–6,Dc2007. Dec 2007) 159–163, (ICCIMA pages Applications 2, Multimedia volume and Intelligence Computational on Conference tional In systems. Proceedings real-time of analysis compositional r nmsiemm ytm ujc opaenoise. phase to subject munications systems mimo massive in mrc eBscee omlvrulzto eurmnsfrteamarchitecture. arm the for requirements virtualization Architecture Formal Systems Bosschere. De fmts-e.In test-bed. ofdm In communications. wireless In Applications and Logic node. Programmable sensor Field wireless on advanced an of configuration 2015. www.ni.com/labview/, report. Technical System-on-Chip*. cessor E Bandwidth 2003. behavior. case average and terization In 2004. systemC. with simulation on Conference International 2009. FPL 2009. 2009. In Applications, exploration. and space design Logic architectural and investigation speed tion in Magazine tions 2008. IEEE, 1–7. pages 2015. INSA Rennes, Télécommunications et Electronique FPGA Maryline cible Hélard, sur implantés fil sans mériques 2013. , 42 7173 e 2015. Feb :711–723, 14(2) , ffi 39 2–0 e.2015. Sep. :24–30, 53(9) , ciency. ae –.IE,2014. IEEE, 1–7. pages , uoenWrso nTsbdbsdwrls research wireless based Testbed on Workshop European td el osmainéegtqed ytmsd omnctosnu- communications de systèmes de énergétique consommation la de Etude 93 1414 2013. :144–154, 59(3) , EETascin nVhclrTechnology Vehicular on Transactions IEEE EEItrainlCneec nCommunications on Conference International IEEE rceig Dsg,Atmto n eti uoe DATE Europe, in Test and Automation -Design, Proceedings 104 ae 3–4,Ot2011. Oct 239–246, pages , h hss 05 hs edcoa iié par dirigée doctorat de Thèse 2015. thesis, PhD . ae 9–9.IE,2011. IEEE, 396–398. pages , elTm ehooyadApiain - Applications and Technology Real-Time EETascin nWrls Com- Wireless on Transactions IEEE 012s nentoa Conference International 21st 2011 eopc ofrne 08IEEE 2008 Conference, Aerospace optrDsg IC) 2011 (ICCD), Design Computer 2016. , ae 9–0.IEEE, 498–502. pages , 2014. , il Programmable Field EECommunica- IEEE Bibliographie 2012. , ora of Journal Interna- , , , Xln noprto.Xoe siao srgie a 02 srGieU40(v13.4). UG440 Guide User 2012. 14.3). Xilinx. Jan (v guide, UG640 user Guide estimator User Xpower 2012. Incorporation. 16 Xilinx Oct. dsp, for generator System [Xil14c] Inc. Xilinx [Xil12c] Xia. Tian [Xil12a] [Xia16] platform. radio cognitive on reconfiguration partial Dynamic [XBG Wu. Yan Feng and Wang Lie In computer. set instruction dynamic [WW09] A Wirthlin. J. M. [Wir95] WiWn,MorgBlc n oahnPri vpa:acsiga pabsdhardware fpga-based an accessing : pvfpga Parri. Jonathan and Bolic, Miodrag Wang, Wei [WBP13] [VSS mpsocs. of exploration space design A Scenario-based : [VSR Pimentel. Reconfiguration Andy Partial and and Stralen Van Dynamic Peter FPGA Fahmy. A. Suhaib and Vipin Kizheppatt E [VSP10] : Zycap Fahmy. A Suhaib and Vipin Kizheppatt [VF18] [VF14] SehnM rmegr he gso PA ersetv ntefis hryyasof years thirty first the on retrospective A : FPGAs of ages Three Trimberger. M. Stephen [Tri15] Systemc. [thr] Website. 2015. studio, System Synopsys. [Sysc] [Syn15] [SYM Secsystem. Specc Men- 2015. systemverilog, and systemc across tlm [SRH for approach scalable A Bhutada. Shashi [spe] [Sha15] S iaata,R drh .Bagv n .J ad.Prilrcngrbeimplemen- reconfigurable Partial Naidu. J. K. and Bhargav, S. Adarsh, R. Sivanantham, S. [SABN14] Bibliographie + + + + + D itV,O adr .Snmn,J edlegr .Ber n .Bce.On-demand Becker. J. and Baehr, S. Heidelberger, J. Sandmann, T. Sander, O. Vu, Viet D. 15] C enl,K ueh .Rte,G asmnrynn n ekBmK.Dnmcpartial Dynamic Ko. Seok-Bum and Lakshminarayanan, G. Rather, R. Suresh, K. Vennila, C. 13] M tebh,R oae,R ahlnr .Huet n .Tih s oe n perfor- and power Esl Teich. J. and Haubelt, C. Hasholzner, R. Rosales, R. Streubuhr, M. 11] Yn u ei rn,EiaehGnae,SaiTaoli lu ot n tiaBilgic. Attila and Mott, Klaus Traboulsi, Shadi Gonzalez, Elizabeth Bruns, Felix Xu, Yang 10] Nkl eamvk,Adlai ons adMse,P hmes ac iRenzo, Di Marco Chambers, P. Mesleh, Raed Younis, Abdelhamid Serafimovski, Nikola 13] NAd ens uy2016. July Rennes, de INSA 2009 ICIS Systems, In Society. Computer IEEE 1995. ednso h nentoa ofrneo optr lcrcl n ytm cec,adEn- and Science, Systems and Electrical, Computer, In on gineering Conference platform. International phone the mobile of modern ceedings on para-virtualization of evaluation Performance Machines Computing Custom for FPGA’s on ytei CDS SS,21 nentoa ofrneon Conference International In 2013 ISSS), (CODES+ environment. Synthesis paravirtualized a in accelerator optn iuain(PS,21 nentoa ofrneon Conference International 2015 (HPCS), In Simulation systems. Computing multicore criticality mixed in coprocessors for reconfiguration eofiual dpietasevrfrod ae ontv ai.In (CCECE) radio. Engineering Computer cognitive and based Electrical on ofdm Conference Canadian for transceiver adaptive reconfigurable 2010. In Applications. and Methods, Architectures, of Survey zynq. xilinx the on ment PAtechnology. FPGA https://rtos.com/support/extra-tools/ imple- Practical Haas. Harald and Beach, A. Mark modulation. spatial Grant, of M. mentation Peter Wang, Xiang Cheng 26. In systemc. on Forum using 2011 mpsocs (FDL), Languages heterogeneous for estimation mance o rpis ht Paper. White Graphics, tor aino ee0.1 ofdm. ieee802.11g of tation rceig 09IE nentoa ofrneo nelgn optn n Intelligent and Computing Intelligent on Conference International IEEE 2009 - Proceedings optrDsg IC) 00IE nentoa ofrneon Conference International IEEE 2010 (ICCD), Design Computer yq70 l rgambeSCTcnclRfrneMna (UG585) Manual Reference Technical SoC Programmable All Zynq-7000 2010. , https://accellera.org/downloads/standards/systemc eerho itaiaintcnoyfrra-iercngrbesystems reconfigurable real-time for technlogy virtualisation on Research http://www.cecs.uci.edu/~specc/ 2009. , rceig fteIEEE the of Proceedings meddSsesLtes IEEE Letters, Systems Embedded ninJunlo cec n Technology and Science of Journal Indian ae –,Sp 2011. Sept 1–8, pages , EETascin nVhclrTechnology Vehicular on Transactions IEEE 105 2015. , CM’5 ae 9,Wsigo,D,USA, DC, Washington, 99–, pages ’95, FCCM , . ffi adaeSfwr oeinadSystem and Codesign Hardware/Software cesd:2019-02-26. : Accessed . in ata eofiuainmanage- reconfiguration partial cient C optn Surveys Computing ACM rceig fteIE Symposium IEEE the of Proceedings ():14,2014. :41–44, 6(3) , ae –.IE,2013. IEEE, 1–9. pages , ae 6–7,Jl 2015. July 569–576, pages , pcfiainadDesign and Specification ae 0–1.IEEE, 305–312. pages , 2014. , ae –,My2013. May 1–4, pages , cesd:2019-02- : Accessed . ihPerformance High 032t IEEE 26th 2013 2013. , 2014. , 2018. , Theses, . Pro-

PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX PARCOURS PROFESSIONNEL SYNTHESISOF RESEARCH WORKS APPENDIX HnigZbl ofagMle,adAdesGrtae.Acrt TSmdln and modeling RTOS Accurate Gerstlauer. machines. Andreas virtual and xen-arm Müller, Wolfgang for [ZPR Zabel, scheduling Henning Real-time Yoo. Chuck and Yoo Seehwan [ZMG09] Yu. Ke [YY14] [Yu10] + Nklo opks noi aaioau rve ahvn iiro odi,and Soudris, Dimitrios Raghavan, Praveen Papanikolaou, Antonis Zompakis, Nikolaos 13] 02 1016 2013. :140–156, 20(2) scenarios. system e using Enabling plications Catthoor. Francky In SystemC. with analysis 2010. York, of University rnatoso oieComputing Mobile on Transactions elTm prtn ytmMdligadSmlto sn SystemC Using Simulation and Modelling System Operating Real-Time adaedpnetSfwr rnilsadPractice and Principles : Software Hardware-dependent ffi 38 15–87 2014. :1857–1867, 13(8) , in ytmcngrtosfrdnmcwrls ap- wireless dynamic for configurations system cient 106 nentoa ora fwrls nomto networks information wireless of journal International Bibliographie h thesis, PhD . 2009. . IEEE ,