Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation Jean-Christophe Prévotet To cite this version: Jean-Christophe Prévotet. Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation. Hardware Architecture [cs.AR]. Université de Rennes1, 2019. tel- 02415974 HAL Id: tel-02415974 https://tel.archives-ouvertes.fr/tel-02415974 Submitted on 17 Dec 2019 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Mémoire Habilitation à Diriger des Recherches Contributions to the Design of Reconfigurable Embedded Systems: from Modelling to Implementation Jean-Christophe Prévotet Maître de Conférences à l’INSA de Rennes Laboratoire IETR / Équipe de recherche SYSCOM A soutenir le 07/06/2019 devant le jury composé de Rapporteurs Diana Göhringer Professeure au TU, Dresden Christophe Jégo Professeur à ENSEIRB-MATMECA, IMS, Bordeaux Gilles Sassatelli Directeur de recherche CNRS, LIRMM, Montpellier Examinateurs Guy Gogniat Professeur à l’université de Bretagne-Sud, Lab-STICC Christophe Moy Professeur à l’université de Rennes 1, IETR Frédéric Pétrot Professeur à l’université de Grenoble, TIMA Fabienne Nouvel Maître de conférences HDR, INSA de Rennes, IETR Sommaire Part. II 1 Synthesis of Research Works ..............................1 Preliminaries...........................................3 111 Introduction .........................................4 Chap. 1 Summary of studies ............................................ 4 1.1 OS Modelling ............................................... 4 1.2 Reconfiguration Management ...................................... 5 1.3 Power Modelling .............................................. 6 2 Historical Research Background ..................................... 7 2.1 PhD Studies ................................................ 7 2.2 ETIS 2002-2007 .............................................. 7 2.3 IETR 2007- Today ............................................. 7 222 From OS Modelling to Implementation .........................9 Chap. 1 Context and Related Works ........................................ 9 2 A new Design Methodology for Operating Systems .......................... 11 2.1 System Specifications .......................................... 12 2.2 The Dogme Tool .............................................. 14 3 OS Model Description ........................................... 14 3.1 Task Manager Service ........................................... 15 3.2 Scheduling Service ............................................ 16 3.3 The IRQ Manager Service ......................................... 16 3.4 The Communication Service ....................................... 16 3.5 The Intercommunication Service ..................................... 16 3.6 The Reconfiguration Management Model ................................ 17 3.6.1 The HW Task Concept ........................................ 18 3.6.2 The Dispatcher ........................................... 18 3.6.3 The placer .............................................. 19 3.6.4 The Offloader ............................................ 19 4 Modelling Evaluation ........................................... 20 4.1 Description ................................................. 21 4.2 System Model ............................................... 22 4.2.1 Application Model .......................................... 22 4.2.2 Architecture Model ......................................... 23 4.2.3 Kernel Model ............................................. 23 4.3 Simulation and results .......................................... 24 5 OS Code Generation ........................................... 25 5.1 OS Meta-model .............................................. 26 5.2 Model to Model Transformation ..................................... 27 6 From the OS to the Hypervisor ...................................... 27 6.1 Is virtualization compatible with real time constraints ? ........................ 27 6.2 Virtualization Overhead .......................................... 29 6.3 Overhead aware schedulability analysis ................................ 30 6.4 Proposal : Ker-ONE : A lighweight Micro-Hypervisor .......................... 33 iii Sommaire 6.4.1 Overview ............................................... 33 6.4.2 Resource Virtualization ....................................... 34 6.4.3 Event Management ......................................... 35 6.5 Performance Evaluation ......................................... 35 6.5.1 Basic Virtualization Functions Overhead ............................. 35 6.5.2 RTOS Virtualization Evaluation ................................... 38 7 Summary .................................................. 39 333 Reconfiguration Management .............................. 40 Chap. 1 Context and Related Works ........................................ 40 2 General Framework ............................................ 45 3 HW Level .................................................. 45 3.1 HW Task Model .............................................. 45 3.2 PRR HW Management ........................................... 47 3.3 The PRR Monitor ............................................. 48 4 OS Level .................................................. 48 4.1 The Configuration Controller (Virtual Device Manager) ........................ 48 4.2 Other OS services to handle reconfiguration .............................. 49 4.2.1 The Parameters Provider ...................................... 50 4.2.2 The HW Updater ........................................... 50 4.3 The particular case of Virtualization : Security Mechanisms ..................... 50 5 Application level .............................................. 51 5.1 Context ................................................... 51 5.2 Case study : VHA for WI-FI and WiMax heterogeneous networks ................... 52 5.3 The Adaptive Scoring System ...................................... 52 5.4 Towards a Smart Reconfiguration Management ............................ 54 5.4.1 Overview ............................................... 54 5.4.2 Modules Description ........................................ 54 5.5 Results ................................................... 56 6 Performances Evaluation ......................................... 57 6.1 Overhead Analysis ............................................ 59 6.2 Experiments and Results ......................................... 60 6.2.1 Description .............................................. 60 6.2.2 Results ................................................ 61 7 Summary .................................................. 62 444 From Power Modeling to highly Energy-Efficient Devices .............. 64 Chap. 1 Context and Related Works ........................................ 64 2 The Classic Implementation Approach ................................. 67 2.1 Studying New Waveforms ......................................... 68 2.2 Proposed Offline Hardware Platform ................................... 69 2.2.1 System Description ......................................... 69 2.2.2 Studied configurations ....................................... 70 2.2.3 Results ................................................ 71 2.3 Studying the SW limitations ....................................... 73 2.4 The Receive Spatial Modulation scheme ................................ 77 2.4.1 Prototype Description ........................................ 77 2.4.2 Results ................................................ 78 3 Evaluation of FPGA-Based Wireless Communications Systems ................... 79 3.1 Proposed approach ............................................ 80 3.1.1 Scenario Definition ......................................... 80 3.1.2 IP Characterization ......................................... 81 3.1.3 Modeling and High Level Simulation ................................ 82 iv Sommaire 3.2 Use Case .................................................. 84 3.2.1 System Description ......................................... 84 3.2.2 Power Estimation .......................................... 85 3.2.3 Power Estimation Speed-Up .................................... 86 4 Towards Fine grain Modeling ....................................... 86 4.1 Analytical Modeling ............................................ 86 4.2 Extension to other FPGA Devices .................................... 87 4.3 Neural Networks based Modeling .................................... 87 4.3.1 Model Definition ........................................... 89 4.3.2 Results ................................................ 90 5 Summary .................................................. 92 555 Research Perspectives .................................. 93 Chap. 1 Embedded Systems Virtualization .................................... 93 1.1 Hypervisor structure ........................................... 93 1.2 Reconfigurable Hardware Resources Sharing ............................. 94 1.3 VM Scheduling and Off-Loading Service ................................ 94 2 End to End Reconfiguration