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Lord of the X86 Rings: a Portable User Mode Privilege Separation Architecture on X86

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Lord of the X86 Rings: a Portable User Mode Privilege Separation Architecture on X86 Lord of the x86 Rings: A Portable User Mode Privilege Separation Architecture on x86 Hojoon Lee Chihyun Song Brent Byunghoon Kang GSIS, School of Computing, KAIST GSIS, School of Computing, KAIST GSIS, School of Computing, KAIST [email protected] [email protected] [email protected] ABSTRACT privilege separation in user applications. As a result, critical appli- Modern applications are increasingly advanced and complex, and cation secrets such as cryptographic information are essentially inevitably contain exploitable software bugs despite the ongoing treated no differently than a "hello world" string in user memory efforts. The applications today often involve processing of sensitive space. When the control flow of a running user context is compro- information. However, the lack of privilege separation within the mised, there is no access control left to prevent the hijacked context user space leaves sensitive application secret such as cryptographic to access arbitrary memory addresses. keys just as unprotected as a "hello world" string. Cutting-edge Many approaches have been introduced to mitigate the challeng- hardware-supported security features are being introduced. How- ing issue within the boundaries of the existing application memory ever, the features are often vendor-specific or lack compatibility protection mechanisms provided by the operating system. A num- with older generations of the processors. The situation leaves de- ber of work proposed using the process abstraction as a unit of pro- velopers with no portable solution to incorporate protection for the tection by separating a program into multiple processes [6, 27, 38]. sensitive application component. The key idea is to utilize the process separation mechanism pro- We propose LOTRx86, a fundamental and portable approach vided by the OS; these work achieve privilege separation by splitting for user space privilege separation. Our approach creates a more a single program into multiple processes. However, this process- privileged user execution layer called PrivUser through harnessing level separation incurs a significant overhead due to the cost of the underused intermediate privilege levels on the x86 architec- the inter-process communication (IPC) between the processes or ture. The PrivUser memory space, a set of pages within process address space switching that incur TLB flushes. Also, the coarse address space that are inaccessible to user mode, is a safe place for unit of separation still leaves a large attack surface for attackers. application secrets and routines that access them. We implement The direction has advanced through a plethora of works on the the LOTRx86 ABI that exports the privcall interface to users to topic. One prominent aspect of the advancements is the granular- invoke secret handling routines in PrivUser. This way, sensitive ity of protection. Thread-level protection schemes [5, 22, 41] have application operations that involve the secrets are performed in reduced the protection granularity compared to the process-level a strictly controlled manner. The memory access control in our separation schemes while still suffering from performance over- architecture is privilege-based, accessing the protected application head from page table modifications. Shreds presented fine-grained secret only requires a change in the privilege, eliminating the need in-process memory protection using a memory partitioning feature for costly remote procedure calls or change in address space. that has long been present in ARM called Memory Domains [9]. We evaluated our platform by developing a proof-of-concept However, the feature has been deprecated in the 64-bit execution LOTRx86-enabled web server that employs our architecture to mode of the ARM architecture (AARCH64). securely access its private key during SSL connection and thereby In the more recent years, a number of processor architecture mitigating the HeartBleed vulnerability by design. We conducted a revisions and academic works have taken a more fundamental set of experiments including a performance measurement on the approach to provide in-process protection; Intel has introduced PoC on both Intel and AMD PCs, and confirmed that LOTRx86 Software Guard Extensions (SGX) to its new x86 processors to pro- incurs only a limited performance overhead. tect sensitive application and code and data from the rest of the application as well as the possibly malicious kernel [4, 12]. Intel also arXiv:1805.11912v1 [cs.CR] 30 May 2018 offers hardware-assisted in-process memory safety and protection 1 INTRODUCTION features [11, 13] and AMD has announced the plans to embed a similar feature to its future generations of x86 processors [17]. How- User applications today are prone to software attacks, and yet are ever, the support for the new processor features are fragmented; often monolithically structured or lack privilege separation. As not only that the features are not inter-operable across processors a result, adversaries who have successfully exploited a software from different vendors (Intel, AMD), they are also only available vulnerability in an application can access to sensitive in-process on the newer processors. Hypervisor-based application memory code or data that are irrelevant to the exploited module or part protection [8, 32] may serve to be a more portable solution, consid- of the application. Today’s applications often contain secrets that ering the widespread adaption of hypervisors nowadays. However, are too critical to reside in the memory along with the rest of it is not reasonable for a developer to assume that her users are the application contents, as we have witnessed in the incident of using a virtual machine. HeartBleed [18, 42]. The situation presents complications for developers who need to The conventional software privilege model that coarsely divides consider the portability as well as the security of the sensitive data the system privilege into only two levels (user-level and kernel- her program processes. Therefore, we argue that there is a need level) has failed to provide a fundamental solution that can support for an approach that provides a basis for an in-process privilege • We introduce the privcall ABI that allows user layer to separation based on only the portable features of the processor. invoke the privcall routines in a strictly controlled way. We An in-process memory separation should not require a complete also provide necessary software for building an LOTRx86- address space switching to access the protected memory or costly enabled software. page table modifications. • In this paper, we propose a novel x86 user-mode privilege sep- We developed a PoC LOTRx86-enabled web server to demon- aration architecture called The Lord of the x86 Rings (LOTRx86) strate the protection of in-memory private key during SSL architecture. Our architecture proposes a drastically different, yet connection. portable approach for user privilege separation on x86. While the existing approaches sought to retrofit the memory protection mech- 2 BACKGROUND: THE X86 PRIVILEGE anisms within the boundaries of the OS kernel’s support, we pro- ARCHITECTURE pose the creation of a more privileged user layer called PrivUser The LOTRx86 architecture design leverages the x86 privilege struc- that protects sensitive application code and data from the normal tures in a unique way. Hence, it is necessary that we explain the user mode. For this objective, LOTRx86 harnesses the underused x86 privilege system before we go further into the LOTRx86 archi- x86 intermediate Rings (Ring1 and Ring2) with our unique design tecture design. In this section, we briefly describe the x86 privilege that satisfies security requirements that define a distinct privilege concepts focusing on the topics that are closely related to this paper. layer. The PrivUser memory space is a subset of a process memory space that is accessible to when the process context is in PrivUser 2.1 The Ring Privileges mode but inaccessible when in user mode. In our architecture, user Modern operating systems on the x86 architecture adapt the two memory access control is . Therefore, the architec- privileged-based privilege level model in which user programs run in Ring3 and ture does not require costly run-time page table manipulations nor kernel in Ring0. The x86 architecture, in fact, supports four privilege address space switching. layers – Ring0 through Ring3 where Ring0 is the highest privilege We also implement the LOTRx86 ABI that exports the privcall on the system. The x86 architecture’s definition of privilege is interface that supports PrivUser layer invocation from user layer. closely tied to a feature called segmentation. To draw an analogy, the syscall interface is a controlled invocation Segmentation divides virtual memory spaces into segments which of kernel services that involve kernel’s exclusive rights on sensitive are defined by a base address, a limit, anda Descriptor Privilege Level system operations. In our architecture, PrivUser holds an exclusive (DPL) that indicates the required privilege level for accessing the right to application secrets and sensitive routines with a program, segment. A segment is defined by segment descriptor in either Global and user layer must invoke privcalls to enter PrivUser mode Descriptor Table (GDT) or Local Descriptor Table (LDT). The privi- and perform sensitive operations involving the secrets in a strictly lege of an executing context is defined by a 16-bit data structure
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