UG534 (V1.9) February 26, 2019 © Copyright 2009–2019 Xilinx, Inc
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ML605 Hardware User Guide UG534 (v1.9) February 26, 2019 © Copyright 2009–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMER The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. 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AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. Revision History The following table shows the revision history for this document. Date Version Revision 8/17/09 1.0 Initial Xilinx release. 11/17/09 1.1 • Updated Figure 1-1, Figure 1-2, Figure 1-3, Figure 1-11, and Figure 1-14. •Added Figure 1-7, Figure 1-8, Figure 1-10, and Figure 1-13. • Updated Table 1-15 and Table 1-18. • Updated Appendix B, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout and Appendix C, Xilinx Design Constraints. • Minor typographical edits. 01/15/10 1.2 • Updated Figure 1-2, Figure 1-3, Figure 1-17, Table 1-3, Table 1-8, Table 1-9, Table A-34, and Table A-35. Miscellaneous typographical edits. 1/21/10 1.2.1 • Corrected typos in Table 1-31 and Figure 1-28. 05/18/10 1.3 Updated 7. Clock Generation, including Table 1-7. Updated Package Placement column in Table 1-8. Updated Figure 1-17. Added notes about FMC HPC J64 and J63 connectors to 19. VITA 57.1 FMC HPC Connector and 20. VITA 57.1 FMC LPC Connector, respectively. Updated description of PMBus Pod and TI Fusion Digital Power Software GUI in Onboard Power Regulation. Updated Table A-35, Appendix B, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout, and Appendix C, Xilinx Design Constraints. ML605 Hardware User Guide www.xilinx.com UG534 (v1.9) February 26, 2019 Date Version Revision 10/12/10 1.4 Updated description of Fusion Digital Power Software in Onboard Power Regulation. 02/15/11 1.5 Revised note in Table 1-6. Revised oscillator manufacturer information from Epson to SiTime on page page 14, page 30 and page 88. 07/18/11 1.6 Corrected “jitter” to “stability” in section Oscillator (Differential). Added Table 1-32, and table notes in Table 1-31. Revised the FPGA U1 Pins for IIC_SDA_MAIN and IIC_SCL_MAIN in Table 1-18. 06/19/12 1.7 Added [Ref 4] link to Oscillator (Differential). Revised Oscillator Socket (Single-Ended, 2.5V). Revised Figure 1-10. 10/02/12 1.8 Updated Figure 1-2. Added Regulatory and Compliance Information. 02/26/19 1.9 Updated Appendix C, Xilinx Design Constraints, Appendix D, Regulatory and Compliance Information, and the 2. 512 MB DDR3 Memory SODIMM section. UG534 (v1.9) February 26, 2019 www.xilinx.com ML605 Hardware User Guide ML605 Hardware User Guide www.xilinx.com UG534 (v1.9) February 26, 2019 Table of Contents Preface: About This Guide Guide Contents . 7 Additional Documentation . 7 Additional Support Resources. 8 Chapter 1: ML605 Evaluation Board Overview . 9 Additional Information . 9 Features . 10 Block Diagram . 12 Related Xilinx Documents. 12 Electrostatic Discharge Caution. 13 Detailed Description . 13 1. Virtex-6 XC6VLX240T-1FFG1156 FPGA . 16 Configuration . 16 I/O Voltage Rails . 17 2. 512 MB DDR3 Memory SODIMM . 17 3. 128 Mb Platform Flash XL. 22 4. 32 MB Linear BPI Flash . 22 ML605 Flash Boot Options . 23 5. System ACE CF and CompactFlash Connector. 27 6. USB JTAG . 29 7. Clock Generation . 30 Oscillator (Differential) . 30 Oscillator Socket (Single-Ended, 2.5V) . 30 SMA Connectors (Differential) . 32 8. Multi-Gigabit Transceivers (GTX MGTs) . 34 9. PCI Express Endpoint Connectivity . 35 10. SFP Module Connector . 38 11. 10/100/1000 Tri-Speed Ethernet PHY . 39 SGMII GTX Transceiver Clock Generation . 40 12. USB-to-UART Bridge. 42 13. USB Controller . 43 14. DVI Codec . 44 15. IIC Bus . 45 8 Kb NV Memory . 47 16. Status LEDs . 48 Ethernet PHY Status LEDs . 49 FPGA INIT and DONE LEDs . 50 17. User I/O . 50 User LEDs . 51 User Pushbutton Switches . 52 User DIP Switch . 53 User SMA GPIO . 54 LCD Display (16 Character x 2 Lines). 55 18. Switches . 56 ML605 Hardware User Guide www.xilinx.com 5 UG534 (v1.9) February 26, 2019 Power On/Off Slide Switch SW2 . 56 FPGA_PROG_B Pushbutton SW4 (Active-Low). 57 SYSACE_RESET_B Pushbutton SW3 (Active-Low) . 57 System ACE CF CompactFlash Image Select DIP Switch S1. 58 Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2 . 59 19. VITA 57.1 FMC HPC Connector . 60 20. VITA 57.1 FMC LPC Connector . 66 21. Power Management . 68 AC Adapter and Input Power Jack/Switch . 68 Onboard Power Regulation . 69 22. System Monitor.