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Run-Time Customization of a Soft-Core Cpu on an Fpga

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Run-Time Customization of a Soft-Core Cpu on an Fpga RUN-TIME CUSTOMIZATION OF A SOFT-CORE CPU ON AN FPGA A DISSERTATION SUBMITTED TO THE UNIVERSITY OF MANCHESTER FOR THE DEGREE OF MASTER OF SCIENCE IN THE FACULTY OF ENGINEERING AND PHYSICAL SCIENCES 2015 By Rehab Abdullah Shendi School of Computer Science Contents Abstract ................................................................................................................... 8 Declaration .............................................................................................................. 9 Copyright .............................................................................................................. 10 Acknowledgements ............................................................................................... 11 Dedication ............................................................................................................. 12 1 Introduction ........................................................................................................ 13 1.1 Aim and Objectives ...................................................................................... 14 1.2 Report Outline ............................................................................................. 15 2 Background ........................................................................................................ 16 2.1 Reconfigurable Computing .......................................................................... 16 2.1.1 History ................................................................................................... 16 2.1.2 FPGA ..................................................................................................... 17 2.1.3 Reconfiguration Hardware ..................................................................... 20 2.1.4 Partial Reconfiguration .......................................................................... 21 2.2 Microprocessor Architecture ........................................................................ 26 2.2.1 RISC Microprocessor ............................................................................ 26 2.2.2 Soft-Core Microprocessor ...................................................................... 27 2.2.3 MIPS Architecture.................................................................................. 28 2.3 Reconfigurable CPU Instruction Set Extensions .......................................... 30 2.3.1 Custom Instructions in Hardware .......................................................... 31 2.3.2 Custom Instructions in Software ............................................................ 32 2.4 Design Considerations ................................................................................. 33 2.5 Previous Work ............................................................................................. 35 2.5.1 Instruction Set Extension ....................................................................... 35 2.5.2 Partial Reconfiguration .......................................................................... 35 3 System Design and Methodology ...................................................................... 37 2 3.1 System Development Methodology ............................................................. 37 3.2 Implementation Tools .................................................................................. 44 3.2.1 Hardware Description Language ........................................................... 44 3.2.2 Xilinx ISE (Xilinx, 2013) : ....................................................................... 45 3.2.3 Cross compiler: ..................................................................................... 46 3.2.4 FPGA Platform: ..................................................................................... 46 3.2.5 GoAhead ............................................................................................... 47 3.3 System Design............................................................................................. 47 3.3.1 System Definition and Scope ................................................................ 48 3.3.2 System Architecture and Components .................................................. 48 4 Implementation .................................................................................................. 54 4.1 Baseline MIPS Soft-Core ............................................................................. 54 4.2 Custom Instruction in Software .................................................................... 57 4.3 Configuration Controller Modules ................................................................ 59 4.4 Custom Instruction in Hardware .................................................................. 61 4.5 Challenges During Implementation .............................................................. 69 5 Testing, Results and Evaluation ......................................................................... 70 5.1 Testing ......................................................................................................... 70 5.2 Results ......................................................................................................... 76 5.3 Evaluation ................................................................................................... 77 6 Conclusions and Future Work ............................................................................ 81 6.1 Conclusions ................................................................................................. 81 6.2 Future Work ................................................................................................. 81 Works Cited .......................................................................................................... 83 Appendix A - MIPS CPU ....................................................................................... 87 Appendix B - Trap handler based on MUX ........................................................... 96 Appendix C - Trap handler based on ICAP ........................................................... 98 3 (Word count 16033) 4 List of Tables Table 1 Configuration speeds with ICAP achievement (Hansen, Koch and Torresen, 2011). ................................................................................................... 25 Table 2 Type of MIPS instructions (Fritzell,2013). ................................................ 30 Table 3 Descriptions of using ICAP_SPARTAN6 Port (Xilinx Inc, 2015). ............. 52 Table 4 Custom instructions’ address and ID........................................................ 60 Table 5 An example of bitstream for the IPROG command using ICAP (Xilinx Inc, 2015). .................................................................................................................... 61 Table 6 Resource requirements for Configuration controller. ................................ 76 Table 7 Resource requirements for Custom modules. .......................................... 77 Table 8: comparison between Xilinx Embedded processors with our soft-core and their Performance. ................................................................................................ 79 Table 9 Software requirements. ............................................................................ 80 5 List of Figures Figure 1 Classification of FPGAs (Koch, 2013). .................................................... 21 Figure 2 Baseline model of partial reconfiguration (Koch, 2013)........................... 22 Figure 3 Styles of reconfigurable modules placement. (a) Island style. (b) Slot style. (c) Grid style (Koch, 2013). .......................................................................... 23 Figure 4 a) a typical CPU b) extensions CPU with Reconfigurable Instructions (Koch, 2013). ........................................................................................................ 31 Figure 5 Design and development tools (Minev and Kukenska, 2007). ................ 34 Figure 6: The general approach of the system development stages (Soft, 2013). 37 Figure 7: A step-by-step design and implementation method. .............................. 38 Figure 8: First step, system overview. ................................................................... 39 Figure 9 Third Step, system overview. .................................................................. 40 Figure 10: Four step, system overview. ................................................................ 40 Figure 11 Five step: system overview of the first approach. ................................. 42 Figure 12 Five step: system overview of the second approach. (Xilinx, 2012). ..... 43 Figure 13 Xilinx Spartan-6 LX16 FPGA platform (Nexys3™ Board Reference Manuall, 2013). ..................................................................................................... 46 Figure 14 The final system design. ....................................................................... 49 Figure 15 The non-pipelined MIPS shows the most important signals and logics (Fritzell, 2013). ...................................................................................................... 50 Figure 16: ICAP Primitive (Xilinx Inc, 2015). ......................................................... 52 Figure 17 Custom Module Logic. .......................................................................... 53 Figure 18 The Program Counter process overview that consists of extra logic and flip-flops to handle branch and jump instructions. (Fritzell,
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