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Network Driver for Micro Os Xv6

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Network Driver for Micro Os Xv6 NETWORK DRIVER FOR MICRO OS XV6 A Project Presented to the faculty of the Department of Computer Science California State University, Sacramento Submitted in partial satisfaction of the requirements for the degree of MASTER OF SCIENCE in Computer Science by Anmoldeep Singh Sandhu SPRING 2020 © 2020 Anmoldeep Singh Sandhu ALL RIGHTS RESERVED ii NETWORK DRIVER FOR MICRO OS XV6 A Project by Anmoldeep Singh Sandhu Approved by: __________________________________, Committee Chair Dr. Jinsong Ouyang __________________________________, Second Reader Dr. Jingwei Yang ____________________________ Date iii Student: Anmoldeep Singh Sandhu I certify that this student has met the requirements for format contained in the University format manual, and this thesis is suitable for electronic submission to the library. Credit is awarded for the Project. __________________________, Graduate Coordinator ___________________ Dr. Jinsong Ouyang Date Department of Computer Science iv Abstract of NETWORK DRIVER FOR MICRO OS XV6 by Anmoldeep Singh Sandhu The network driver is one of the primary requirements for any operating system. Xv6 is a micro-operating system based on version 6 Unix. The latest version of xv6 does not have support for the ethernet driver or the four-layer UDP/IP model. Our work extends the xv6 operating system to support a functioning network driver with the capability of handling a packet burst. This Project also adds support for UDP/IP and Ethernet protocol to the xv6 operating system. _______________________ Committee Chair Dr. Jinsong Ouyang _____________________ Date v ACKNOWLEDGMENTS I am thankful to Dr. Ouyang for providing me the opportunity to learn new skills in the field of driver development. Dr. Ouyang showed trust in me in carrying out this Project. Dr.Ouyang's course on advanced operating systems is my inspiration for this Project. Dr. Ouyang was always available for queries and provided regular feedback and helped me finish this Project. I would also like to thank Dr. Jingwei Yang as my second reader for his efforts in reviewing and giving feedback on my project report. I want to thank my friends for giving me valuable input while developing this Project. Many thanks to my family for moral support. vi TABLE OF CONTENTS Page Acknowledgments .................................................................................................................... vi List of Tables ........................................................................................................................... ix List of Figures .......................................................................................................................... x Chapter 1.Introduction……..…………………………………………………………………………..1 1.1 Overview ................................................................................................................ 1 1.2 Project Design Overview ....................................................................................... 1 1.3 Software Stack........................................................................................................ 2 1.2 Report Organization ............................................................................................... 4 2.PCI Initialization ................................................................................................................... 5 2.1 Introduction to PCI ................................................................................................ 5 2.2 PCI Initialization. .................................................................................................. 6 3.Device Initialization .............................................................................................................. 9 3.1 Device Initialization Introduction ......................................................................... 9 3.2 Receive Initialization ............................................................................................. 9 3.3 Transmit Initialization ......................................................................................... 13 4. Packet Reception and Transmission ............................................................................... 16 4.1 Receiving Packets ............................................................................................... 16 4.2 Interrupt handling ................................................................................................ 16 4.3 Buffer Reading Algorithm Register level ........................................................... 17 4.4 Concurrency in Packet Reception ...................................................................... 21 4.4 Packet transmission Register level ...................................................................... 22 5. Network Stack ................................................................................................................ 25 vii 5.1 Network Stack Introduction ................................................................................ 25 5.2 UDP Layer 3........................................................................................................ 25 5.3 IP Protocol Layer 2 ............................................................................................. 28 5.4 Data link layer 1 .................................................................................................. 31 6. Testing Traffic ................................................................................................................ 33 6.1 Testing Setup. ...................................................................................................... 33 6.2 Testing Reception of Payload ............................................................................. 33 6.3 Traffic Transmission ........................................................................................... 34 6.4 Workload Testing ................................................................................................ 36 7. Conclusion and Future .................................................................................................... 40 Bibliography ........................................................................................................................... 41 viii LIST OF TABLES Tables Page Table 1: Interrupt bits………………………………… ............ .……………………………….9 Table 2: Receive control register bits ...................................... .……………………………….13 Table 3: Transmission control register values .................................. .…………………………15 Table 4: Interrupts cause register bit description ............................. .…………………………16 Table 5: Drop rate with OS buffer size 2048 ................................... .…………………………38 Table 6: Drop rate with OS buffer size 131072 ............................... .…………………………38 Table 7: Drop rate with OS buffer size 524288 ............................... .…………………………38 Table 8: Drop rate with OS buffer size 786432 ............................... .…………………………39 ix LIST OF FIGURES Figures Page Figure 1: Module Design Overview .......................................... .……………………………….2 Figure 2: QEMU and host machine stack ...................................... …………………………….3 Figure 3: Device PCI configuration ...................... ………….………………………………….5 Figure 4: PCI mandatory registers ...................................................... ………………………….6 Figure 5: PCI initialization code ........................................................ ………………………….7 Figure 6: Command register bit specifications ................................... ………………………….7 Figure 7: Packet Receive descriptor ................................................. ………………………….10 Figure 8: receive descriptor .............................................................. ………………………….10 Figure 9: Receive Descriptor status fields first three bits ................. ………………………….11 Figure 10: Receive descriptor and memory buffer pointer array ..... ………………………….12 Figure 11: Receive initialization code .............................................. ………………………….13 Figure 12: Transmit Descriptor ........................................................ ………………………….14 Figure 13: Transmit descriptor definition ........................................ ………………………….14 Figure 14: Transmit initialization code ............................................ ………………………….15 Figure 15: Interrupt handler ............................................................. ………………………….17 Figure 16: buffer between driver and network stack ........................ ………………………….18 Figure 17: Buffer sharing between driver and network stack thread .... ………………………19 Figure 18: Circular queue for receive descriptor array ......................... ………………………20 Figure 19: Packet read code .................................................................. ………………………20 Figure 20: concurrency between driver and network stack thread ........ ………………………22 Figure 21: Thread reading the memory_driver_thread buffer ............... ………………………22 Figure 22: Packet received by transmission layer ................................. ………………………22 x Figure 23: Transmit descriptor fields .................................................... ………………………23 Figure 24: Packet transmission code ..................................................... ………………………24 Figure 25: UDP header fields ................................................................ ………………………26 Figure 26: UDP header format .............................................................
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