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Operand Specifier Processing Suropaisches Patentamt 0 349 124 J) European Patent Office © Publication number: Office europeen des brevets © EUROPEAN PATENT APPLICATION © Application number: 89305430.4 © Int. CI.4: G06F 9/34 © Date of filing: 30.05.89 © Priority: 27.06.88 US 212348 © Applicant: DIGITAL EQUIPMENT CORPORATION © Date of publication of application: 111 Powdermill Road 03.01.90 Bulletin 90/01 Maynard Massachusetts 01754-1418(US) © Designated Contracting States: © inventor: Uhler, Michael G. DE FR GB 1200 Concord Road Marlborough Massachusettes 01752(US) Inventor: Brown III, John F. 42 Catherine Drive Northborough Massachusettes 06532(US) © Representative: Goodman, Christopher et al Eric Potter & Clarkson 14 Oxford Street Nottingham NG1 5BP(GB) © Operand specifier processing. © A method of specifying the operands for a microcoded CPU employs a combination of a set of microinstruction routines for generic operand modes, \ along with hardware primitives for selecting various \ Decode of specific types .of operand treatment. a unit XQUEHCtft machine-level instruction produces an entry point for of the set of the microstore to select one generic JO operand modes, and also decode of the instruction control bits that are used directly to select /I! produces n the hardware the specific operand type or use by ST0HC primitives. In this way, branching is avoided in the UNIT microinstruction sequences for operand specifying, ^but yet the amount of microcode needed is a mini- IDI MANMO-CNT j UNIT _/ 05 taiBttct CO CL HI 1^— MtMORY UNIT Xerox Copy Centre I =P 0 349 124 A2 2 OPERAND SPECIFIER PROCESSING This invention relates generally to the operation Often, a single machine level instruction in- of digital computers, and in particular relates to the volves several CPU register transfers, each initiated implementation of complex instruction sets in high by the assertion of one or more control signals. In performance computer systems. the typical case of a simple memory read, for In its simplest form, a digital computer consists 5 example, the control unit would cause the following of five functionally independent main parts: input, steps to be taken: First, after reading from memory memory, arithmetic and logic, output, and control the machine-level instruction requesting the mem- units. In the traditional organization of a so-called ory read, the address of the desired memory loca- 'single store' or 'stored program' computer, activity tion would be . loaded into the memory address within the computer is governed by a program io register via a CPU bus; the control unit accom- consisting of a set of instructions stored in main plishes this by asserting a signal which tells the memory. An instruction specifies an operation to be memory address register to latch the data currently performed by the computer. Individual instructions on the CPU bus. Once this is done, the control unit are brought from main memory into the processor, would initiate a read at the memory location speci- which decodes and executes them. In addition to 15 fied in the memory address register by asserting a the machine-level instructions, numerical data used different control signal. Next, when the desired as operands for the instructions are also stored in location has been read, the memory unit would the same main memory space, hence the name make the value available on the CPU bus, and the 'single store' computer. control unit would assert another control signal In modern computers, the arithmetic and logic 20 causing the contents of the CPU bus to be latched unit (ALU) and its associated control circuitry are into the memory data register. Here the value frequently grouped together to form a so-called would be subsequently available, via the CPU bus, central processing unit, or CPU, which can be to any of the other functional units which require it. implemented as a monolithic semiconductor de- Typically, machine-level instructions consist of vice. A CPU usually contains, in addition to the 25 at least two parts: an operation code or 'opcode' ALU, a collection of one-word storage locations, which specifies which operation is to be performed, called registers, used to hold instructions or data and one or more address fields which specify during program execution. Some CPU registers are where the data values (operands) used for that all-purpose storage locations which can be used to operation can be found. A computer executes one hold any intermediate values which the CPU might 30 machine-level instruction in what may be called an need to temporarily save. Other registers have spe- instruction cycle, and an instruction cycle usually cifically defined uses. For example, a CPU tradi- includes two parts. During the first part, called the tionally has a register called the program counter fetch cycle, the opcode of the next instruction (the (PC) which holds the address in the main memory instruction pointed to by the PC) is loaded into the space of the next (or currently executing) instruc- 35 CPU's instruction register. Once the opcode is in tion. In addition, a CPU will typically have an in- the IR, the second part, called the execute cycle, is struction register (IR) which holds the instruction performed (often each of these parts will require fetched from memory that is currently being ex- more than one state time or clock cycle. In the ecuted by the computer. A CPU will also usually execute cycle, the controller interprets the opcode have additional special purpose registers, such as 40 and executes the instruction by sending out the a memory address register and a memory data appropriate sequence of control signals to cause register, which are defined to contain, respectively, data to be transferred or to cause an arithmetic or the main memory address of a word to be written logical operation to be performed by the ALU. In or read by the CPU, and a data value to be stored many cases, the execution cycle of an instruction in or received from memory. Each of the functional 45 will include the fetching of operands specified by units of a CPU is able to pass data to and from that instruction. For example, for a simple 'ADD' other units via one or more CPU busses, and instruction, the location of two values to be added transfers between the units are initiated and con- together must be specified in the instruction, and trolled by the control unit. The sequence of individ- these two values must be fetched and brought into ual steps required for a computer to execute a so CPU registers so that the ALU will have access to machine-level instruction is directed by a control them. unit, which is responsible for asserting control sig- The collection of machine-level instructions that nals to initiate transfers of data from one register to a CPU supports is called its instruction set. Within another, or between main memory and registers, or the computer, instructions are represented as se- between registers and the ALU, via a CPU bus. quences of bits arranged in memory words, iden- 2 P 0 349 124 AZ ifying the constituent elements of the instruction, tun lengtn aaaress ot tne operana. i wo mam mem- n addition to the opcode and the source operands ory accesses are required to obtain an operand operands used as inputs for the specified opera- specified in an indirect addressing mode. Other ion), an instruction might also identify the desired addressing modes commonly supported by pro- iestination of the operation's result, as well as the 5 cessing units include register indirect addressing, □cation of the next instruction to be executed. This in which a CPU register specified in the instruction de- !uggests that a plurality of operand fields may contains the address in main memory of the >xist for a given instruction. The arrangement of sired operand, and various kinds of displacement ields in an instruction is known as the instruction addressing, in which an explicit offset value con- ormat. Depending upon how much information o tained in the is used as a displacement from an- nust be specified, an instruction can be one or other address included in the instruction, whose obtain the nore memory words long. Some simple instruc- contents are added to the offset value to ions, like 'HALT', might require no operands, and address of the operand. :an be represented in a single memory word con- Since the control unit is responsible for initiat- aining only the opcode for that instruction. Other es ing all activity within a CPU, acceptable system nstructions, called unary instructions, might require performance depends upon efficient operation of he specification of a single operand. Unary instruc- the control unit. Two basic strategies exist for im- ions, such as 'BRANCH', 'INCREMENT', or plementation of a control unit. The first, known as a CLEAR' can be contained in a single memory hardwired controller implementation, involves the vord containing both the opcode and the operand >o use of combinatorial logical hardware that produces specifier, or in two words, one for the opcode and the appropriate sequence of output control signals jne for the operand specifier. Likewise, a binary in response to a particular opcode. The primary nstruction, like 'ADD' or 'SUBTRACT', requires the inputs to a hardwired controller are the instruction specification of two operands, and can be con- register and a clock. The combinatorial logic in the ained either in a single word which contains the 25 hardwired controller identifies (decodes) the unique Dpcode and the identity of both operands, or in two opcode associated with every instruction, and as- control x more words. Frequently, a CPU's instruction set serts the appropriate sequence of output /vill include instructions of varying formats.
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