Operand Specifier Processing

Suropaisches Patentamt 0 349 124 J) European Patent Office © Publication number: Office europeen des brevets

© Designated Contracting States: © inventor: Uhler, Michael G. DE FR GB 1200 Concord Road Marlborough Massachusettes 01752(US) Inventor: Brown III, John F. 42 Catherine Drive Northborough Massachusettes 06532(US)

© A method of specifying the operands for a microcoded CPU employs a combination of a set of microinstruction routines for generic operand modes, \ along with hardware primitives for selecting various \ Decode of specific types .of operand treatment. a unit XQUEHCtft machine-level instruction produces an entry point for of the set of the microstore to select one generic JO operand modes, and also decode of the instruction control bits that are used directly to select /I! produces n the hardware the specific operand type or use by ST0HC primitives. In this way, branching is avoided in the UNIT microinstruction sequences for operand specifying, ^but yet the amount of microcode needed is a mini- IDI

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OPERAND SPECIFIER PROCESSING

This invention relates generally to the operation Often, a single machine level instruction in- of digital computers, and in particular relates to the volves several CPU register transfers, each initiated implementation of complex instruction sets in high by the assertion of one or more control signals. In performance computer systems. the typical case of a simple memory read, for In its simplest form, a digital computer consists 5 example, the control unit would cause the following of five functionally independent main parts: input, steps to be taken: First, after reading from memory memory, arithmetic and logic, output, and control the machine-level instruction requesting the mem- units. In the traditional organization of a so-called ory read, the address of the desired memory loca- 'single store' or 'stored program' computer, activity tion would be . loaded into the memory address within the computer is governed by a program io register via a CPU bus; the control unit accom- consisting of a set of instructions stored in main plishes this by asserting a signal which tells the memory. An instruction specifies an operation to be memory address register to latch the data currently performed by the computer. Individual instructions on the CPU bus. Once this is done, the control unit are brought from main memory into the processor, would initiate a read at the memory location speci- which decodes and executes them. In addition to 15 fied in the memory address register by asserting a the machine-level instructions, numerical data used different control signal. Next, when the desired as operands for the instructions are also stored in location has been read, the memory unit would the same main memory space, hence the name make the value available on the CPU bus, and the 'single store' computer. control unit would assert another control signal In modern computers, the arithmetic and logic 20 causing the contents of the CPU bus to be latched unit (ALU) and its associated control circuitry are into the memory data register. Here the value frequently grouped together to form a so-called would be subsequently available, via the CPU bus, central processing unit, or CPU, which can be to any of the other functional units which require it. implemented as a monolithic semiconductor de- Typically, machine-level instructions consist of vice. A CPU usually contains, in addition to the 25 at least two parts: an operation code or 'opcode' ALU, a collection of one-word storage locations, which specifies which operation is to be performed, called registers, used to hold instructions or data and one or more address fields which specify during program execution. Some CPU registers are where the data values (operands) used for that all-purpose storage locations which can be used to operation can be found. A computer executes one hold any intermediate values which the CPU might 30 machine-level instruction in what may be called an need to temporarily save. Other registers have spe- instruction cycle, and an instruction cycle usually cifically defined uses. For example, a CPU tradi- includes two parts. During the first part, called the tionally has a register called the program counter fetch cycle, the opcode of the next instruction (the (PC) which holds the address in the main memory instruction pointed to by the PC) is loaded into the space of the next (or currently executing) instruc- 35 CPU's instruction register. Once the opcode is in tion. In addition, a CPU will typically have an in- the IR, the second part, called the execute cycle, is struction register (IR) which holds the instruction performed (often each of these parts will require fetched from memory that is currently being ex- more than one state time or clock cycle. In the ecuted by the computer. A CPU will also usually execute cycle, the controller interprets the opcode have additional special purpose registers, such as 40 and executes the instruction by sending out the a memory address register and a memory data appropriate sequence of control signals to cause register, which are defined to contain, respectively, data to be transferred or to cause an arithmetic or the main memory address of a word to be written logical operation to be performed by the ALU. In or read by the CPU, and a data value to be stored many cases, the execution cycle of an instruction in or received from memory. Each of the functional 45 will include the fetching of operands specified by units of a CPU is able to pass data to and from that instruction. For example, for a simple 'ADD' other units via one or more CPU busses, and instruction, the location of two values to be added transfers between the units are initiated and con- together must be specified in the instruction, and trolled by the control unit. The sequence of individ- these two values must be fetched and brought into ual steps required for a computer to execute a so CPU registers so that the ALU will have access to machine-level instruction is directed by a control them. unit, which is responsible for asserting control sig- The collection of machine-level instructions that nals to initiate transfers of data from one register to a CPU supports is called its instruction set. Within another, or between main memory and registers, or the computer, instructions are represented as se- between registers and the ALU, via a CPU bus. quences of bits arranged in memory words, iden-

2 P 0 349 124 AZ ifying the constituent elements of the instruction, tun lengtn aaaress ot tne operana. i wo mam mem- n addition to the opcode and the source operands ory accesses are required to obtain an operand operands used as inputs for the specified opera- specified in an indirect addressing mode. Other ion), an instruction might also identify the desired addressing modes commonly supported by pro- iestination of the operation's result, as well as the 5 cessing units include register indirect addressing, □cation of the next instruction to be executed. This in which a CPU register specified in the instruction de- !uggests that a plurality of operand fields may contains the address in main memory of the >xist for a given instruction. The arrangement of sired operand, and various kinds of displacement ields in an instruction is known as the instruction addressing, in which an explicit offset value con- ormat. Depending upon how much information o tained in the is used as a displacement from an- nust be specified, an instruction can be one or other address included in the instruction, whose obtain the nore memory words long. Some simple instruc- contents are added to the offset value to ions, like 'HALT', might require no operands, and address of the operand. :an be represented in a single memory word con- Since the control unit is responsible for initiat- aining only the opcode for that instruction. Other es ing all activity within a CPU, acceptable system nstructions, called unary instructions, might require performance depends upon efficient operation of he specification of a single operand. Unary instruc- the control unit. Two basic strategies exist for im- ions, such as 'BRANCH', 'INCREMENT', or plementation of a control unit. The first, known as a CLEAR' can be contained in a single memory hardwired controller implementation, involves the vord containing both the opcode and the operand >o use of combinatorial logical hardware that produces specifier, or in two words, one for the opcode and the appropriate sequence of output control signals jne for the operand specifier. Likewise, a binary in response to a particular opcode. The primary nstruction, like 'ADD' or 'SUBTRACT', requires the inputs to a hardwired controller are the instruction specification of two operands, and can be con- register and a clock. The combinatorial logic in the ained either in a single word which contains the 25 hardwired controller identifies (decodes) the unique Dpcode and the identity of both operands, or in two opcode associated with every instruction, and as- control x more words. Frequently, a CPU's instruction set serts the appropriate sequence of output /vill include instructions of varying formats. In such signals necessary to accomplish the requested instruc- a case, the CPU controller must decode an instruc- task. Clearly, even for a moderately sized :ion's opcode, and then fetch additional words as 30 tion set, the controller must contain a large amount -equired by the format associated with that particu- of logic hardware for distinguishing between the the ar instruction. many instruction formats that may be used, In order to reference a large range of locations many different operations that can be performed, n the specification of operands, the instruction sets and for asserting the correct control signals during 3f most computers support a variety of different 35 the various phases of each of the various instruc- methods, called addressing modes, for indicating tion cycles. the effective address of operands in a machine- A simpler approach to the design of processor level instruction. The simplest method of specifying control units is known as a microprogrammed im- an operand in a machine-level instruction is imme- plementation. In a microprogrammed controller, in diate or literal addressing, in which the value of the 40 each instruction opcode indicates an address a operand is included in the machine-level instruction special CPU memory where CPU control words itself. This mode is useful in defining constants and called microinstructions are stored. Each microin- initial values of variables, and no main memory struction contains information about which control references are needed to obtain the operand. Like- lines to assert when that microinstruction is ex- wise, a register addressing mode requires no main 45 ecuted by the controller. A single machine-level memory accesses, since the operand is stored in a instruction thus corresponds to a specific sequence CPU register which is specified in the machine- of one or more microinstructions to be executed (a level instruction. Another simple form of operand microprogram routine). Microinstructions typically specification is called direct addressing, wherein reside in a dedicated area of CPU read-only-mem- the main memory address of the operand is sup- 50 ory (ROM) called the micro-store. Upon receiving plied in the instruction. Direct addressing requires an instruction's opcode in the IR, a microprogram- only one memory reference to obtain the operand, med controller would derive from the opcode an but is limited to specifying addresses which are entry point into a microprogram routine in the small enough to fit in the address field of the micro-store. Starting at this entry point, microin- instruction, which can be smaller than one memory 55 structions are read one at a time from the microword. Indirect addressing modes overcome this store, just as machine-level instructions are fetched limitation by providing in the instruction an address from main memory, and used by the controller to of a word in main memory which in turn contains a determine which control signals to assert. In what 5 EP 0 349 124 A2 6 is called a fully horizontal microinstruction format, instruction set comprised of a relatively small num- each bit of a microinstruction corresponds to a ber of simple instructions. The machine-level single control signal, so that a one in a certain bit instructions in a RISC computer typically execute position corresponds to the assertion of that control in one clock cycle, have fixed instruction formats, signal, and a zero in the same bit position cor- 5 and support only a few simple addressing modes. responds to the de-assertion of that control signal. In order to take full advantage of the speed of RISC Alternatively, with a so-called fully vertical microin- instruction execution, RISC computers customarily struction format, the bits of the microinstruction employ hardwired controllers instead of microprog- must themselves be decoded to determine which rammed controllers. control signals to assert. In the fully horizontal 10 The general-purpose instruction set most com- format, n bits are required to represent the state of monly implemented in computers represents a n control signals, while in the fully vertical format, n compromise between the smaller program size and bits can be used to represent the state of 2" control larger controller micro-store size of CISC architec- signals. A diagonal microinstruction format repre- tures and the larger program size and smaller sents a compromise between the speed of the fully rs controller size of RISC systems. The wide variety horizontal format and the small microinstruction of instruction formats and addressing modes in size of the fully vertical format. In a diagonal for- CISC systems makes instruction decoding and mat, the bits of a microinstruction are grouped into operand fetching slower and more involved, while fields, where each field corresponds to the control the simpler operations and minimal addressing signals associated with a particular system re- 20 modes of RISC systems require relatively longer source (main memory, ALU, CPU bus, CPU regis- programs to accomplish similar tasks. ters, and so on). A field of k bits can be used to In a microprogrammed computer, the complex- specify up to 2k control signals associated with a ity of a machine-level instruction set clearly has an particular resource. impact on the size of the micro-store containing the A computer is often characterized by the in- 25 microinstructions to support the instruction set. The struction set supported by its processing unit. The size of the micro-store depends not only on the instruction set determines many of the functions number of instructions supported, but also on the performed by the CPU and thus has a significant complexity of these operations and the range of effect on the implementation of the CPU and the addressing modes available to the instructions. The overall performance of the computer system. In 30 performance characteristics of the computer sys- practice, at least two differing approaches to the tem are also affected by these factors, since com- design of instruction sets exist in the art. One, plex instructions involve more CPU register trans- referred to as a complex instruction set, attempts fers than simpler instructions and thus require to make the machine-level instructions more com- more microinstructions and more clock cycles to patible with instructions of higher-level program- 35 complete. Furthermore, as the instruction set's ming languages. Complex instruction sets typically complement of addressing modes increases, a include a large number of different instructions, larger amount of microcode is required for operand ranging from simple operations such as MOVE, to address calculation. more complex operations, such as vector manipu- Microcode processing of operand specifiers in- lation, matrix operations, and sophisticated 40 volves dispatching to a microprogram routine which arithmetic functions. The instructions in a complex will perform the actions necessary to identify the instruction set computer (CISC) usually support a location of an operand, and then taking the appro- wide range of operand addressing modes, and priate action based on the use of the operand in have widely varying formats. The use of complex the given instruction. In lower performance sys- instruction sets is based on the reasoning that 45 terns, the processing of all specifier types may be since a complex instruction would do more than a done by a single general microprogram routine t simple instruction, fewer instructions would be which resolves differences in operand specification needed for a given program, thus reducing the by using conditional branching statements in the number memory fetches involved in the execution microprogram routine. Higher performance sys- of a program. The increasing availability of faster, 50 terns, on the other hand, may provide a dedicated larger ROMs further suggested that implementing microprogram routine for each possible combina- complicated software functions in larger micro-code tion of operand specifiers used with a particular routines would result in faster, easier-to-use com- machine-level instruction. This dedicated routine puters, and lower costs for software development. method allows the system to achieve maximum An alternative approach to instruction set de- 55 performance by eliminating the need for slow con- sign employs a reduced instruction set. Reduced ditional branching within the microprogram. The instruction set computer (RISC) architecture refers general purpose routine method, on the other hand, to a broad design philosophy characterized by an requires much less micro-store memory space than

4 :P 0 349 124 A2 he dedicated routine method, but is also slower. -Byte displacement: The present invention is aimed at overcoming The address of the operand is calculated by adding some of the undesirable features associated with a byte displacement to the contents of a general he implementation of complex instructions sets purpose CPU register; vhich support a variety of operand addressing 5 -Byte displacement deferred: nodes. Specifically, this invention suggests a strat- The sum of a byte displacement and the contents read sgy for reducing the micro-store memory dedi- of a general purpose CPU register is used to :ated to operand specifier processing, while also from memory the main memory address of the educing the size and the time spent by a proces- operand; sor in obtaining the necessary operands specified ro -Word displacement: n complex instructions. The address of the operand is calculated by adding This invention describes a method and appara- a two-byte displacement to the contents of a gen- us for implementing high performance, low over- eral purpose CPU register; lead microcoded operand specifier processing by -Word displacement deferred: jrouping similar specifier types together and pro- rs The sum of a two-byte displacement and the con- dding a general routine for each. Hardware primi- tents of a general purpose CPU register is used to ives are then used to resolve the differences in read from memory the address of the operand; specifier type within each group. In this way, the -Longword displacement: present invention combines the performance char- The address of the operand is calculated by adding acteristics of the dedicated microprogram routine 20 a four-byte displacement to the contents of a gen- nethod of operand specifier processing with the eral purpose CPU register. -Longword displace- minimal micro-store size of the general micropro- ment deferred: and the gram routine method of operand specifier process- The sum of four-byte displacement con- is used to ng. tents of a general purpose CPU register The invention is directed towards computer 25 read from memory the address of the operand. systems which support many or all of the following The above collection of operand specification tiirteen operand addressing modes typically found modes is one that is representative of the address- n CISC architectures (it being understood that oth- ing mode sets commonly found in complex instruc- sr names may be used for these modes, and that tion set architectures. In addition, instruction set arocessors may employ additional modes or may 30 implementations frequently recognize the distinc- 3mit some of these modes): tion between at least five different ways that ■Literal: operands may be used by a given instruction. This The operand is included as part of the specifier in operand usage information must be provided to the the machine-level instruction stream; memory unit during execution of a machine-level ■Index: 35 instruction so that the necessary access privilege The address of the operand is calculated from a to operand memory locations can be confirmed, base address and an index contained in a general and so that the memory access can be initiated. In read purpose CPU register; particular, an instruction may require access ■Register: to an operand, write access to an operand, or both The operand is the value contained in a general 40 read and write (modify) access to the operand. the purpose CPU register; Alternatively, an instruction might utilize only -Register deferred: address of an operand, and not the value of the The main memory address of the operand is con- operand; the address may be used alone, or as a tained in a general purpose CPU register; base address with offset for an in-memory data -Auto-decrement: 45 structure. Furthermore, of the thirteen operand The address of the operand is calculated by sub- specifier types listed above, eight involve a general tracting the size of the operand from an address purpose CPU register; in some systems, the pro- contained in a general purpose CPU register; gram counter can also be used in place of this -Auto-increment: general purpose register, increasing the number of The address of the operand in main memory is so different addressing modes from thirteen to twenty- contained in a general purpose CPU register. The one. Since an operand specified in one of these size of the operand is then added to the general twenty-one modes can be used in any of five controller purpose register; different ways, a microprogrammed sup- -Auto-increment deferred: porting all of the above addressing modes and An address contained in a general purpose CPU 55 operand usages must be able to process operands register is used to read from memory the address in (21 x 5) = 105 different ways. of the operand. A constant is then added to the With such a potentially large number of distinct general purpose register; ways to specify operands in a machine-level in-

5 9 EP 0 349 124 A2 10 struction, a dedicated routine approach to operand ware primitive must determine which of these three specifier processing would require an equally large usages is specified, and pass this information along number of individual routines for operand fetching, to the memory interface upon completion of resulting in a very large micro-store. Likewise, a operand specifier processing. In this way, simple general routine approach would require a micro- 5 decoding hardware in the memory interface is able routine with a large number of inefficient condi- to confirm and initiate the necessary access to the tional branch statements, resulting in extremely operand's location (either read, write or modify slow operand processing. The present invention access), once that location has been determined suggests a novel solution to this problem wherein by the microprogram routine. similar operand specifications are grouped together 10 The novel features believed characteristic of and processed by a microprogram routine dedi- the invention are set forth in the appended claims. cated to that group. By taking advantage of The invention itself, however, as well as other fea- similarities among certain modes and usages, the tures and advantages thereof, will be best under- number of dedicated routines can be minimized, stood by reference to the detailed description of a and the amount of conditional branch statements in is specific embodiment, when read in - conjunction those routines can also be reduced. with the accompanying drawings wherein: The grouping of similar operand specifier types Figure 1 is a block diagram showing the described by this invention is made according to major functional units which comprise a central several criteria: the type of operand (either byte, processing unit of a preferred embodiment of the word, or longword), the level of indirection (either 20 invention. the operand is supplied, or the address of the Although the present invention can be applied operand is supplied, or the address of the address to any microprogrammed architecture which sup- of the operand is supplied), the registers involved ports a diverse collection of operand addressing (either none, or general purpose registers, or the modes, a preferred embodiment is realized by im- program counter), whether incrementing or de- 25 plementing the invention within a machine conform- crementing is required, and the displacement, if ing to the VAX architecture standard, as presently any. After a grouping of operand specifiers has sold by the assignee of this invention. been determined, microprogram routines corre- FIG. 1 shows a simplified block diagram of a sponding to each group are defined. As specified central processing unit (CPU) 10 of the preferred in the invention, each microprogram routine can 30 embodiment, which is comprised of a plurality of begin execution at one of two different entry points, functional units hereinafter described: allowing for efficient resolution of differences in - An Instruction Unit 12 performs the instruction usage. fetch subcycle of a machine-level instruction cycle; Although operand specifiers within a particular that is, a machine-level instruction is fetched from group are said to be similar, some differences will 35 main memory 13 (or a cache memory) based upon necessarily exist between any two, since each an address in a program counter (PC). In addition, operand specifier is, by assumption, different from the Instruction Unit 12, decodes the opcode field of any other. In order to avoid conditionally branching this machine-level instruction, and this decode de- within any of the dedicated microprogram routines, termines the type of operand specifier(s) used in the present invention calls for the provision of a 40 the machine-level instruction. The Instruction Unit small collection of hardware units which function to 12 initiates the execution of all microprogram rou- resolve differences among specifiers of a common tines by supplying the microprogram routine entry group. One of these hardware primitives is required address or dispatch address to the microprogram for all operand specifiers which involve adding a controller, in a manner described in detail below. displacement value to the contents of a CPU regis- 45 When one microprogram routine terminates, the ter. Since the displacement field in the machine- Instruction Unit 12 must dispatch the entry address level instruction formats can be of varying sizes, of the next microprogram routine to be executed. this primitive is responsible for sign-extending the - An Execution Unit 14 contains the functional displacement in the instruction to 32 bits, and pro- facilities to implement the instruction set of the viding this 32-bit quantity to the dedicated micro- 50 preferred embodiment. In particular, the Execution program routine. In this manner, the microprogram Unit 14 includes a collection of CPU registers, a routines can treat all displacement values as 32-bit program counter (PC) register, and an arithmetic quantities, regardless of their original size. A sec- and logic unit (ALU). These CPU registers, in the ond hardware primitive can be employed to deter- usual manner, include temporary data registers, mine the specified usage of an operand. Since 55 memory address registers, index registers, as may either read and write and read/write (modify) us- be required for executing the instruction set for the ages are grouped together at one of the entry CPU. points in each dedicated routine, this second hard- - A Memory Management Unit 16 contains logic

6 1 :P 0 349 124 A2 jsed to control access to main memory 13, mclud- - A 3-bit instruction Access lype bus carries ng instruction fetches as required by the Instruc- three control bits from the Instruction Unit 12 to the ion Unit. The memory management unit will gen- Execution Unit 14, indicating the necessary mem- erate read and write controls to be applied to the ory access type for the operand specifier currently jus interface unit which controls the system bus 1 5 5 being processed. This 3-bit access-type control is )y read and write controls and whatever acknowl- generated in the instruction unit 12 by decoding edge, ready, wait controls as may be needed, part of the machine-level instruction. iepending upon the specific system selected. - A 2-bit Instruction Data Length Bus 36 carries two A Micro-store 18 is a ROM or other memory control bits from the Instruction Unit 12 to the :ontaining the microprogram routines needed to to Execution Unit 14 indicating the length (byte, word, execute the instruction set of the system. A Micro- or longword) of the memory data for the operand sequencer 20 includes logic that determines the currently being accessed. Typically, a byte is 8-bit address of the next microword to be fetched and data, a word is 16-bit data, and a longword is 32-bit axecuted from the Micro-store 1 8. data. ■ An Internal Data Bus 22 provides a data path 15 - A 3-bit Access Type Bus 38 enables the Execu- connecting the various functional units 12, 14 and tion Unit 14 to forward to the Memory Management 1 6 and the bus interface unit. The Internal Data Unit 16 the three control bits defining memory 3us 22 carries both read and write memory data access type that were received from the Instruction and addresses between the above mentioned func- Unit 12 via lines 34, so that the memory manage- :ional units, and usually includes control lines as >o ment unit can generate the read or write controls, well. Operands fetched from memory 13 (or cache) bus access requests, or whatever is needed to Dased upon an address in a memory address reg- pass onto the bus interface to implement the de- ster in the execution unit 14, for example, are sired memory operation for the specified operands. transferred via bus 22 into the execution unit 14 to - A 2-bit Data Length Bus 40 similarly enables the the ALU input registers or busses or wherever 25 Execution Unit 14 to forward the two control bits specified by the microinstruction sequence. defining the data length from the Instruction Unit 1 2 • A Dispatch Bus 24 carries micro-store entry ad- to the Memory Management Unit 16 so the mem- dresses from the Instruction Unit 12 to the Micro- ory management unit and bus interface operate on sequencer 20. the desired data length to be fetched or written to • An Instruction Data Bus 26 provides a data path 30 memory 13 as specified by the machine-level in- From the Instruction Unit 12 to the Execution Unit struction. 14, for literal (immediate) data contained in the - The Bus Interface Unit 42 provides the interface machine-level instructions. If a literal operand ad- between the CPU 10 (particularly the bus 22 in- dressing mode is used in executing a given including data, address and control lines) and the struction, then data from the machine-level instruc- 35 external system bus 15 including address, data, tion itself is loaded to a data register in the execu- and control signal lines, going to main memory 13. tion unit 14 via lines 26. The instruction set of the preferred embodi- - A Microinstruction Bus 28 carries the current ment supports a number of operand addressing microinstruction to be executed from the Micro- modes; for example all of the thirteen addressing store 18 to the Execution Unit 14, and to the 40 modes previously described and recited here may Memory Management Unit 16. The individual con- be implemented: ductor lines comprising the Microinstruction Bus 28 Literal Mode are divided into two groups 28a, 28b. The low- Index Mode order bit lines 28a provide a path for next-microin- Register Mode struction address information passed from the 45 Register Deferred Mode Micro-store 18 to the Microsequencer 20. The high- Auto-decrement Mode order bit lines 28b enable microprogram control Auto-Increment Mode bits to be delivered to the Execution Unit 14. Typi- Auto Increment Deferred Mode cally, a microinstruction may be comprised of fifty Byte Displacement Mode bits, for example, where sixteen bits are the ad- so Byte Displacement Deferred Mode dress of the next microinstruction transferred on Word Displacement Mode lines 28a, and the remaining thirty-four bits are Word Displacement Deferred Mode applied to the execution unit (or memory manage- Longword Displacement Mode ment unit) via lines 28b. Longword Displacement Deferred Mode - A Microaddress Bus 30 is a 16-bit bus for trans- 55 In addition, the usage of operands specified in one ferring micro-store addresses from the Micro- of these modes can be specified to be one of five sequencer 20 to the address input of the Micro- different types (these are the "access types" as store 18. defined by the three control bits on the lines 36

7 13 EP 0 349 124 A2 14 and 38): the microinstruction and from the control bits 34, Read Usage 36 as in 1 ) to specify the memory access required. Modify Usage That is, the address generated by the ADD may be Write Usage read from, written to, or both read and written Address Usage 5 (modify). Bit Held Base Address Usage 4) Index type: address or bit field usage.. Furthermore, eight of the above addressing modes This will use the same microinstructions as 3), but involve the use of a general purpose data or ad- with no read, write or modify of data in main dress register in the execution unit 14 (the CPU) memory 13. for which the Program Counter or PC Register in 10 5) Register type; read, modify or write us- the CPU may be substituted. Substituting the Pro- age. An operand will be one of the general purpose gram Counter Register for a general purpose regis- registers in the register file of the CPU, so the ter in these eight modes results in eight addressing microinstructions for this generic type will merely modes which are distinct from the thirteen listed access a field of the machine-level instruction via above. This implies a total of twenty-one possible is lines 26 to use as an address to pick out the different ways to specify an operand, each of which register of the CPU, along with memory control bits can be used in one of five different ways, yielding as in 1). (21 x 5) = 105 distinct combinations of addressing 6) Register type; address or bit field usage. mode and usage specification. This will have the same microinstructions as 3), but According to the method specified by the 20 with the memory controls as in 2). present invention, the 105 combinations are 7) Register deferred type; read, write or grouped according to similarities in mode and us- modify usage. The address of an operand is in one age to provide a number of "generic" operand of the general purpose registers, so the microin- modes each of which has steps which are imple- structions for this generic type will access a field of mented by microinstruction states so that a number 25 the machine-level instruction via lines 26 to use as of specific operand modes can be produced by an address to select one of the registers of the slight modifications (not using microinstructions) CPU register file, then will send out the contents of implemented by the control bits 34 and 36. The the selected register via the bus 22 and bus inter- preferred embodiment designates these twenty-two face 16 to the memory 13, then also direct the groups as follows: 30 memory management unit to perform the memory 1) Literal type; read, modify or write usage. access type defined on the control bits 38. An operand from the instruction itself is loaded via 8) Register deferred type; address or bit lines 26 to a data register of the CPU; this may field usage. This will produce microinstructions, as involve only one or a very few microinstructions in 7) but with no memory read, write or modify. from microstore 18, i.e., "load input bus of CPU to 35 9) Auto-decrement type; read, modify, or register A", along with a microinstruction to mem- write usage. The microinstructions to implement ory management unit 16 to generate memory con- this type would transfer a field of the machine-level trols as defined by bits received via 36, 40 to direct instruction via bus 26 to an input of the ALU of the the result of the arithmetic or logic operation which CPU, direct a register of the CPU register file to the opcode field of the instruction will require. 40 the other input of the CPU, do a SUBTRACT op- 2) Literal type: address or bit field usage. eration in the ALU, then use the result as an This may be the same as 1) except the microin- operand address by sending it out on the address struction bits to define memory controls will be lines of bus 22. Memory controls would be gen- different, i.e., will not allow read or write to memory erated using the control bits 38 (and data size 13. 45 defined via lines 40). 3) Index type; read, modify or write usage. 1 0) Auto-decrement type; address or bit field The microinstructions to implement index address- usage. The microinstructions would be the same as ing will including accessing the machine level in- 9), but there would be no memory read, write or struction via lines 26 to get the address of the modify. general purpose register in the register file of the so 11) Auto-increment type with general pur- CPU acting as the index register, doing an ADD in pose register; read, write or modify usage. Microin- the ALU using the contents of this index register, structions here would be the same as for 9), but an along with the contents of a memory address regis- ADD would be done instead of a SUBTRACT. ter in the CPU register file, as the A and B inputs 12) Auto-increment type with general pur- to the ALU, then placing the results of the ADD in a 55 pose register; address or bit field usage. Microin- memory address register to send out to the mem- structions are same as 1) but with no memory ory 13 via bus 22 and interface 42, using controls read, write or modify; i.e., the address itself is used produced by memory management unit 16 from as an operand.

8 5 :P 0 349 124 A2

13) Auto-increment type with PC as the reg- groups listed above, ana turtner eacn micropro- ister; read, write or modify usage. Microinstructions gram routine is executed entirely as outputs from are same as for 11), but the PC instead of a the micro-store 18, beginning at the entry point general purpose register is used, as the second addresses or dispatches sent on lines 24 to the input of the ALU for the ADD operation. 5 sequencer or address generator 20 and proceeding 14) Auto-increment type with PC as the reg- with no conditional branches or the like in the ister; address or bit field usage. Same as 10) but sequence of microinstructions. These entry points using PC as the second ALU input as in 13). are in pairs; the first corresponds to operands 15) Auto-increment deferred type with gen- specified in that group's addressing mode which eral purpose register; read, modify or write usage. w are to be read, modified or written; the second Microinstructions will be the same as for 11), but entry point corresponds to instances when the ad- the contents of the location for which the address dress of the specified operand is to be used, or was generated at the ALU output is itself used as when the address of the operand is to be used as the address of the operand. a base address for an in-memory bit field. In this 16) Auto-increment deferred type with gen- is manner, twenty-two microprogram routine entry eral purpose register, address or bit field usage. points are defined for operand specifier processing, Same as 15), but the operand specified would not instead of one (as would be the case in a general be read, written or modified, but instead the ad- routine implementation) or 105 (as would be the dress of this operand itself would be used by the case in a fully dedicated routine implementation). opcode. 20 Operation of the processing unit 10 proceeds 17) Auto-increment deferred type with PC as as follows: The Instruction Unit 12 receives a the register; read, modify or write usage. Microin- machine-level instructions via the Internal Data Bus structions are the same as for 1 5), but use the PC 22 from the memory 13 to start an instruction as the second input to the ALU for the ADD opera- cycle. The Instruction Unit 12 is responsible for tion. 25 extracting from a machine-level instruction all en- 18) Auto-increment deferred type with PC as coded and decoded instruction stream information the register; address or bit field usage. Same as that is required during the execution of micro- 16), but no read, write or modify. routines which accomplish the requested operation. 19) Byte, word or longword displacement This information includes the opcode, registers type; read, modify or write usage. Microinstructions 30 specified, operand specifiers, operand use the 32-bit sign-extended input via bus 26 as usage/access type, operand data lengths, operand one input of the ALU and the contents of a general destinations, information about the next value of the purpose register are used as the other ALU input; Program Counter Register, and other control and the ALU performs an ADD, and the result is loaded status information. Operand access type and data to a memory address register of the CPU and used 35 length information is decoded from the opcode by as the address of the operand. Also, the controls the Instruction Unit 12 and provided to the Execu- for a memory access are generated, while the tion Unit 14 via the dedicated, 3-bit Instruction specific memory usage (read, write, or modify) is Access Type Bus 34 and 2-bit Instruction Data specified by the 3-bit controls, and the data length Length Bus 36, respectively. (byte, word or longword) specified by the 2-bit 40 The Execution Unit 14 forwards this access controls. type and data length information to the Memory 20) Byte, word or longword displacement Management Unit 16 via the Access Type Bus 38 type; address a bit field usage. Same as 19), but and Data Length Bus 40, respectively. The Memory no read, write a modify of the operand is done in Management Unit 16 uses this information as it memory 13. 45 initiates memory accesses to the required loca- 21) Byte, word or longword displacement tions. Specifically, a simple hardware primitive cir- deferred type; read, modify or write usage. Same cuit (i.e., a decoder) in the Memory Management as 19), but the contents of the address in memory Unit 16, quickly decodes the bits on the Access 13 generated is read from memory 13 and used as Type Bus 38 in order to determine if the specific the address of the operand. so access type to initiate at the memory location cor- 22) Byte, and a longword displacement de- responding to the currently requested memory ac- ferred type; address or bit "field usage. Same as cess, if a read, write or modify is to be done. As 21), but the operand thus defined is not read, noted above, these access types include read, written or modified, but instead the address itself is write, modify (also referred to as used. 55 "read/modify/write"), address (i.e., the address it- For this invention, a microprogram routine (a self is used with no read, write or modify), and bit sequence of one or more microinstructions) will be field. If the access type is "address or bit field" defined for each of the generic addressing mode then the execution unit itself implements the speci-

9 17 EP 0 349 124 A2 18 fied "access type" operation. The data size of this these operands can be read from main memory access is indicated on the Data Length Bus 40. under control of the Memory Management Unit 16 While the Instruction Unit 12 is classifying the and provided to the Execution Unit 14. The VAX operand specifier into one of the twenty-two groups Architecture Standard defines machine-level of addressing modes, the Instruction Unit 12 also 5 instructions which have up to six operands speci- decodes the access type bits in the machine-level fied. Only after all operand specifiers have been instruction for that operand. This information, in processed may another microprogram routine be conjunction with the operand specifier group clas- executed to initiate the execution of the requested sification determines which one of the twenty-two operation on the operands. microprogram routine entry points should be used w Upon completion of the execution of the opera- to initiate processing of the corresponding operand tion requested in a machine-level instruction, the specifier. This entry address is then passed from next machine-level instruction pointed to by the PC the Instruction Unit 12 to the Microsequencer 20 is fetched from main memory, and the entire pro- via Dispatch Bus 24. The Microsequencer 20 then cess above is repeated for this instruction. initiates microprogram execution at this point by is While this invention has been described with sending the entry address to the Micro-store 18 via reference to a specific embodiment, the description the Microaddress bus 30. As sequences of micro- is not meant to be construed in a limiting sense. words are read from the Micro-store 18 they are Various modifications of the disclosed embodiment, made available to the Execution Unit 14 and the as well as other embodiments of the invention, will memory management Unit 16 on the Microinstruc- 20 be apparent to persons skilled in the art upon tion Bus 28. The low-order sixteen bit lines 28a of reference to this description. It is therefore con- the Microinstruction Bus 28 are routed back to the templated that the appended claims will be con- Microsequencer 20 so that these bits of the strued to cover any such modifications or embodi- microinstruction can be used by the Microsequen- ments as fall within the true scope of the invention. cer 20 to determine the micro-store address of the 25 next microinstruction to be executed. The remaining high-order bit lines 28b of the Microinstruction Claims Bus 28 are routed to the Execution Unit 14, providing a path for the bits of the individual microinstruc- 1. A method of specifying operands for an tion that are used to control the activity in the 30 instruction executed in a microcoded CPU, where Execution Unit 14, e.g., reading or loading the said' operands may be of a plurality of different various registers, operating the ALU, I/O to the addressing modes, and a plurality of different data busses 26, 32 and the like, in the usual manner of lengths may be used with at least some of said a microcoded CPU. addressing modes, comprising the steps of: Literal or immediate data contained in 35 decoding an opcode part of said instruction to machine-level instructions, such as addressing generate a dispatch address for one of a set of mode displacement values, are forwarded by the microinstruction sequences, each one of said set Instruction Unit 12 to the Execution Unit 14 via the defining a generic operand addressing mode, Instruction Data Bus 26, so that they are available addressing a micro-store beginning at an entry to the Execution Unit 14 for the computation of 40 point determined by said dispatch address and operand addresses and operands. Displacement continuing to address said micro-store to produce values specified in machine-level instructions can. the selected microinstruction sequence, be 8-bit, 16-bit or 32-bit quantities. A hardware applying said microinstruction sequence to an ex- primitive circuit (i.e., decoder and logic circuit) re- ecution unit of the CPU to fetch or select operands siding in the Instruction Unit 12 is responsible for 45 according to the selected generic operand address- sign extending (if necessary) all displacements so ing mode, that they all become 32-bit quantities. In this way, and also decoding said instruction to generate con- 32-bit displacement values are passed from the trol bits separate from said dispatch address to Instruction Unit 1 2 to the Execution Unit 1 4 via the select a specific operand mode from a set of Instruction Data Bus 26, where all displacements so specific operand modes, and applying said control can be uniformly treated as 32-bit quantities re- bits to said execution unit separately from said gardless of their originally specified size. sequence of microinstructions. The execution of each machine-level instruc- 2. A method according to claim 1 wherein said tion requires the execution of several microprogram set of microinstruction sequences includes N routines. First, one of the twenty-two generic micro- 55 microinstruction sequences and said set of specific program operand specifier processing routines operating modes includes M specific operating must be executed for each of the operand specifi- modes, where N and M are greater than 2, where- ers in the machine level instruction word, so that by the number of said microinstruction sequences

10 9 P 0 349 124 A2 u i said set is much less than N times M. ing a plurality or registers ana ous ana memory 3. A method according to claim 1 wherein said addressing means responsive to said microinstruc- ipecific operand modes include addressing tions to fetch or select operands according to the iperands of different data lengths. selected generic operand addressing mode, 4. A method according to claim 1 wherein said 5 and also means for decoding said instruction to ipecific operand modes include memory control generate control bits separate from said dispatch unctions of read and write. address to select a specific addressing mode from 5. A method according to claim 1 wherein said a set of specific operand modes, leneric operand addressing modes include at least means for applying said control bits to said execu- ine displacement type generic addressing mode in o tion and addressing means separately from said vhich data of variable length is included along with microinstruction sequence, and means responsive aid instruction as a displacement and said dis- to said control bits to implement said selected jlacement is added to a value in a register in said specific addressing mode. ixecution unit. 12. Apparatus according to claim 11 wherein 6. A method according to claim 5 wherein said 5 said set of microinstruction sequences includes N ipecific operating modes include modes for at microinstruction sequences and said set of specific east two different data lengths for said displace- operating modes includes M specific operating nents. modes, where N and M are greater than 2, where- 7. A method according to claim 6 including the by the number of said microinstruction sequences step of sign-extending all displacements received >o is much less than N times M. rom the instruction to the maximum of said dif- 13. Apparatus according to claim 11 wherein erent data lengths. said specific operand modes include addressing 8. A method according to claim 1 wherein said operands of different data lengths. set of generic operand addressing modes includes 14. Apparatus according to claim 11 wherein it least one literal addressing mode, at least one ?5 said specific operand modes include memory con- ndex addressing mode, and at least one register trol functions of read and write. iddressing mode. 15. Apparatus according to claim 11 wherein 9. A method according to claim 8 wherein said said generic operand addressing modes include at set of generic operand addressing modes includes least one displacement type generic addressing wo of said literal addressing modes, one of said 30 mode in which data of variable length is included iteral addressing modes providing for reading or along with said instruction as a displacement and writing to an address in memory, and the other of said displacement is added to a value in a register said literal addressing modes providing for defining in said execution unit. said address without reading or writing it in mem- 16. Apparatus according to claim 15 wherein modes include modes for at Dry. 35 said specific operating 10. A method according to claim 9 wherein least two different data lengths for said displace- said set of specific operand addressing modes ments. ncludes a specific mode for reading and a specific 17. Apparatus according to claim 16 including mode for writing. means for sign-extending all displacements re- 11. Apparatus for specifying operands for an 40 ceived by said execution unit from the instruction instruction executed in a microcoded CPU, where to the maximum of said different data lengths. wherein said operands may have a plurality of different 18. Apparatus according to claim 11 addressing modes and a plurality of different data said set of generic operand addressing modes lengths, comprising: includes at least one literal addressing mode, at decoding means for decoding an opcode part of 45 least one index addressing mode, and at least one said instruction to generate a dispatch address for register addressing mode. one of a set of microinstruction sequences.each 19. Apparatus according to claim 18 wherein one of said set defining a generic operand ad- said set of generic operand addressing modes dressing mode, includes two of said literal addressing modes, one for read- a microstore having an address input and a so of said literal addressing modes providing microinstruction output, and addressing means for ing or writing to an address in memory, and the addressing said microstore beginning at an entry other of said literal addressing modes providing for it in point determined by said dispatch address re- defining said address without reading or writing ceived from said decoding means, said microstore memory. wherein producing at said microinstruction output the se- 55 20. Apparatus according to claim 19 lected microinstruction sequence determined by said set of specific operand addressing modes said entry point, includes a specific mode for reading and a specific execution and addressing means of the CPU hav- mode for writing.

n 21 EP 0 349 124 A2 22

21. A method of operating a microcoded CPU in a computer system, comprising the steps of: decoding an instruction to determine which one of a set of different generic operand addressing modes is specified by said instruction, 5 addressing a microstore to provide a selected sequence of microinstructions corresponding to said one of said set, also decoding said instruction to determine which one of another set of operand features is specified to by said instruction, and producing specific control bits to define said one of said another set, using said selected sequence of microinstructions and said specific control bits to- fetch or select operands to be processed by said instruction. rs 22. A method according to claim 21 wherein said set of different operand addressing modes includes at least one literal addressing mode where at least one operand is included with said instruction, and further includes at least one index ad- 20 dressing mode where the address of at least one operand is calculated from a base address and an index contained in a register of said CPU. 23. A method according to claim 22 wherein said set of different operand addressing modes 25 further includes at least one register addressing mode where at least one operand is contained in a register of said CPU. 24. A method according to claim 23 wherein said set of different operand addressing modes 30 further includes at least one register-deferred addressing mode where the address of an operand is contained in a register of the CPU. 25. A method according to claim 22 wherein said set of operand features includes a plurality of 35 different data lengths for an operand. 26. A method according to claim 25 wherein said data lengths include an eight-bit byte, a sixteen-bit word, and a thirty-two bit word. 27. A method according to claim 22 wherein 40 said set of operand features includes a plurality of different memory read/write controls including read, write and no read or write.

12 EP 0 349 124 A2

10 /

12 \

22 INSTRUCTION UNIT

14 \

EXECUTION UNIT

38 16 40 L

MEMORY MANAGEMENT 42 UNIT /

BUS INTERFACE UNIT ■71

13 MAIN MEMORY UNIT

FIG. 1