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Ece 685 Digital Computer Structure/Architecture ECE 685 DIGITAL COMPUTER STRUCTURE/ARCHITECTURE FALL SEMESTER, 2002 TEXT: J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach,3rd Edition, Morgan Kaufmann, 2003 Instructor: Heath SYLLABUS ECE 685-001 DIGITAL COMPUTER STRUCTURE/ARCHITECTURE COURSE SYLLABUS FALL, 2002 • Instructor: Dr. J. Robert (Bob) Heath • Office: 313 Electrical Engineering Annex • Office Phone Number: (859) 257-3124 • Email: [email protected] • Web Page: http://www.engr.uky.edu/~heath • Office Hours: M (3:30 pm-5:00 pm) W (2:30 pm-4:00 pm) • Text: J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Third Edition, Morgan Kaufmann, 2003. • References: H.S. Stone, High Performance Computer Architecture, Addison Wesley, 1990. C. Hamacher, Z. Vranesic, and S. Zaky, Computer Organization, Fifth Edition, McGraw Hill, 2002. S.G. Shiva, Computer Design & Architecture, Second Edition, Harper Collins, 1991. D.A.Patterson and J.L.Hennessy, Computer Organization and Design: The Hardware/Software Interface, Second Edition, Morgan Kaufmann, San Mateo, CA 1998. Heath 2 SYLLABUS (continued) • W.Stallings, Computer Organization and Architecture: Designing for Performance, Fourth Edition, Prentice Hall, 1996. • S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall, 1996. • M. Ciletti, Modeling, Synthesis, And Rapid Prototyping With The Verilog HDL, Prentice Hall, 1999 (Available for purchase in local bookstores). • Meeting Schedule MWF (10:00 am-10:50 am) 303 Slone Research Bldg. • Course Description Study of fundamental concepts in digital computer system architecture/structure and design. Topics include: computer system modeling based on instruction set architecture models; architecture and design of datapaths, control units, processors, memory systems hierarchy, and input/output systems. Special topics include floating-point arithmetic, multiple level cache design, pipeline design techniques, multiple issue processors, and an introduction to parallel computer architectures. Use of Hardware Description Languages (HDLs) for architecture/design verification/validation via pre- synthesis simulation. Prereq: EE380 and EE581 or consent of instructor. Heath 3 SYLLABUS (Continued) • Topical Outline 1. Introduction to Computer Architecture and Design Fundamentals. 2. Instruction Set Architecture Models. 3. Introduction to Computer Architecture/Design Verification via use of a Hardware Description Language (HDL) – VERILOG. 4. Instruction Set Principles and Examples. 5. Pipelining. 6. Advanced Pipelining and Instruction-Level Parallelism. 7. Memory Hierarchy Design. 8. Storage Systems. 9. Input/Output Systems. 10. Computer Design & Design Documentation and Verification via VERILOG. 11. Interconnection Networks. 12. Introduction to Multiprocessors and Models. 13. Introduction to Vector Processors. • Grade: Test 1: (October 11) 25% Test 2: (November 25) 25% Homework: Design, Design Verification Projects: 25% Final Exam -Comprehensive (Fri. Dec. 20 (10:30 am)): 25% Your final grade will generally be determined by the number of points you have accumulated from 100 possible points as follows: A: 90-100 pts. B: 80-89 pts. C: 70-79 pts. E: 69 or below An equitable grade scale will be applied when warranted. Heath 4 SYLLABUS (Continued) • Make-Up Examinations Make-up examinations will only be given to students who miss examinations as a result of excused absences according to applicable university policy. Make-up exams may be of a different format from the regular exam format (Example: Oral format). • Cheating: Cheating will not be allowed or tolerated. Anyone who cheats will be dealt with according to applicable university policy. (Assignment of a grade of E for the course). • Class Attendance Attendance of all class lectures is required to assure maximum course performance. You are responsible for all business conducted within a class. • Homework Assignments Homework assignments will be periodically made. All assignments may not be graded. Assignments are due at the beginning of the class period on due dates. Heath 5 VERILOG • A Hardware Description Language (HDL) Used To Describe Digital Systems Hardware Design and Structure. • A HDL Can Be Used For Digital System Design Verification/Validation and ImplementationVia HDL Simulation, Synthesis, And Implementation. • Systems May Be Described At Three Levels: Behavioral, Register Transfer (Dataflow, Equation), And Gate (Structural) Levels. • Example: • Binary Full Adder Heath 6 Verilog Coding Example: Binary Full Adder (bfa) Gate (Structural) Level Coding Style module fulladd1 (I2, I1, I0, so, co); // Module Name and Input/Output Signal //Declaration input I2, I1, I0 ; // Input, Output, and Wire Declaration output so; output co; wire wx0, wa0, wa1, wa2; xor XO (wx0, I2, I1); // Gate Identification, Instantiation Names, an Output/Input(s) xor X1 (so, wx0, I0); and A0 (wa0, I1, I0); and A1 (wa1, I2, I1); and A2 (wa2, I2, I0); or (co, wa0, wa1, wa2); endmodule // End of Module // “and AI #2(wf,wc,wd)” Gate Delay Of 2 Simulation Time Units. Heath 7 Verilog Coding Example: Binary Full Adder (bfa) Register-Transfer-Level (RTL), Dataflow, Or Equation Level Coding Style // "bfa" RTL Coding Style. module fulladd2 (I2, I1, I0, so, co); // Module Name and Input/Output Signal Declaration. input I2, I1, I0 ; // Input, Output, and Wire Declaration. output so; output co; assign so = I2 ^ I1 ^ I0; // Equations of Binary Full Adder (bfa). Bit Wise Exclusive-OR (^). assign co = (I2 && I0) || (I1 && I0) || (I2 && I1); //Logical AND (&&); Logical OR (||). //Bit Wise AND (&); Bit Wise OR (|). endmodule // End of Module. Heath 8 Verilog Coding Example: Binary Full Adder (bfa) Behavioral Level Coding Style // "bfa" Behavioral Coding Style. module fulladd3 (I2, I1, I0, so, co); // Module Name and Input/Output Signal Declaration. input I2, I1, I0 ; // Input and Output Declaration. output co, so; reg co, so; // Port (Signal) Values Are Held Until They Change. always @ (I2 or I1 or I0) //Following Code Executed Anytime I2, I1 or I0 Changes begin //Value. case ({I2,I1,I0}) //Use Behavioral Level "Case" Structure. 3'b000: begin co=1’b0; so=1’b0; end //Implements Truth Table.. 3'b001: begin co=1’b0; so=1’b1; end 3'b010: begin co=1’b0; so=1’b1; end //3'b010 Implies 3-Bits Binary And They are //010. 3'b011: begin co=1’b1; so=1’b0; end 3'b100: begin co=1’b0; so=1’b1; end 3'b101: begin co=1’b1; so=1’b0; end 3'b110: begin co=1’b1; so=1’b0; end 3'b111: begin co=1’b1; so=1’b1; end endcase end endmodule Heath 9 AUTOMATED TESTBENCH FOR “fulladd1” MODULE module testfulladd1; reg I2, I1, I0, Cot, Sot, flag; // Signals Declared to be Registers (Hold Values Until Changed) wire Sos,Cos; fulladd1 ADD0(I2, I1, I0, Sos, Cos); // Instantation of Module Under Test (MUT) initial // This Process Defines Signals We Want to View as begin // System is Simulated and the Code We Represent // Signals in. Choices are Binary, Octal, or Hex $monitor($time, "I2=%b I1=%b I0=%b Cos=%b Cot=%b Sos=%b Sot=%b flag=%b", I2,I1,I0,Cos,Cot,Sos,Sot,flag); end initial // This Process Generates Stimulus Inputs to MUT begin: I2_loop // and for Each a Theoretically Correct Output integer m; for (m = 0 ; m < 2; m=m+1) begin: I1_loop integer n; for (n = 0 ; n < 2; n=n+1) begin: I0_loop integer o; for (o = 0 ; o <2; o=o+1) begin #1 I2 = m; I1 = n; I0 = o; // Stimulus Applied to MUT Inputs Heath 10 AUTOMATED TESTBENCH FOR “fulladd1” MODULE (Continued) if(m == 0 && n == 0 && o == 0) Cot = 0; // Generation of if(m == 0 && n == 0 && o == 0) Sot = 0; //Theoretically if(m == 0 && n == 0 && o == 1) Cot = 0; //Correct Outputs if(m == 0 && n == 0 && o == 1) Sot = 1; if(m == 0 && n == 1 && o == 0) Cot = 0; if(m == 0 && n == 1 && o == 0) Sot = 1; if(m == 0 && n == 1 && o == 1) Cot = 1; if(m == 0 && n == 1 && o == 1) Sot = 0; if(m == 1 && n == 0 && o == 0) Cot = 0; if(m == 1 && n == 0 && o == 0) Sot = 1; if(m == 1 && n == 0 && o == 1) Cot = 1; if(m == 1 && n == 0 && o == 1) Sot = 0; if(m == 1 && n == 1 && o == 0) Cot = 1; if(m == 1 && n == 1 && o == 0) Sot = 0; if(m == 1 && n == 1 && o == 1) Cot = 1; if(m == 1 && n == 1 && o == 1) Sot = 1; #1 if((Cos==Cot)&&(Sos==Sot)) flag = 0; // Comparison of Theoretically else flag = 1; // Correct Output to MUT Output. end // “==“ Logical Equality end end #5 flag = 1; end initial // Process Which Will Shut Down a Run-Away Simulation begin // ie, Getting in an Endless Loop. #150 $finish; end endmodule Heath 11 SIMUCAD SILOS III DEMONSTRATIONS (Use Files “bfa_gate_level” And “testbfa_gate_level”) (Use Files “mux4x1_gate_level” And “testmux4x1_gate_level”) • Examples Of “Exhaustive Automated” Testbenches Heath 12 CHAP. 1 –Fundamentals of Computer Design • Electronic Computing Originated in 1945. • Performance Growth 1945 ? % Per Year Technology and Architectural Innovation. 1970 25% – 35% Per Year Technology Only. 1980 50% Per Year *RISC – Technology and Arch. Innovation (Inst. Level Parallelism (ILP) and Cache Memories. * (Microprocessor Driven) Fewer: Mainframes Supercomputers 1995 50% Per Year *Technology and Architectural Innovation. (Super Scalar Pipelining, ILP, and Parallel Processing) *Application Classes: PCs, Servers, Embedded Computers. 2002 Heath 13 Growth In Microprocessor Performance Due to Technology and Architectural Innovation 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 Heath 14 TASK OF A COMPUTER DESIGNER (ARCHITECT) 1. Determine Important Requirements/Attributes of a New Computer to be Developed. 2. Design to Meet Requirements/Attributes and to Maximize Performance (When Required) and Lower Cost. • Design Steps: 1. Assembly Language Instruction Set Design. 2. Functional Organization (1. and 2. Comprise ISA Design). 3. Logic Design of Functional Units to RTL and Gate Level only when Required. 4. Design Capture (Verilog or VHDL). 5. Organization/Architecture/Design Verification/Validation via HDL Simulation. 6. Implementation. * IC Design, Layout, etc. * Power * Cooling * Low Power Design * Testing • Computer Architecture: Includes: 1. Instruction Set Architecture Design.
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