Important Μps at a Glance Athlon 64 "Winchester" (D0, 90 Nm) Model

Total Page:16

File Type:pdf, Size:1020Kb

Important Μps at a Glance Athlon 64 Important µPs at a glance AMD Athlon 64 "Winchester" (D0, 90 nm) L2- Model Freque Mult VCo TD Socke Release Part Cach HT Number ncy i 1 re P t Date Number(s) e Athlon 64 1800 512 1000 1.40 67 Socket October ADA3000DIK 9x 3000+ MHz KB MHz V W 939 14, 2004 4BI Athlon 64 2000 512 1000 1.40 67 Socket October ADA3200DIK 10x 3200+ MHz KB MHz V W 939 14, 2004 4BI Athlon 64 2200 512 1000 1.40 67 Socket October ADA3500DIK 11x 3500+ MHz KB MHz V W 939 14, 2004 4BI "Manchester" (E4, 90 nm) L2- Model Freque Mult VCo TD Socke Release Part Cach HT Number ncy i 1 re P t Date Number(s) e Athlon 64 2000 512 1000 1.35 67 Socket May 31, ADA3200DKA 10x 3200+ MHz KB MHz V W 939 2005 4CG Page | 132 Important µPs at a glance Athlon 64 2200 512 1000 1.35 67 Socket May 31, ADA3500DKA 11x 3500+ MHz KB MHz V W 939 2005 4CG "San Diego" (E4, 90 nm) L2- Model Freque Mul TD Socke Releas Part Cach HT VCore Number ncy ti 1 P t e Date Number(s) e Athlon 2200 512 1000 1.35/1.4 67 Socket May 4, ADA3500DAA 64 11x MHz KB MHz 0 V W 939 2005 4BN 3500+ Athlon 2200 1024 1000 1.35/1.4 89 Socket May 4, ADA3700DAA 64 11x MHz KB MHz 0 V W 939 2005 5BN 3700+ Athlon 2400 1024 1000 1.35/1.4 89 Socket May 4, ADA4000DAA 64 12x MHz KB MHz 0 V W 939 2005 5BN 4000+ "Toledo" (E6, 90 nm) L2- Model Freque Mult VCo TD Socke Release Part Cach HT Number ncy i 1 re P t Date Number(s) e Page | 132 Important µPs at a glance Athlon 64 2200 1024 1000 1.35 89 Socket ADA3700DKA 11x 3700+ MHz KB MHz V W 939 5CF Athlon 64 2400 1024 1000 1.35 89 Socket ADA4000DKA 12x 4000+ MHz KB MHz V W 939 5CF Page | 133 Important µPs at a glance "Orleans" (Energy Efficient 45W, F3, 90 nm) L2- Model Freque Mul TD Socke Release Part Cach HT VCore Number ncy ti 1 P t Date Number(s) e Athlon 64 2200 1024 1000 1.25/1.4 45 Socket October ADH1600IAA 11x LE-1600 MHz KB MHz 0 V W AM2 8, 2007 5DH Athlon 64 2400 1024 1000 1.25/1.4 45 Socket October ADH1620IAA 12x LE-1620 MHz KB MHz 0 V W AM2 8, 2007 5DH Athlon 64 2600 1024 1000 1.25/1.4 45 Socket January ADH1640IAA 13x LE-1640 MHz KB MHz 0 V W AM2 7, 2008 5DH "Orleans" (Energy Efficient Small Form Factor, F2, 90 nm) L2- Model Freque Mul TD Socke Releas Part Cach HT VCore Number ncy ti 1 P t e Date Number(s) e Athlon 64 2200 512 1000 1.20/1.2 35 Socket May 23, ADD3500IAA 11x 3500+ MHz KB MHz 5 V W AM2 2006 4CN Athlon 64 FX Page | 132 Important µPs at a glance "SledgeHammer" (C0 & CG, 130 nm) L2- Model Freque Mul VCo TD Socke Release Part Cach HT Number ncy ti 1 re P t Date Number(s) e Athlon 64 2200 1024 800 1.50 89 Socket September ADAFX51CEP 11x FX-51 (C0) MHz KB MHz V W 940 23, 2003 5AK Athlon 64 2200 1024 800 1.50 89 Socket September ADAFX51CEP 11x FX-51 (CG) MHz KB MHz V W 940 23, 2003 5AT Athlon 64 2400 1024 800 1.50 89 Socket March 18, ADAFX53CEP 12x FX-53 (CG) MHz KB MHz V W 940 2004 5AT "ClawHammer" (CG, 130 nm) L2- Model Freque Mul VCo TD Socke Release Part Cach HT Number ncy ti 1 re P t Date Number(s) e Athlon 64 2400 1024 1000 1.50 89 Socket June 1, ADAFX53DEP 12x FX-53 MHz KB MHz V W 939 2004 5AS Athlon 64 2600 1024 1000 1.50 104 Socket ~ October ADAFX55DEI 13x FX-55 MHz KB MHz V W 939 10, 2004 5AS "San Diego" (E4, 90 nm) Page | 132 Important µPs at a glance L2- Model Freque Mul TD Socke Releas Part Cach HT VCore Number ncy ti 1 P t e Date Number(s) e Athlon 64 2600 1024 1000 1.35- 104 Socket ADAFX55DAA 13x FX-55 MHz KB MHz 1.40 V W 939 5BN Athlon 64 2800 1024 1000 1.35- 104 Socket June 27, ADAFX57DAA 14x FX-57 MHz KB MHz 1.40 V W 939 2005 5BN Dual-Core Desktop Processors Athlon 64 X2 "Manchester" (E4, 90 nm) L2- Model Freque Mul VCor Sock Releas Cach HT TDP Part Number(s) Number ncy ti 1 e et e Date e Athlon 2 x 1.30- 89- 2000 1000 Socke 64 X2 256 10x 1.35 110 ADA3600DAA4BV MHz MHz t 939 3600+ KB V W Athlon 2 x 1.30- 2000 1000 89 Socke August 64 X2 512 10x 1.35 ADA3800DAA5BV MHz MHz W t 939 1, 2005 3800+ KB V Athlon 2200 2 x 1000 11x 1.30- 89 Socke May ADA4200DAA5BV 64 X2 512 1.35 31, or Page | 132 Important µPs at a glance 4200+ MHz KB MHz V W t 939 2005 ADA4200BVBOX Athlon 2 x 1.30- May 2400 1000 110 Socke 64 X2 512 12x 1.35 31, ADA4600DAA5BV MHz MHz W t 939 4600+ KB V 2005 "Windsor" (Energy Efficient Small Form Factor, F2, 90 nm) L2- Model Freque Mul TD Socke Releas Part Cach HT VCore Number ncy ti 1 P t e Date Number(s) e ADD3800IAA Athlon 64 2 x May 2000 1000 1.025/1.0 35 Socket 5CU X2 512 10x 23, MHz MHz 75 V W AM2 ADD3800IAT 3800+ KB 2006 5CU Athlon X2 Athlon 64 FX "Toledo" (E6, 90 nm) Model Freque L2- Mul TD Socke Release Part HT VCore Number ncy Cache ti 1 P t Date Number(s) Athlon 2600 2 x 1000 13x 1.35- 110 Socket January ADAFX60DAA Page | 132 Important µPs at a glance 1024 64 FX-60 MHz MHz 1.40 V W 939 9, 2006 6CD KB "Windsor" (F2, 90 nm) Model Freque L2- Mul Socke Releas Part HT VCore TDP Number ncy Cache ti 1 t e Date Number(s) 2 x Athlon 2800 1000 1.35 / 125 Socket May 23, ADAFX62IAA 1024 14x 64 FX-62 MHz MHz 1.40 V W AM2 2006 6CS KB Athlon Neo "Huron" (65 nm, 15W TDP) L2- Model Freque Mul VCo TD Packa Releas Cach HT Part Number(s) Number ncy ti 1 re P ge e Date e Athlon 1600 512 1600 1.1 15 January AMGMV40OAX4D Neo MV- 8x ASB1 MHz KB MHz V W 9, 2009 X (Tray) 40 Intel Page | 132 Important µPs at a glance Process Year of Peak Clock Address Data bus Address or Manufactu power bus able re Memory 4004 November 740 4 bits multiplexed 640 bytes 15, 1971 kHz address/data 8008 April 1, 500 8 bits multiplexed 16 KB 1972 kHz address/data 8080 April 1, 2 MHz 16 bits 8 bits 64 KB 1974 8085 March 1976 5 MHz 16 bits 8 bits 8086 June 8, 1978 5-10 20 bits 16 bits 1 MB MHz 8088 June 1, 1979 4.77-9 20 bits 8 bits 1 MB MHz external, 16 bits internal 80286 February 1, 6-25 16 bits 16 bits 16 MB 1982 MHz October 17, 16-33 32 bits 32 bits 4 GB 80386DX 1985 MHz June 16, 16-33 24 bits 16 bits 16 MB 80386SX 1988 MHz 1994 60-66 32 bits 4GB Pentium I MHz 1997 300- Pentium 500 II MHz 1999 450- Pentium 600 III MHz 2000 Pentium IV May 29, 733- Itanium 2001 800 MHz 2004 1.86- Xeon 2.8 GHz 2007 1.60- Dual 2.7 Page | 133 Important µPs at a glance Page | 134 Important µPs at a glance Hewlett- Packard CPU Used in calculator models Properties codename Saturn HP-71B, HP-18C, HP-28C 640 kHz 640 kHz, 10 KB ROM, 256 Bytes RAM, LCD Bert HP-10B, HP-20S, HP-21S driver HP-14B, HP-22S, HP-32S, HP- 640 kHz, 16 KB ROM, 512 Bytes RAM, LCD Sacajawea 32SII driver HP-17B, HP-19B, HP-27S, HP- 1 MHz, 64 KB ROM, LCD driver, memory Lewis 28S, HP-42S controller, IR control 2 MHz, LCD controller, memory controller, Clarke HP-48SX, HP-48S UART and IR control HP-48GX, HP-48G, HP-38G, 3.68 MHz, LCD controller, memory Yorke HP-39G, HP-49G controller, UART and IR control Page | 132 Important µPs at a glance IBM • IBM 801 — Pioneering prototype RISC processor; 1980 • IBM ROMP — RISC processor, also known as 032 processor • IBM POWER — Commercial RISC processor range ○ POWER1 ○ POWER2 ○ POWER3 ○ POWER4 ○ POWER5 ○ POWER6 ○ POWER7 in development • PowerPC — Partly based on POWER ○ PPC 601 ○ PPC 603 ○ PPC 604 ○ PPC 620 ○ PPC 7xx ○ PPC 4xx embedded CPUs ○ IBM RS64 ○ PPC 970 ○ Cell microprocessor ○ Gekko, Broadway and Xenon CPUs for game consoles. Page | 133 Important µPs at a glance Motorola 68020: • 32-bit address & ALU. • 3 stage pipeline. • Instruction cache of 256 bytes. • Unrestricted word and longword data access (see alignment). • 8 x multiprocessing capability. • Larger multiply (32×32 -> 64 bits) and divide (64÷32 -> 32 bits quotient and 32 bits remainder) instructions, and bit field manipulations. • Addressing modes added scaled indexing and another level of indirection.
Recommended publications
  • Wind Rose Data Comes in the Form >200,000 Wind Rose Images
    Making Wind Speed and Direction Maps Rich Stromberg Alaska Energy Authority [email protected]/907-771-3053 6/30/2011 Wind Direction Maps 1 Wind rose data comes in the form of >200,000 wind rose images across Alaska 6/30/2011 Wind Direction Maps 2 Wind rose data is quantified in very large Excel™ spreadsheets for each region of the state • Fields: X Y X_1 Y_1 FILE FREQ1 FREQ2 FREQ3 FREQ4 FREQ5 FREQ6 FREQ7 FREQ8 FREQ9 FREQ10 FREQ11 FREQ12 FREQ13 FREQ14 FREQ15 FREQ16 SPEED1 SPEED2 SPEED3 SPEED4 SPEED5 SPEED6 SPEED7 SPEED8 SPEED9 SPEED10 SPEED11 SPEED12 SPEED13 SPEED14 SPEED15 SPEED16 POWER1 POWER2 POWER3 POWER4 POWER5 POWER6 POWER7 POWER8 POWER9 POWER10 POWER11 POWER12 POWER13 POWER14 POWER15 POWER16 WEIBC1 WEIBC2 WEIBC3 WEIBC4 WEIBC5 WEIBC6 WEIBC7 WEIBC8 WEIBC9 WEIBC10 WEIBC11 WEIBC12 WEIBC13 WEIBC14 WEIBC15 WEIBC16 WEIBK1 WEIBK2 WEIBK3 WEIBK4 WEIBK5 WEIBK6 WEIBK7 WEIBK8 WEIBK9 WEIBK10 WEIBK11 WEIBK12 WEIBK13 WEIBK14 WEIBK15 WEIBK16 6/30/2011 Wind Direction Maps 3 Data set is thinned down to wind power density • Fields: X Y • POWER1 POWER2 POWER3 POWER4 POWER5 POWER6 POWER7 POWER8 POWER9 POWER10 POWER11 POWER12 POWER13 POWER14 POWER15 POWER16 • Power1 is the wind power density coming from the north (0 degrees). Power 2 is wind power from 22.5 deg.,…Power 9 is south (180 deg.), etc… 6/30/2011 Wind Direction Maps 4 Spreadsheet calculations X Y POWER1 POWER2 POWER3 POWER4 POWER5 POWER6 POWER7 POWER8 POWER9 POWER10 POWER11 POWER12 POWER13 POWER14 POWER15 POWER16 Max Wind Dir Prim 2nd Wind Dir Sec -132.7365 54.4833 0.643 0.767 1.911 4.083
    [Show full text]
  • March 11, 2010 Presentation
    IBM Power Systems POWER7TM Announcement, The Next Generation of Power Systems Power your planet. February 25, 2010 IBM Power Systems 2 February 25, 2010 IBM Power Systems POWER7 System Highlights .Balance System Design - Cache, Memory, and IO .POWER7 Processor Technology - 6th Implementation of multi-core design - On chip L2 & L3 caches .POWER7 System Architecture - Blades to High End offerings - Enhances memory implementation - PCIe, SAS / SATA .Built in Virtualization - Memory Expansion - VM Control .Green Technologies - Processor Nap & Sleep Mode - Memory Power Down support - Aggressive Power Save / Capping Modes 600 500 .Availability 400 - Processor Instruction Retry 300 - Alternate Process Recovery 200 100 - Concurrent Add & Services 0 JS23 JS43 520 550 560 570/16 570/32 595 3 February 25, 2010 IBM Power Systems 4 February 25, 2010 IBM Power Systems Power Processor Technology IBM investment in the Power Franchise Dependable Execution for a decade POWER8 POWER7 45 nm Globalization and globally POWER6 available resources 65 nm •Performance/System Capacity POWER5 •4-5X increase from Power6 130 nm •Multi Core – Up to 8 POWER4 •SMT4 – 4 threads/core 180 nm . Dual Core •On-Chip eDRAM . High Frequencies • Energy . Dual Core . Virtualization + . Enhanced Scaling • Efficiency: 3-4X Power6 . Memory Subsystem + . SMT • Dynamic Energy . Dual Core . Altivec . Distributed Switch + Management . Chip Multi Processing . Instruction Retry . Distributed Switch . Core Parallelism + • Reliability + . Dyn Energy Mgmt . Shared L2 . FP Performance + . SMT + •Memory DIMM – DRAM . Dynamic LPARs (32) . Memory bandwidth + . Protection Keys Sparing . Virtualization •N+2 Voltage Regulator Redundancy •Protection Keys + 5 February 25, 2010 IBM Power Systems POWER6 – POWER7 Compare Wireless world Mobile platforms are developing as new means of identification.
    [Show full text]
  • Copyrighted Material
    CHAPTER 1 MULTI- AND MANY-CORES, ARCHITECTURAL OVERVIEW FOR PROGRAMMERS Lasse Natvig, Alexandru Iordan, Mujahed Eleyat, Magnus Jahre and Jorn Amundsen 1.1 INTRODUCTION 1.1.1 Fundamental Techniques Parallelism hasCOPYRIGHTED been used since the early days of computing MATERIAL to enhance performance. From the first computers to the most modern sequential processors (also called uni- processors), the main concepts introduced by von Neumann [20] are still in use. How- ever, the ever-increasing demand for computing performance has pushed computer architects toward implementing different techniques of parallelism. The von Neu- mann architecture was initially a sequential machine operating on scalar data with bit-serial operations [20]. Word-parallel operations were made possible by using more complex logic that could perform binary operations in parallel on all the bits in a computer word, and it was just the start of an adventure of innovations in parallel computer architectures. Programming Multicore and Many-core Computing Systems, 3 First Edition. Edited by Sabri Pllana and Fatos Xhafa. © 2017 John Wiley & Sons, Inc. Published 2017 by John Wiley & Sons, Inc. 4 MULTI- AND MANY-CORES, ARCHITECTURAL OVERVIEW FOR PROGRAMMERS Prefetching is a 'look-ahead technique' that was introduced quite early and is a way of parallelism that is used at several levels and in different components of a computer today. Both data and instructions are very often accessed sequentially. Therefore, when accessing an element (instruction or data) at address k, an auto- matic access to address k+1 will bring the element to where it is needed before it is accessed and thus eliminates or reduces waiting time.
    [Show full text]
  • Power4 Focuses on Memory Bandwidth IBM Confronts IA-64, Says ISA Not Important
    VOLUME 13, NUMBER 13 OCTOBER 6,1999 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Power4 Focuses on Memory Bandwidth IBM Confronts IA-64, Says ISA Not Important by Keith Diefendorff company has decided to make a last-gasp effort to retain control of its high-end server silicon by throwing its consid- Not content to wrap sheet metal around erable financial and technical weight behind Power4. Intel microprocessors for its future server After investing this much effort in Power4, if IBM fails business, IBM is developing a processor it to deliver a server processor with compelling advantages hopes will fend off the IA-64 juggernaut. Speaking at this over the best IA-64 processors, it will be left with little alter- week’s Microprocessor Forum, chief architect Jim Kahle de- native but to capitulate. If Power4 fails, it will also be a clear scribed IBM’s monster 170-million-transistor Power4 chip, indication to Sun, Compaq, and others that are bucking which boasts two 64-bit 1-GHz five-issue superscalar cores, a IA-64, that the days of proprietary CPUs are numbered. But triple-level cache hierarchy, a 10-GByte/s main-memory IBM intends to resist mightily, and, based on what the com- interface, and a 45-GByte/s multiprocessor interface, as pany has disclosed about Power4 so far, it may just succeed. Figure 1 shows. Kahle said that IBM will see first silicon on Power4 in 1Q00, and systems will begin shipping in 2H01. Looking for Parallelism in All the Right Places With Power4, IBM is targeting the high-reliability servers No Holds Barred that will power future e-businesses.
    [Show full text]
  • POWER® Processor-Based Systems
    IBM® Power® Systems RAS Introduction to IBM® Power® Reliability, Availability, and Serviceability for POWER9® processor-based systems using IBM PowerVM™ With Updates covering the latest 4+ Socket Power10 processor-based systems IBM Systems Group Daniel Henderson, Irving Baysah Trademarks, Copyrights, Notices and Acknowledgements Trademarks IBM, the IBM logo, and ibm.com are trademarks or registered trademarks of International Business Machines Corporation in the United States, other countries, or both. These and other IBM trademarked terms are marked on their first occurrence in this information with the appropriate symbol (® or ™), indicating US registered or common law trademarks owned by IBM at the time this information was published. Such trademarks may also be registered or common law trademarks in other countries. A current list of IBM trademarks is available on the Web at http://www.ibm.com/legal/copytrade.shtml The following terms are trademarks of the International Business Machines Corporation in the United States, other countries, or both: Active AIX® POWER® POWER Power Power Systems Memory™ Hypervisor™ Systems™ Software™ Power® POWER POWER7 POWER8™ POWER® PowerLinux™ 7® +™ POWER® PowerHA® POWER6 ® PowerVM System System PowerVC™ POWER Power Architecture™ ® x® z® Hypervisor™ Additional Trademarks may be identified in the body of this document. Other company, product, or service names may be trademarks or service marks of others. Notices The last page of this document contains copyright information, important notices, and other information. Acknowledgements While this whitepaper has two principal authors/editors it is the culmination of the work of a number of different subject matter experts within IBM who contributed ideas, detailed technical information, and the occasional photograph and section of description.
    [Show full text]
  • Openpower AI CERN V1.Pdf
    Moore’s Law Processor Technology Firmware / OS Linux Accelerator sSoftware OpenStack Storage Network ... Price/Performance POWER8 2000 2020 DRAM Memory Chips Buffer Power8: Up to 12 Cores, up to 96 Threads L1, L2, L3 + L4 Caches Up to 1 TB per socket https://www.ibm.com/blogs/syst Up to 230 GB/s sustained memory ems/power-systems- openpower-enable- bandwidth acceleration/ System System Memory Memory 115 GB/s 115 GB/s POWER8 POWER8 CPU CPU NVLink NVLink 80 GB/s 80 GB/s P100 P100 P100 P100 GPU GPU GPU GPU GPU GPU GPU GPU Memory Memory Memory Memory GPU PCIe CPU 16 GB/s System bottleneck Graphics System Memory Memory IBM aDVantage: data communication and GPU performance POWER8 + 78 ms Tesla P100+NVLink x86 baseD 170 ms GPU system ImageNet / Alexnet: Minibatch size = 128 ADD: Coherent Accelerator Processor Interface (CAPI) FPGA CAPP PCIe POWER8 Processor ...FPGAs, networking, memory... Typical I/O MoDel Flow Copy or Pin MMIO Notify Poll / Int Copy or Unpin Ret. From DD DD Call Acceleration Source Data Accelerator Completion Result Data Completion Flow with a Coherent MoDel ShareD Mem. ShareD Memory Acceleration Notify Accelerator Completion Focus on Enterprise Scale-Up Focus on Scale-Out and Enterprise Future Technology and Performance DriVen Cost and Acceleration DriVen Partner Chip POWER6 Architecture POWER7 Architecture POWER8 Architecture POWER9 Architecture POWER10 POWER8/9 2007 2008 2010 2012 2014 2016 2017 TBD 2018 - 20 2020+ POWER6 POWER6+ POWER7 POWER7+ POWER8 POWER8 P9 SO P9 SU P9 SO 2 cores 2 cores 8 cores 8 cores 12 cores w/ NVLink
    [Show full text]
  • 18-741 Advanced Computer Architecture Lecture 1: Intro And
    18-742 Fall 2012 Parallel Computer Architecture Lecture 10: Multithreading II Prof. Onur Mutlu Carnegie Mellon University 9/28/2012 Reminder: Review Assignments Due: Sunday, September 30, 11:59pm. Mutlu, “Some Ideas and Principles for Achieving Higher System Energy Efficiency,” NSF Position Paper and Presentation 2012. Ebrahimi et al., “Parallel Application Memory Scheduling,” MICRO 2011. Seshadri et al., “The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing,” PACT 2012. Pekhimenko et al., “Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency,” CMU SAFARI Technical Report 2012. 2 Feedback on Project Proposals In your email General feedback points Concrete mechanisms, even if not fully right, is a good place to start testing your ideas 3 Last Lecture Asymmetry in Memory Scheduling Wrap up Asymmetry Multithreading Fine-grained Coarse-grained 4 Today More Multithreading 5 More Multithreading 6 Readings: Multithreading Required Spracklen and Abraham, “Chip Multithreading: Opportunities and Challenges,” HPCA Industrial Session, 2005. Kalla et al., “IBM Power5 Chip: A Dual-Core Multithreaded Processor,” IEEE Micro 2004. Tullsen et al., “Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor,” ISCA 1996. Eyerman and Eeckhout, “A Memory-Level Parallelism Aware Fetch Policy for SMT Processors,” HPCA 2007. Recommended Hirata et al., “An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads,” ISCA 1992 Smith, “A pipelined, shared resource MIMD computer,” ICPP 1978. Gabor et al., “Fairness and Throughput in Switch on Event Multithreading,” MICRO 2006. Agarwal et al., “APRIL: A Processor Architecture for Multiprocessing,” ISCA 1990. 7 Review: Fine-grained vs.
    [Show full text]
  • IBM Power Systems Performance Report Apr 13, 2021
    IBM Power Performance Report Power7 to Power10 September 8, 2021 Table of Contents 3 Introduction to Performance of IBM UNIX, IBM i, and Linux Operating System Servers 4 Section 1 – SPEC® CPU Benchmark Performance 4 Section 1a – Linux Multi-user SPEC® CPU2017 Performance (Power10) 4 Section 1b – Linux Multi-user SPEC® CPU2017 Performance (Power9) 4 Section 1c – AIX Multi-user SPEC® CPU2006 Performance (Power7, Power7+, Power8) 5 Section 1d – Linux Multi-user SPEC® CPU2006 Performance (Power7, Power7+, Power8) 6 Section 2 – AIX Multi-user Performance (rPerf) 6 Section 2a – AIX Multi-user Performance (Power8, Power9 and Power10) 9 Section 2b – AIX Multi-user Performance (Power9) in Non-default Processor Power Mode Setting 9 Section 2c – AIX Multi-user Performance (Power7 and Power7+) 13 Section 2d – AIX Capacity Upgrade on Demand Relative Performance Guidelines (Power8) 15 Section 2e – AIX Capacity Upgrade on Demand Relative Performance Guidelines (Power7 and Power7+) 20 Section 3 – CPW Benchmark Performance 19 Section 3a – CPW Benchmark Performance (Power8, Power9 and Power10) 22 Section 3b – CPW Benchmark Performance (Power7 and Power7+) 25 Section 4 – SPECjbb®2015 Benchmark Performance 25 Section 4a – SPECjbb®2015 Benchmark Performance (Power9) 25 Section 4b – SPECjbb®2015 Benchmark Performance (Power8) 25 Section 5 – AIX SAP® Standard Application Benchmark Performance 25 Section 5a – SAP® Sales and Distribution (SD) 2-Tier – AIX (Power7 to Power8) 26 Section 5b – SAP® Sales and Distribution (SD) 2-Tier – Linux on Power (Power7 to Power7+)
    [Show full text]
  • Hard Real-Time Performances in Multiprocessor-Embedded Systems Using ASMP-Linux
    Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2008, Article ID 582648, 16 pages doi:10.1155/2008/582648 Research Article Hard Real-Time Performances in Multiprocessor-Embedded Systems Using ASMP-Linux Emiliano Betti,1 Daniel Pierre Bovet,1 Marco Cesati,1 and Roberto Gioiosa1, 2 1 System Programming Research Group, Department of Computer Science, Systems, and Production, University of Rome “Tor Vergata”, Via del Politecnico 1, 00133 Rome, Italy 2 Computer Architecture Group, Computer Science Division, Barcelona Supercomputing Center (BSC), c/ Jordi Girona 31, 08034 Barcelona, Spain Correspondence should be addressed to Roberto Gioiosa, [email protected] Received 30 March 2007; Accepted 15 August 2007 Recommended by Ismael Ripoll Multiprocessor systems, especially those based on multicore or multithreaded processors, and new operating system architectures can satisfy the ever increasing computational requirements of embedded systems. ASMP-LINUX is a modified, high responsive- ness, open-source hard real-time operating system for multiprocessor systems capable of providing high real-time performance while maintaining the code simple and not impacting on the performances of the rest of the system. Moreover, ASMP-LINUX does not require code changing or application recompiling/relinking. In order to assess the performances of ASMP-LINUX, benchmarks have been performed on several hardware platforms and configurations. Copyright © 2008 Emiliano Betti et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 1. INTRODUCTION nificantly higher than that of single-core processors, we can expect that in a near future many embedded systems will This article describes a modified Linux kernel called ASMP- make use of multicore processors.
    [Show full text]
  • Power1.Ps (Mpage)
    Low Energy & Power Design Issues Low Power Design Problem • Processor trends Microprocessor Power • Circuit and Technology Issues (source ISSCC) 30 • Architectural optimizations • Low power µP research project 20 10 Power (Watt) 0 75 80 85 90 95 Year When supply voltage drops to 1Volt, then 100Watts = 100 Amps Slide 2 Portable devices Two Kinds of Computation Required • General purpose processing (what you have been Portable Functions studying so far) • Multimodal radio • Bursty - mostly idle with bursts of computation • Protocols, ECC, ... • Maximum possible throughput required during active • Voice I/O compression & periods decompression • Handwriting recognition • Signal processing (for multimedia, wireless Battery • Text/Graphics processing communications, etc.) (40+ lbs) • Video decompression • Stream based computation • Speech recognition • No advantage in increasing processing rate above • Java interpreter required for real-time requirements How to get 1 month of operation? Slide 3 Slide 4 Optimizing for Energy Consumption Switching Energy • Conventional General Purpose processors (e.g. Vdd Pentiums) • Performance is everything ... somehow we’ll get the Vin Vout power in and back out • 10-100 Watts, 100-1000 Mips = .01 Mips/mW CL • Energy Optimized but General Purpose • Keep the generality, but reduce the energy as much as 2 possible - e.g. StrongArm Energy/transition = CL * Vdd • .5 Watts, 160 Mips = .3 Mips/mW 2 Power = Energy/transition * f = CL * Vdd * f • Energy Optimized and Dedicated • 100 Mops/mW Slide 5 Slide 6 Low Power
    [Show full text]
  • Chapter 1-Introduction to Microprocessors File
    Chapter 1 Introduction to Microprocessors Expected Outcomes Explain the role of the CPU, memory and I/O device in a computer Distinguish between the microprocessor and microcontroller Differentiate various form of programming languages Compare between CISC vs RISC and Von Neumann vs Harvard architecture NMKNYFKEEUMP Introduction A microprocessor is an integrated circuit built on a tiny piece of silicon It contains thousands or even millions of transistors which are interconnected via superfine traces of aluminum The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions The particular functions a microprocessor perform are dictated by software The first microprocessor was the Intel 4004 (16-pin) introduced in 1971 containing 2300 transistors with 46 instruction sets Power8 processor, by contrast, contains 4.2 billion transistors NMKNYFKEEUMP Introduction Computer is an electronic machine that perform arithmetic operation and logic in response to instructions written Computer requires hardware and software to function Hardware is electronic circuit boards that provide functionality of the system such as power supply, cable, etc CPU – Central Processing Unit/Microprocessor Memory – store all programming and data Input/Output device – the flow of information Software is a programming that control the system operation and facilitate the computer usage Programming is a group of instructions that inform the computer to perform certain task NMKNYFKEEUMP Introduction Computer
    [Show full text]
  • Power Architecture® ISA 2.06 Stride N Prefetch Engines to Boost Application's Performance
    Power Architecture® ISA 2.06 Stride N prefetch Engines to boost Application's performance History of IBM POWER architecture: POWER stands for Performance Optimization with Enhanced RISC. Power architecture is synonymous with performance. Introduced by IBM in 1991, POWER1 was a superscalar design that implemented register renaming andout-of-order execution. In Power2, additional FP unit and caches were added to boost performance. In 1996 IBM released successor of the POWER2 called P2SC (POWER2 Super chip), which is a single chip implementation of POWER2. P2SC is used to power the 30-node IBM Deep Blue supercomputer that beat world Chess Champion Garry Kasparov at chess in 1997. Power3, first 64 bit SMP, featured a data prefetch engine, non-blocking interleaved data cache, dual floating point execution units, and many other goodies. Power3 also unified the PowerPC and POWER Instruction set and was used in IBM's RS/6000 servers. The POWER3-II reimplemented POWER3 using copper interconnects, delivering double the performance at about the same price. Power4 was the first Gigahertz dual core processor launched in 2001 which was awarded the MicroProcessor Technology Award in recognition of its innovations and technology exploitation. Power5 came in with symmetric multi threading (SMT) feature to further increase application's performance. In 2004, IBM with 15 other companies founded Power.org. Power.org released the Power ISA v2.03 in September 2006, Power ISA v.2.04 in June 2007 and Power ISA v.2.05 with many advanced features such as VMX, virtualization, variable length encoding, hyper visor functionality, logical partitioning, virtual page handling, Decimal Floating point and so on which further boosted the architecture leadership in the market place and POWER5+, Cell, POWER6, PA6T, Titan are various compliant cores.
    [Show full text]