DOCSLIB.ORG

March 11, 2010 Presentation

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
March 11, 2010 Presentation IBM Power Systems POWER7TM Announcement, The Next Generation of Power Systems Power your planet. February 25, 2010 IBM Power Systems 2 February 25, 2010 IBM Power Systems POWER7 System Highlights .Balance System Design - Cache, Memory, and IO .POWER7 Processor Technology - 6th Implementation of multi-core design - On chip L2 & L3 caches .POWER7 System Architecture - Blades to High End offerings - Enhances memory implementation - PCIe, SAS / SATA .Built in Virtualization - Memory Expansion - VM Control .Green Technologies - Processor Nap & Sleep Mode - Memory Power Down support - Aggressive Power Save / Capping Modes 600 500 .Availability 400 - Processor Instruction Retry 300 - Alternate Process Recovery 200 100 - Concurrent Add & Services 0 JS23 JS43 520 550 560 570/16 570/32 595 3 February 25, 2010 IBM Power Systems 4 February 25, 2010 IBM Power Systems Power Processor Technology IBM investment in the Power Franchise Dependable Execution for a decade POWER8 POWER7 45 nm Globalization and globally POWER6 available resources 65 nm •Performance/System Capacity POWER5 •4-5X increase from Power6 130 nm •Multi Core – Up to 8 POWER4 •SMT4 – 4 threads/core 180 nm . Dual Core •On-Chip eDRAM . High Frequencies • Energy . Dual Core . Virtualization + . Enhanced Scaling • Efficiency: 3-4X Power6 . Memory Subsystem + . SMT • Dynamic Energy . Dual Core . Altivec . Distributed Switch + Management . Chip Multi Processing . Instruction Retry . Distributed Switch . Core Parallelism + • Reliability + . Dyn Energy Mgmt . Shared L2 . FP Performance + . SMT + •Memory DIMM – DRAM . Dynamic LPARs (32) . Memory bandwidth + . Protection Keys Sparing . Virtualization •N+2 Voltage Regulator Redundancy •Protection Keys + 5 February 25, 2010 IBM Power Systems POWER6 – POWER7 Compare Wireless world Mobile platforms are developing as new means of identification. Security technology is many years behind the security used to protect PCs. Supply chain The chain is only as strong as the weakest link… partners need to shoulder their fair share of the load for compliance and the responsibility for failure. Clients expect privacy An assumption or expectation now exists to integrate security into the infrastructure, processes and applications to maintain privacy. Compliance fatigue Organizations are trying to maintain a balance between investing in both the security and compliance postures. 6 February 25, 2010 IBM Power Systems POWER7 Processor Chip Cores : 8 ( 4 / 6 core options ) Local SMP Links 567mm2 Technology: 45nm lithography, Cu, SOI, eDRAM POWER7 POWER7 POWER7 POWER7 F Transistors: 1.2 B CORE A CORE CORE CORE S Equivalent function of 2.7B L2 Cache T L2 Cache L2 Cache L2 Cache eDRAM efficiency L3 REGION Eight processor cores 12 execution units per core MC0 MC1 L3 Cache and 4 Way SMT per core – up to 4 threads per core Chip Interconnect 32 Threads per chip L2 Cache L2 Cache L2 Cache L2 Cache L1: 32 KB I Cache / 32 KB D Cache L2: 256 KB per core POWER7 POWER7 POWER7 POWER7 L3: Shared 32MB on chip eDRAM CORE CORE CORE CORE Dual DDR3 Memory Controllers 100 GB/s Memory bandwidth per chip Remote SMP & I/O Links Scalability up to 32 Sockets 360 GB/s SMP bandwidth/chip 20,000 coherent operations in flight Binary Compatibility with POWER6 7 February 25, 2010 IBM Power Systems Memory Channel Bandwidth Evolution POWER5 POWER6 POWER7 Memory Performance: Memory Performance: Memory Performance: 2x DIMM 4x DIMM 6x DIMM D D D D D D D D D D D D D D D D D D D D R R R R R R R R R R 3 3 3 3 3 3 3 3 3 3 DDR2 @ 553 MHz DDR2 @ 553 / 667 MHz DDR3 @ 1066 MHz Effective Bandwidth: Effective Bandwidth: Effective Bandwidth: 1.1 GB/s 2.6 GB/sec 6.4 GB/sec 8 February 25, 2010 IBM Power Systems Multi-threading Evolution Single thread Out of Order S80 HW Multi-thread FX0 FX0 FX1 FX1 FP0 FP0 FP1 FP1 LS0 LS0 LS1 LS1 BRX BRX CRL CRL POWER5 2 Way SMT POWER7 4 Way SMT FX0 FX0 FX1 FX1 FP0 FP0 FP1 FP1 LS0 LS0 LS1 LS1 BRX BRX CRL CRL No Thread Executing Thread 0 Executing Thread 1 Executing Thread 2 Executing Thread 3 Executing 9 February 25, 2010 IBM Power Systems POWER7 TurboCore Mode Power 780 TurboCore Chip . TurboCore Chips: 4 available cores Core Core Core Core . Aggregation of L3 Caches of unused cores. P O . TurboCore chips have a 2X the L3 Cache W L2 L2 L2 L2 per Chip available E S R - 4 TurboCore Chips L3 = 32 MB M P . Performance gain over POWER6. G 32 MB F - Provides up to 1.5X per core to core X L3 Cache A . Chips run at higher frequency: B R - Power reduction of unused cores. I C . With “Reboot”, System can be reconfigured B L2 L2 L2 L2 U to 8 core mode. S - ASM Menus Core Core Core Core Unused Memory Interface TurboCores Core 1 February 25, 2010 0 IBM Power Systems Active Memory Expansion Effectively up to 100% more True True True Expanded Expanded Expanded memory memory memory memory memory memory memory True True True Expanded Expanded memory Expanded memory memory memory memory memory POWER7 advantage Expand memory beyond physical limits More effective server consolidation Run more application workload / users per partition Run more partitions and more workload per server 11 February 25, 2010 IBM Power Systems Active Memory Expansion Innovative POWER7 technology For AIX 6.1 or later For POWER7 servers Uses compression/decompression to effectively expand the true physical memory available for client workloads Often a small amount of processor resource provides a significant increase in the effective memory maximum Processor resource part of AIX partition’s resource and licensing Actual expansion results dependent upon how “compressible” the data being used in the application A SAP ERP sample workload shows up to 100% expansion, Your results will vary Estimator tool and free trial available 12 February 25, 2010 IBM Power Systems Active Memory Expansion & Active Memory Sharing Active Memory Expansion Active Memory Sharing Effectively gives more memory capacity to Moves memory from one partition to the partition using compression / another decompression of the contents in true Best fit when one partition is not busy memory when another partition is busy AIX partitions only AIX, IBM i, and Linux partitions 15 #10 #9 #8 10 #7 #6 #5 5 #4 #3 #2 0 #1 Active Memory Expansion Active Memory Sharing Supported, potentially a very nice option Considerations Only AIX partitions using Active Memory Expansion Active Memory Expansion value is dependent upon compressibility of data and available CPU resource (Source: CSI 2007 Survey, n= 494, US) 13 February 25, 2010 IBM Power Systems TPMD: Thermal Power Management Device . TPMD card is part of the base hardware configuration. Residing on the processor planar . TPMD function is comprised of a risk processor and data acquisition . TPMD monitor power usage and temperatures in real time . Responsible for thermal protection of the processor cards . Can adjust the processor power and performance in real time. If the temperature exceeds an upper (functional) threshold, TPMD actively reduces power consumption by reducing processor voltage and frequency or throttling memory as needed. If the temperature is lower than upper (functional) threshold, TPMD will allows POWER7 cores to “Over clock” if workloads demands are present. 14 February 25, 2010 IBM Power Systems 15 February 25, 2010 IBM Power Systems Power Systems – February 2010 . New POWER7 in middle of the line Power 780 . Power 750 Express . Power 755 for HPC Power 770 . Power 770 modular . Power 780 modular high-end . POWER6 continues . Power 520, Blades Power 750 . Power 550 . Power 560 . Power 570 . Power 575 Power 560 . Power 595 Power 755 JS Blades IBM Systems Software 16 February 25, 2010 IBM Power Systems Processor Offerings for Rack / HPC POWER7 Processor Offerings Cores / Socket 4 6 8 Power 750 - Yes Yes (3) Power 755 - - Yes Configuration Options Sockets 1 2 3 4 6 Core Chips 6 Cores 12 Cores 18 Cores 24 Cores 8 Core Chips 8 Cores 16 Cores 24 Cores 32 Cores 1-4 Socket System 17 February 25, 2010 IBM Power Systems Processor Offerings for Modular Systems POWER7 TurboCore / CoD Processor Offerings Cores / Socket 4 TurboCore 6 8 Base 8 Enhanced Power 770 - Yes Yes - Power 780 Yes - - Yes Configuration Options Enclosures 1 2 3 4 4 Core Chips 8 Cores 16 Cores 24 Cores 32 Cores 6 Core Chips 12 Cores 24 Cores 36 Cores 48 Cores 8 Core Chips 16 Cores 32 Cores 48 Cores 64 Cores 18 February 25, 2010 IBM Power Systems POWER7 Model 750 8233-E8B 19 February 25, 2010 IBM Power Systems Power 750 System 8233-E8B 6 Cores @ 3.3 GHz POWER7 Architecture 8 Cores @ 3. 0, 3.3, 3.55 GHz Up to 181,000 CPW! Max: 4 Sockets DDR3 Memory Up to 512 GB Up to 8 Drives (HDD or SSD) System Unit SAS SFF 73 / 146 / 300GB @ 15k (2.4 TB) Bays (Opt: cache & RAID-5/6) PCIe x8: 3 Slots (2 shared) System Unit PCI-X DDR: 2 Slots IO Expansion Slots 1 GX+ & Opt 1 GX++ 12X cards 4U Integrated SAS / SATA Yes Depth: 28.8” System Unit 3 USB, 2 Serial, 2 HMC Integrated Ports Integrated Virtual Quad 10/100/1000 Ethernet Optional: Dual 10 Gb System Unit Media Bays 1 Slim-line DVD & 1 Half Height IO Drawers w/ PCI slots PCIe = 4 Max: PCI-X = Max 8 Cluster 12X SDR / DDR (IB technology) Redundant Power and Yes (AC or DC Power) Cooling Single phase 240 VAC or -48 VDC Certification (SoD) NEBS / ETSI for harsh environments Active Thermal Power Management EnergyScale Dynamic Energy Save & Capping 20 February 25, 2010 IBM Power Systems Power 750 Information…. .Physical Specifications: - Width: 440 mm (17.3 in) - Depth: 730.8 mm (28.8 in) - Height: 175 mm (6.89 in) - Weight: 54.4 kg (120 lb) .Operating voltage: - 200 to 240 V .Operating Frequency: 50/60 Hz .Power Consumption: 1950 watts (maximum) .Power Factor: 0.97 .Thermal Output: 4778 Btu/hour (maximum) .Power-source Loading Recommend either - 1.443 KVA (maximum configuration) rack acoustic doors or .Noise Level and Sound locating in a machine room.
Load more

Recommended publications
  • POWER® Processor-Based Systems
    IBM® Power® Systems RAS Introduction to IBM® Power® Reliability, Availability, and Serviceability for POWER9® processor-based systems using IBM PowerVM™ With Updates covering the latest 4+ Socket Power10 processor-based systems IBM Systems Group Daniel Henderson, Irving Baysah Trademarks, Copyrights, Notices and Acknowledgements Trademarks IBM, the IBM logo, and ibm.com are trademarks or registered trademarks of International Business Machines Corporation in the United States, other countries, or both. These and other IBM trademarked terms are marked on their first occurrence in this information with the appropriate symbol (® or ™), indicating US registered or common law trademarks owned by IBM at the time this information was published. Such trademarks may also be registered or common law trademarks in other countries. A current list of IBM trademarks is available on the Web at http://www.ibm.com/legal/copytrade.shtml The following terms are trademarks of the International Business Machines Corporation in the United States, other countries, or both: Active AIX® POWER® POWER Power Power Systems Memory™ Hypervisor™ Systems™ Software™ Power® POWER POWER7 POWER8™ POWER® PowerLinux™ 7® +™ POWER® PowerHA® POWER6 ® PowerVM System System PowerVC™ POWER Power Architecture™ ® x® z® Hypervisor™ Additional Trademarks may be identified in the body of this document. Other company, product, or service names may be trademarks or service marks of others. Notices The last page of this document contains copyright information, important notices, and other information. Acknowledgements While this whitepaper has two principal authors/editors it is the culmination of the work of a number of different subject matter experts within IBM who contributed ideas, detailed technical information, and the occasional photograph and section of description.
    [Show full text]
  • Openpower AI CERN V1.Pdf
    Moore’s Law Processor Technology Firmware / OS Linux Accelerator sSoftware OpenStack Storage Network ... Price/Performance POWER8 2000 2020 DRAM Memory Chips Buffer Power8: Up to 12 Cores, up to 96 Threads L1, L2, L3 + L4 Caches Up to 1 TB per socket https://www.ibm.com/blogs/syst Up to 230 GB/s sustained memory ems/power-systems- openpower-enable- bandwidth acceleration/ System System Memory Memory 115 GB/s 115 GB/s POWER8 POWER8 CPU CPU NVLink NVLink 80 GB/s 80 GB/s P100 P100 P100 P100 GPU GPU GPU GPU GPU GPU GPU GPU Memory Memory Memory Memory GPU PCIe CPU 16 GB/s System bottleneck Graphics System Memory Memory IBM aDVantage: data communication and GPU performance POWER8 + 78 ms Tesla P100+NVLink x86 baseD 170 ms GPU system ImageNet / Alexnet: Minibatch size = 128 ADD: Coherent Accelerator Processor Interface (CAPI) FPGA CAPP PCIe POWER8 Processor ...FPGAs, networking, memory... Typical I/O MoDel Flow Copy or Pin MMIO Notify Poll / Int Copy or Unpin Ret. From DD DD Call Acceleration Source Data Accelerator Completion Result Data Completion Flow with a Coherent MoDel ShareD Mem. ShareD Memory Acceleration Notify Accelerator Completion Focus on Enterprise Scale-Up Focus on Scale-Out and Enterprise Future Technology and Performance DriVen Cost and Acceleration DriVen Partner Chip POWER6 Architecture POWER7 Architecture POWER8 Architecture POWER9 Architecture POWER10 POWER8/9 2007 2008 2010 2012 2014 2016 2017 TBD 2018 - 20 2020+ POWER6 POWER6+ POWER7 POWER7+ POWER8 POWER8 P9 SO P9 SU P9 SO 2 cores 2 cores 8 cores 8 cores 12 cores w/ NVLink
    [Show full text]
  • IBM Power Systems Performance Report Apr 13, 2021
    IBM Power Performance Report Power7 to Power10 September 8, 2021 Table of Contents 3 Introduction to Performance of IBM UNIX, IBM i, and Linux Operating System Servers 4 Section 1 – SPEC® CPU Benchmark Performance 4 Section 1a – Linux Multi-user SPEC® CPU2017 Performance (Power10) 4 Section 1b – Linux Multi-user SPEC® CPU2017 Performance (Power9) 4 Section 1c – AIX Multi-user SPEC® CPU2006 Performance (Power7, Power7+, Power8) 5 Section 1d – Linux Multi-user SPEC® CPU2006 Performance (Power7, Power7+, Power8) 6 Section 2 – AIX Multi-user Performance (rPerf) 6 Section 2a – AIX Multi-user Performance (Power8, Power9 and Power10) 9 Section 2b – AIX Multi-user Performance (Power9) in Non-default Processor Power Mode Setting 9 Section 2c – AIX Multi-user Performance (Power7 and Power7+) 13 Section 2d – AIX Capacity Upgrade on Demand Relative Performance Guidelines (Power8) 15 Section 2e – AIX Capacity Upgrade on Demand Relative Performance Guidelines (Power7 and Power7+) 20 Section 3 – CPW Benchmark Performance 19 Section 3a – CPW Benchmark Performance (Power8, Power9 and Power10) 22 Section 3b – CPW Benchmark Performance (Power7 and Power7+) 25 Section 4 – SPECjbb®2015 Benchmark Performance 25 Section 4a – SPECjbb®2015 Benchmark Performance (Power9) 25 Section 4b – SPECjbb®2015 Benchmark Performance (Power8) 25 Section 5 – AIX SAP® Standard Application Benchmark Performance 25 Section 5a – SAP® Sales and Distribution (SD) 2-Tier – AIX (Power7 to Power8) 26 Section 5b – SAP® Sales and Distribution (SD) 2-Tier – Linux on Power (Power7 to Power7+)
    [Show full text]
  • System Automation for Z/OS : Planning and Installation About This Publication
    System Automation for z/OS Version 4.Release 1 Planning and Installation IBM SC34-2716-01 Note Before using this information and the product it supports, read the information in Appendix H, “Notices,” on page 201. Edition Notes This edition applies to IBM System Automation for z/OS® (Program Number 5698-SA4) Version 4 Release 1, an IBM licensed program, and to all subsequent releases and modifications until otherwise indicated in new editions. This edition replaces SC34-2716-00. © Copyright International Business Machines Corporation 1996, 2017. US Government Users Restricted Rights – Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Figures................................................................................................................. xi Tables................................................................................................................ xiii Accessibility........................................................................................................ xv Using assistive technologies...................................................................................................................... xv Keyboard navigation of the user interface................................................................................................. xv About this publication........................................................................................ xvii Who Should Use This Publication.............................................................................................................xvii
    [Show full text]
  • Upgrade to POWER9 Planning Checklist
    Achieve your full business potential with IBM POWER9 Future-forward infrastructure designed to crush data-intensive workloads Upgrade to POWER9 Planning Checklist Using this checklist will help to ensure that your infrastructure strategy is aligned to your needs, avoiding potential cost overruns or capability shortfalls. 1 Determine current and future capacity 5 Identify all dependencies for major database requirements. Bring your team together, platforms, including Oracle, DB2, SAP HANA, assess your current application workload and open-source databases like EnterpriseDB, requirements and three- to five-year MongoDB, neo4j, and Redis. You’re likely outlook. You’ll then have a good picture running major databases on the Power of when and where application growth Systems platform; co-locating your current will take place, enabling you to secure servers may be a way to reduce expenditure capacity at the appropriate time on an and increase flexibility. as-needed basis. 6 Understand current and future data center 2 Assess operational efficiencies and identify environmental requirements. You may be opportunities to improve service levels unnecessarily overspending on power, while decreasing exposure to security and cooling and space. Savings here will help your compliancy issues/problems. With new organization avoid costs associated with data technologies that allow you to easily adjust center expansion. capacity, you will be in a much better position to lower costs, improve service Identify the requirements of your strategy for levels, and increase efficiency. 7 on- and off-premises cloud infrastructure. As you move to the cloud, ensure you 3 Create a detailed inventory of servers have a strong strategy to determine which across your entire IT infrastructure.
    [Show full text]
  • Power8 Quser Mspl Nov 2015 Handout
    IBM Power Systems Power Systems Hardware: Today and Tomorrow November 2015 Mark Olson [email protected] © 2015 IBM Corporation IBM Power Systems POWER8 Chip © 2015 IBM Corporation IBM Power Systems Processor Technology Roadmap POWER11 Or whatever it is POWER10 named Or whatever it is POWER9 named Or whatever it is named POWER7 POWER8 POWER6 45 nm 22 nm POWER5 65 nm 130 nm POWER4 90 nm 180 nm 130 nm 2001 2004 2007 2010 2014 Future 3 © 2015 IBM Corporation IBM Power Systems Processor Chip Comparisons POWER5 POWER6 POWER7 POWER7+ POWER8 2004 2007 2010 2012 45nm SOI 32nm SOI 22nm SOI Technology 130nm SOI 65nm SOI eDRAM eDRAM eDRAM Compute Cores 2 2 8 8 12 Threads SMT2 SMT2 SMT4 SMT4 SMT8 Caching On-chip 1.9MB (L2) 8MB (L2) 2 + 32MB (L2+3) 2 + 80MB (L2+3) 6 + 96MB (L2+3) Off-chip 36MB (L3) 32MB (L3) None None 128MB (L4) Bandwidth Sust. Mem. 15GB/s 30GB/s 100GB/s 100GB/s 230GB/s Peak I/O 6GB/s 20GB/s 40GB/s 40GB/s 96GB/s 4 © 2015 IBM Corporation IBM Power Systems Processor Designs POWER5+ POWER6 POWER7 POWER7+ POWER8 Max cores 4 2 8 8 12 Technology 90nm 65nm 45nm 32nm 22nm Size 245 mm2 341 mm2 567 mm2 567 mm2 650 mm2 * Transistors 276 M 790 M 1.2 B 2.1 B 4.2 B * 1.9 4 - 5 3 – 4 Up to 4.4 Up to 4.1 Frequencies GHz GHz GHz GHz GHz ** SMT (threads) 2 2 4 4 8 L2 Cache 1.9MB Shared 4MB / Core 256KB / core 256KB / core 512KB/core 4MB / Core 10MB / Core 8MB / Core L3 Cache 36MB 32MB On chip On chip On chip L4 Cache -- -- -- -- Up to 128MB Bandwidth Sust memory 15GB/s 30GB/s 100GB/s 100GB/s 230GB/s Peak I/O 6GB/s 20GB/s 40GB/s 40GB/s 96GB/s * with 12-core
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • KVM on POWER7
    Developments in KVM on Power Paul Mackerras, IBM LTC OzLabs [email protected] Outline . Introduction . Little-endian support . OpenStack . Nested virtualization . Guest hotplug . Hardware error detection and recovery 2 21 October 2013 © 2013 IBM Introduction • We will be releasing POWER® machines with KVM – Announcement by Arvind Krishna, IBM executive • POWER8® processor disclosed at Hot Chips conference – 12 cores per chip, 8 threads per core – 96kB L1 cache, 512kB L2 cache, 8MB L3 cache per core on chip u u Guest Guest m host OS process m e e OS OS q host OS process q host OS process KVM Host Linux Kernel SAPPHIRE FSP POWER hardware 3 21 October 2013 © 2013 IBM Introduction • “Sapphire” firmware being developed for these machines – Team led by Ben Herrenschmidt – Successor to OPAL • Provides initialization and boot services for host OS – Load first-stage Linux kernel from flash – Probe the machine and set up device tree – Petitboot bootloader to load and run the host kernel (via kexec) • Provides low-level run-time services to host kernel – Communication with the service processor (FSP) • Console • Power and reboot control • Non-volatile memory • Time of day clock • Error logging facilities – Some low-level error detection and recovery services 4 21 October 2013 © 2013 IBM Little-endian Support • Modern POWER CPUs have a little-endian mode – Instructions and multi-byte data operands interpreted in little-endian byte order • Lowest-numbered byte is least significant, rather than most significant – “True” little endian, not address swizzling
    [Show full text]
  • Title: an Inside Look at POWER7 Architecture
    2011 IBM Power Systems Technical University October 10-14 | Fontainebleau Miami Beach | Miami, FL Title: An Inside Look at POWER7 Architecture Session ID: HE01 Joel M. Tendler [email protected] © Copyright IBM Corporation 2011 Materials may not be reproduced in whole or in part without the prior written permission of IBM. 5.3 IBM Power Systems value proposition PowerPower SystemsSystems TechnicalTechnical UniversityUniversity Deliver business value by leveraging technology Performance Flexibility Reliability Affordability + – . the highest value at the lowest risk with leading technology © Copyright IBM Corporation 2011 2 Over 20 Years of POWER Processors 45nm PowerPower SystemsSystems TechnicalTechnical UniversityUniversity 65nm Next Gen. POWER7 RS64IV Sstar 130nm -Multi-core POWER6TM RS64III Pulsar 180nm -Ultra High Frequency .18um RS64II North Star .25um POWER5TM -SMT RS64I Apache .35um BiCMOS .5um POWER4TM Major POWER® Innovation .5um Muskie A35 .22um -Dual Core -1990 RISC Architecture .5um -1994 SMP -Cobra A10 -1995 Out of Order Execution -64 bit -1996 64 Bit Enterprise Architecture POWER3TM -1997 Hardware Multi-Threading .35um -630 -2001 Dual Core Processors -2001 Large System Scaling -2001 Shared Caches .72um -2003 On Chip Memory Control POWER2TM P2SC -2003 SMT .25um -2006 Ultra High Frequency RSC .35um -2006 Dual Scope Coherence Mgmt 1.0um -2006 Decimal Float/VSX .6um -2006 Processor Recovery/Sparing 604e -2009 Balanced Multi-core Processor -603 POWER1 -2009 On Chip EDRAM -AMERICA’s -601 1990 1995 2000 2005 2010 * Dates represent
    [Show full text]
  • IBM Energyscale for POWER7 Processor-Based Systems
    ibm IBM EnergyScale for POWER7 Processor-Based Systems March 2013 Authors: Martha Broyles Chris Francois Andrew Geissler Gordon Grout Michael Hollinger Todd Rosedahl Guillermo J. Silva Mark Vanderwiel Jeff Van Heuklon Brian Veale Table of Contents Executive Overview...................................................................................................................................4 EnergyScale Features.................................................................................................................................5 Power Trending................................................................................................................................................................5 Thermal Reporting...........................................................................................................................................................6 Static Power Saver Mode.................................................................................................................................................6 Dynamic Power Saver Mode...........................................................................................................................................7 Differences in Dynamic Power Saver from POWER6 to POWER7.........................................................................7 Power Management's Effect on System Performance................................................................................................8 Dynamic Power Saver Tunable Parameters...................................................................................................................10
    [Show full text]
  • IBM Energyscale for POWER7 Processor-Based Systems
    ibm IBM EnergyScale for POWER7 Processor-Based Systems August 2010 Authors: Martha Broyles Chris Francois Andrew Geissler Michael Hollinger Todd Rosedahl Guillermo Silva Jeff Van Heuklon Brian Veale Table of Contents Executive Overview...................................................................................................................................4 EnergyScale Features.................................................................................................................................5 Power Trending................................................................................................................................................................5 Thermal Reporting...........................................................................................................................................................5 Static Power Saver Mode.................................................................................................................................................6 Dynamic Power Saver Mode...........................................................................................................................................6 Differences in Dynamic Power Saver from POWER6 to POWER7.........................................................................7 Power Management's Effect on System Performance................................................................................................8 Power Capping.................................................................................................................................................................9
    [Show full text]
  • CFD) Applications on HPC Systems
    Performance Portability Strategies for Computational Fluid Dynamics (CFD) Applications on HPC Systems A DISSERTATION SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA BY Pei-Hung Lin IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Doctor of Philosophy Professor Pen-Chung Yew, Advisor Professor Paul R. Woodward, Co-Advisor June, 2013 c Pei-Hung Lin 2013 ALL RIGHTS RESERVED Acknowledgements First and foremost, I would like to thank my advisors, professor Paul R. Woodward and professor Pen-Chung Yew for their guidance in my doctoral program. Professor Woodward continuously inspired and encouraged me to pursue my research career. Professor Yew with his solid background in architecture and compiler guided me and taught me in academic research. They selflessly advised me conducting researches and shared their experiences in research, in work, and also in their lives. I also would like to thank my thesis committee members { professor Antonia Zhai and professor Eric Van Wyk for their insight and efforts in reviewing my dissertation. Furthermore, I would like to thank my colleagues and mentors in my graduate study. Dr. Dan Quinlan, and Dr. Chunhua Liao provided me the internship opportunities to work at Lawrence Livermore National Laboratory and will continue to support me in my post-doctoral career. Dr. Jagan Jayaraj (now at Sandia National Laboratory) and Michael Knox were my long-term colleagues in both study and work and we exchanged lots ideas in achieving our research goal. Dr. Ben Bergen and Dr. William Dai at Los Alamos National Laboratory provided me strong support and great assistant during my internship at LANL.
    [Show full text]