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Development System Reference Guide 10.1 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. © 2002–2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Development System Reference Guide www.xilinx.com Table of Contents Preface: About This Guide Guide Contents . 17 Additional Resources . 20 Conventions . 20 Typographical. 20 Online Document . 21 Chapter 1: Introduction Command Line Program Overview . 23 Command Line Syntax . 24 Command Line Options . 24 –f (Execute Commands File) . 24 –h (Help) . 25 –intstyle (Integration Style) . 26 –p (Part Number) . 27 Invoking Command Line Programs. 28 Chapter 2: Design Flow Design Flow Overview . 29 Design Entry and Synthesis . 33 Hierarchical Design . 33 Schematic Entry Overview . 34 HDL Entry and Synthesis . 35 Functional Simulation . 35 Constraints . 35 Netlist Translation Programs . 36 Design Implementation . 36 Mapping (FPGAs Only) . 39 Placing and Routing (FPGAs Only) . 39 Bitstream Generation (FPGAs Only) . 39 Design Verification . 40 Simulation . 42 Static Timing Analysis (FPGAs Only). 47 In-Circuit Verification . 48 FPGA Design Tips . 49 Design Size and Performance. 49 Global Clock Distribution . 49 Data Feedback and Clock Enable . 50 Counters . 51 Other Synchronous Design Considerations . 52 Chapter 3: Tcl Tcl Overview . 53 Development System Reference Guide www.xilinx.com 3 R Tcl Device Support. 54 Xilinx Tcl Shell . 54 Accessing Help . 54 Tcl Fundamentals . 55 Xilinx Namespace . 56 Xilinx Tcl Commands . 56 Tcl Commands for General Use . 59 lib_vhdl . 59 partition . 61 process . 66 project . 68 timing_analysis. 78 xfile . 87 Tcl Commands for Advanced Scripting . 90 collection (create and manage a collection) . 90 object (get object information) . 97 search (search for matching design objects) . 99 Project and Process Properties . 101 Project Properties. 101 Process Properties - Synthesize Process . 103 Process Properties - Translate Process . 107 Process Properties - Map Process . 108 Process Properties - Place & Route Process . 110 Process Properties - Generate Post-Place & Route Static Timing Process . ..

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