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2 Field-Programmable Gate Arrays 8 2.1 Background Research Collection Doctoral Thesis Hades: fast hardware synthesis tools and a reconfigurable coprocessor Author(s): Ludwig, Stefan Hans-Melchior Publication Date: 1997 Permanent Link: https://doi.org/10.3929/ethz-a-001859409 Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library Hades — Fast Hardware Synthesis Tools and a Reconfigurable Coprocessor Diss. ETH No. 12276 Hades — Fast Hardware Synthesis Tools and a Reconfigurable Coprocessor A dissertation submitted to the SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH (ETH ZURICH¨ ) for the degree of Doctor of Technical Sciences presented by Stefan Hans-Melchior Ludwig Dipl. Informatik-Ing. ETH born May 21, 1966 citizen of Schiers, Graub¨unden accepted on the recommendation of Prof. Dr. N. Wirth, examiner Prof. Dr. H. Eberle, co-examiner 1997 c Stefan H.-M. Ludwig, 1997 Fur¨ Irene, Vanessa und Cyril. Fur¨ meine Eltern. Acknowledgments I would like to express my appreciation and gratitude to my advisor Prof. Niklaus Wirth. His striving for simplicity and understandability are unparalleled. If Hades is fast, it is because of the constant “fear” of spending a cycle too much here or a byte too much there. He is a fabulous teacher and it was a pleasure to work under his supervision. I thank Prof. Hans Eberle for being my co-examiner. His knowledge in hardware design was very welcomed during the development of the Hades hardware and his constant skepticism of the feasibility of reconfigurable coprocessors was a driving force behind this work. Many thanks go to my colleague, collaborator and office mate for the past four years, Stephan Gehring, for his excellent Trianus framework, for the discussions and feedback, for the criti- cism and for his willingness to enhance or alter Trianus almost instantly. It was fun to work with you! Thanks to Immo Noack for many things, especially for being who you are. Thanks and acknowledgments go to • all of my colleagues at the Institute for Computer Systems for a stimulating and enjoy- able working environment. Remember, there is only one true “Ludwig-of-the-day”. • Erwin Oertli for tips regarding the details of the Hades board and many other things. • Marco Sanvido for the provision of a timing analyzer. • Beat Heeb for helping with the Ceres-2 and Cuno Pfister for having produced CALLAS, a good tool to measure my own work against. • Wolfgang Weck and Clemens Szyperski for discussions on various issues. • Tom Kean for the chip and much more. • Bill Wilkie for answering my endless questions and for never stopping to appreciate my corrections to the data sheet. • the remaining people at Xilinx Development Corp., Scotland, for their openness and generosity. • Virtual Computer Corporation for distributing Hades with their board. • Dr. Roger Woods and Jean-Paul Heron of the DSP Laboratory, Queen’s University of Belfast, for their willingness to work with Hades and for their humor. • Patrick M¨uller and Reto Zimmermann for betting a term project on Hades, and for succeeding. • Chuck Thacker, Dave Conroy and Mark Shand of the Digital Systems Research Center for discussions about FPGAs and high-performance memory systems. • Monty Brekke and Steve Atkins for the Verilog code and Martin Radetzki for the VHDL code. v vi • Peter Alfke for background information on the XC4000 and the FPGA market. • David Hofmann for the logic minimizer. • my proofreaders Stephan Gehring, Taylor Hutt, Cheryl Lins and Nels Vander Zanden. I owe you a dinner in Silicon Valley. This work would have been impossible without the love and support of my beloved wife, Irene. Thank you for everything during the past nine years. I love you! Contents Acknowledgments v Kurzfassung xiii Abstract xiv 1 Introduction 1 1.1Coprocessors.................................. 2 1.2User-ConfigurableHardware.......................... 3 1.3ReconfigurableCoprocessors.......................... 3 1.4HardwareSynthesis............................... 5 1.5Contributions.................................. 5 1.6OverviewofThesis............................... 7 2 Field-Programmable Gate Arrays 8 2.1 Background . ............................. 8 2.2GeneralStructure................................ 9 2.3 The Xilinx XC6200 . ............................. 10 2.4OtherArchitectures............................... 15 2.5Evaluation.................................... 17 3 Foundations: Lola and Trianus 21 3.1 Hardware Description Languages . ..................... 21 3.2 The Hardware Description Language Lola . .............. 21 3.3Trianus..................................... 25 3.4Discussion.................................... 39 4 Hades Hardware 40 4.1Motivation.................................... 41 4.2 Design Alternatives . ............................. 41 4.3OverviewoftheHadesReconfigurableCoprocessor.............. 43 4.4ChoiceofHostWorkstation........................... 43 4.5ArchitectureoftheHadesBoard........................ 46 4.6ConstructingtheBoard............................. 52 4.7SystemSoftware................................ 54 4.8Discussion.................................... 54 5 Hades Software 55 5.1ProblemStatementandMotivation....................... 56 5.2 Programming Methodology . ......................... 60 5.3Overview.................................... 61 5.4Mapper..................................... 61 5.5 Placer and Floor Planner . ......................... 71 5.6Router...................................... 85 vii viii 5.7BitstreamGeneratorandLoader........................ 95 5.8RuntimeSystem................................. 98 5.9 Support Modules and Genericity in Oberon . .............. 100 5.10 Quantitative Issues . ............................. 101 5.11 Experiences with Our Programming Methodology and Oberon . ...... 103 5.12Discussion.................................... 104 6 Application and Evaluation 106 6.1 Applications Running in Hardware . ..................... 106 6.2PatternMatchingApplication.......................... 106 6.3 Comparison to XACT step Series 6000 ..................... 126 6.4HadesintheWorld............................... 131 6.5PossibleFutureApplications.......................... 132 6.6Discussion.................................... 133 7 Related Work 134 7.1CustomComputers............................... 134 7.2ReconfigurableCoprocessors.......................... 135 7.3ReconfigurableProcessors........................... 136 7.4High-LevelHardwareDescription....................... 137 7.5TheNeedforBetterTools........................... 138 8 Summary, Conclusions and Outlook 139 8.1WhathasbeenAccomplished?......................... 139 8.2HadesHardware................................. 139 8.3HadesSoftware................................. 139 8.4LolaandTrianus................................ 140 8.5Conclusions................................... 140 8.6Outlook..................................... 141 A Syntax of Lola 143 B Schema of Hades Coprocessor Board 145 C Photograph of Hades Coprocessor Board 147 D Components for a Hades Board 148 E Hades RC Board Decoder 150 F Wotan Microprocessor 154 F.1 ArchitectureandPrincipleofOperation.................... 154 F.2 LolaCode.................................... 156 F.3 Layout Synthesis . ............................. 164 G Resources on the Web 167 Bibliography 168 Curriculum Vitae 176 List of Figures 1.1CPUandCoprocessor.............................. 2 1.2TypicalReconfigurableCoprocessor...................... 4 1.3HardwareSynthesisFlow............................ 6 2.1GeneralFPGAStructure............................ 9 2.2PassGate.................................... 10 2.3ConfigurationStore............................... 10 2.4 XC6200 Function Unit ............................. 11 2.5 Mux Implementation of the AND and XOR Functions............. 12 2.6 XC6200 Neighbor Routing . ......................... 13 2.7 XC6200 Length-4 FastLANEs ......................... 14 2.8 XC6200 Logic Symbol ............................. 14 2.9CALFunctionUnit............................... 15 2.10 AT6000 Function Unit ............................. 16 2.11 AT6000 Routing Network . ......................... 17 2.12 XC4000EX Function Unit (Simplified) ..................... 18 2.13 XC4000EX Routing (Simplified) . ..................... 18 3.1DifferentViewsinTrianus........................... 28 3.2LolaandTrianusPartinDesignFlowfromFig.1.3.............. 29 3.3TrianusTypesandLolaConstructs....................... 33 3.4 Data Structure for AddElem Type........................ 34 3.5 XC6200 Layout of AddElem .......................... 37 3.6 OBDD for Carry-Out of AddElem ....................... 38 3.7 Schema Showing an AddElem ......................... 39 4.1 Hades Hardware Part within the Design Flow of Fig. 1.3 . .......... 40 4.2 FPGA Attached to the CPU (Two Alternatives) . .............. 42 4.3 FPGA with Local Memory on Extension Card . .............. 44 4.4HadesReconfigurableCoprocessor....................... 45 4.5InterfaceTiming................................ 50 5.1 Hades Software Part within the Design Flow of Fig. 1.3 . .......... 55 5.2RoutingChannel................................ 58 5.3 Wave Expansion (1, 2, 3, 4) with Resulting Route . .............. 59 5.4 XC6200 Cell Configurations (without Registers) . .............. 63 5.5 Mapping of NOT-Gate............................. 64 5.6 Mapping of AND-Gate............................. 66 5.7MappingofLatch................................ 66 5.8MappingofRegister.............................
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