DOCSLIB.ORG

Design Alternatives for Barrel Shifters

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Design Alternatives for Barrel Shifters Design alternatives for barrel shifters Matthew R. Pillmeier Rushmore Pro cessor 2 Unisys Corp oration Blue Bell, PA 19424 Michael J. Schulte and E. George Walters I I I Computer Architecture and Arithmetic Lab oratory Computer Science and Engineering Department Lehigh University Bethlehem, PA 18015, USA ABSTRACT Barrel shifters are often utilized byemb edded digital signal pro cessors and general-purp ose pro cessors to ma- nipulate data. This pap er examines design alternatives for barrel shifters that p erform the following functions: shift right logical, shift right arithmetic, rotate right, shift left logical, shift left arithmetic, and rotate left. Four di erent barrel shifter designs are presented and compared in terms of area and delayforavariety of op erand sizes. This pap er also examines techniques for detecting results that over ow and results of zero in parallel with the shift or rotate op eration. Several Java programs are develop ed to generate structural VHDL mo dels for each of the barrel shifters. Synthesis results show that data-reversal barrel shifters have less area and mask- based data-reversal barrel shifters have less delay than other designs. Mask-based data-reversal barrel shifters are esp ecially attractivewhenover ow and zero detection is also required, since the detection is p erformed in parallel with the shift or rotate op eration. Keywords: barrel shifters, rotators, masks, data-reversal, over ow detection, zero ag, computer arithmetic. 1. INTRODUCTION Shifting and rotating data is required in several applications including arithmetic op erations, variable-length co ding, and bit-indexing. Consequently, barrel shifters, which are capable of shifting or rotating data in a single cycle, are commonly found in b oth digital signal pro cessors and general-purp ose pro cessors. Several patents [1{ 10] and research articles [11{15] have b een written on ecient designs and implementations for barrel shifters. In [16], several 32-bit barrel shifters are compared in terms of delay,power, and p ower-delay pro duct. This pap er examines design alternatives for barrel shifters that p erform the following op erations: shift right logical, shift right arithmetic, rotate right, shift left logical, shift left arithmetic, and rotate left. These designs are optimized to share hardware for di erent op erations. Techniques are also presented for detecting results that over ow and results of zero in parallel with the shift or rotate op eration. Section 2 describ es the basic shift and rotate op erations and gives examples of each op eration. Section 3 presents designs for several typ es of barrel shifters. Section 4 gives area and delay estimates for eachtyp e of barrel shifter as the op erand size varies. Section 5 presents conclusions. Further details on the designs presented in this pap er are given in [17]. 2. SHIFT AND ROTATE OPERATIONS In this pap er, we de ne A to be the input op erand, B to be the shift/rotate amount, and Y to be the shifted/rotated result. We de ne A to be an n-bit value, where n is an integer power of two. Therefore, B is a log (n)-bit integer representing values from 0 to n 1. The barrel shifters presented in this pap er 2 perform the following six op erations: shift right logical, shift right arithmetic, rotate right, shift left logical, shift left arithmetic, and rotate left. Table1gives an example for each of these op erations. In this table, the bit vector for A is denoted as a a a a a a a a and the shift/rotate amount, B , is 3 bits. As illustrated in this 7 6 5 4 3 2 1 0 table: Op eration Y 3-bit shift right logical 0 0 0 a a a a a 7 6 5 4 3 3-bit shift right arithmetic a a a a a a a a 7 7 7 7 6 5 4 3 3-bit rotate right a a a a a a a a 2 1 0 7 6 5 4 3 3-bit shift left logical a a a a a 0 0 0 4 3 2 1 0 3-bit shift left arithmetic a a a a a 0 0 0 7 3 2 1 0 3-bit rotate left a a a a a a a a 4 3 2 1 0 7 6 5 Table 1. Shift and rotate examples for A = a a a a a a a a and B =3. 7 6 5 4 3 2 1 0 3-bit Op co de lef t r otate ar ithmetic Op eration 0 0 0 shift right logical 0 0 1 shift right arithmetic 0 1 X rotate right 1 0 0 shift left logical 1 0 1 shift left arithmetic 1 1 X rotate left Table 2. Op eration control bits. A B -bit shift right logical op eration p erforms a B -bit right shift and sets the upp er B bits of the result to zeros. A B -bit shift right arithmetic op eration performs a B -bit right shift and sets the upp er B bits of the result to a ,which corresp onds to the sign bit of A. n1 A B -bit rotate right op eration p erforms a B -bit right shift and sets the upp er B bits of the result to the lower B bits of A. A B -bit shift left logical op eration p erforms a B -bit left shift and sets the lower B bits of the result to zeros. A B -bit shift left arithmetic op eration p erforms a B -bit left shift and sets the lower B bits of the result to zeros. The sign bit of the result is set to a . n1 A B -bit rotate left op eration p erforms a B -bit left shift and sets the lower B bits of the result to the upp er B bits of A. 3. BARREL SHIFTER DESIGNS This section discusses barrel shifter designs. Basic shifter and rotator designs are describ ed rst in Section 3.1. Mux-based data-reversal barrel shifters, mask-based data-reversal barrel shifters, mask-based two's complement barrel shifters, and mask-based one's complement barrel shifters are then discussed in Sections 3.2 through 3.5. In the following discussion the term multiplexor refers to a 1-bit 2-to-1 multiplexor, unless otherwise stated. The op eration p erformed by the barrel shifters is controlled by a 3-bit op co de, which consists of the bits lef t, r otate,andar ithmetic, as summarized in Table 2. Additional control signals, sr a and sl a, are set to one when p erforming shift right arithmetic and shift left arithmetic op erations, resp ectively. 3.1. Shifters and Rotators An n-bit logarithmic barrel shifter uses log (n) stages [1, 2]. Each bit of the shift amount, B ,controls a di erent 2 k stage of the shifter. The data into the stage controlled by b is shifted by2 bits if b = 1; otherwise it is not k k Figure 1. 8-bit logical right shifter. Figure 2. 8-bit right rotator. shifted. Figure 1 shows the blo ck diagram of an 8-bit logical right shifter, which uses three stages with 4-bit, 2-bit, and 1-bit shifts. To optimize the design, eachmultiplexor that has '0' for one of its inputs can b e replaced b as inputs. by a 2-input and gate with the data bit and k A similar unit that performs right rotations, instead of right shifts, can be designed by mo difying the connections to the more signi cantmultiplexors. Figure 2 shows the blo ck diagram of an 8-bit right rotator, which uses three stages with 4-bit, 2-bit, and 1-bit rotates. The right rotator and the logical right shifter supply di erent inputs to the more signi cantmultiplexors. With the rotator, since all of the input bits are routed to the output, there is no longer a need for interconnect lines carrying zeros. Instead, interconnect lines are k k inserted to enable routing of the 2 low order data bits to the 2 high order multiplexors in the stage controlled by b . Changing from a non-optimized shifter to a rotator has no impact on the theoretical area or delay. The k longer interconnect lines of the rotator, however, can increase b oth area and delay. The logical right shifter can b e extended to also p erform shift right arithmetic and rotate right op erations by adding additional multiplexors. This approach is illustrated in Figure 3, for an 8-bit right shifter/rotator with three stages of 4-bit, 2-bit, and 1-bit shifts/rotates. Initially, a single multiplexor selects b etween '0' for logical k right shifting and a for arithmetic right shifting to pro duce s. In the stage controlled by b ,2 multiplexors n1 k k select b etween s for shifting and the 2 lower bits of the data for rotating. Figure 3. 8-bit mux-based right shifter/rotator. A right shifter can b e extended to also p erform left shift op erations by adding a rowof n multiplexors b oth b efore and after the right shifter [4]. When a left shift op eration is p erformed, these multiplexors reverse the data into and out of the right shifter. When a right shift op eration is p erformed, the data into and out of the shifter is not changed.
Load more

Recommended publications
  • Bit Shifts Bit Operations, Logical Shifts, Arithmetic Shifts, Rotate Shifts
    Why bit operations Assembly languages all provide ways to manipulate individual bits in multi-byte values Some of the coolest “tricks” in assembly rely on Bit Shifts bit operations With only a few instructions one can do a lot very quickly using judicious bit operations And you can do them in almost all high-level ICS312 programming languages! Let’s look at some of the common operations, Machine-Level and starting with shifts Systems Programming logical shifts arithmetic shifts Henri Casanova ([email protected]) rotate shifts Shift Operations Logical Shifts The simplest shifts: bits disappear at one end A shift moves the bits around in some data and zeros appear at the other A shift can be toward the left (i.e., toward the most significant bits), or toward the right (i.e., original byte 1 0 1 1 0 1 0 1 toward the least significant bits) left log. shift 0 1 1 0 1 0 1 0 left log. shift 1 1 0 1 0 1 0 0 left log. shift 1 0 1 0 1 0 0 0 There are two kinds of shifts: right log. shift 0 1 0 1 0 1 0 0 Logical Shifts right log. shift 0 0 1 0 1 0 1 0 Arithmetic Shifts right log. shift 0 0 0 1 0 1 0 1 Logical Shift Instructions Shifts and Numbers Two instructions: shl and shr The common use for shifts: quickly multiply and divide by powers of 2 One specifies by how many bits the data is shifted In decimal, for instance: multiplying 0013 by 10 amounts to doing one left shift to obtain 0130 Either by just passing a constant to the instruction multiplying by 100=102 amounts to doing two left shifts to obtain 1300 Or by using whatever
    [Show full text]
  • Implementation of Optimized CORDIC Designs
    IJIRST –International Journal for Innovative Research in Science & Technology| Volume 1 | Issue 3 | August 2014 ISSN(online) : 2349-6010 Implementation of Optimized CORDIC Designs Bibinu Jacob Reenesh Zacharia M Tech Student Assistant Professor Department of Electronics & Communication Engineering Department of Electronics & Communication Engineering Mangalam College Of Engineering, Ettumanoor Mangalam College Of Engineering, Ettumanoor Abstract CORDIC stands for COordinate Rotation DIgital Computer, which is likewise known as Volder's algorithm and digit-by-digit method. It is a simple and effective method to calculate many functions like trigonometric, hyperbolic, logarithmic etc. It performs complex multiplications using simple shifts and additions. It finds applications in robotics, digital signal processing, graphics, games, and animation. But, there isn't any optimized CORDIC designs for rotating vectors through specific angles. In this paper, optimization schemes and CORDIC circuits for fixed and known rotations are proposed. Finally an argument reduction technique to map larger angle to an angle less than 45 is discussed. The proposed CORDIC cells are simulated by Xilinx ISE Design Suite and shown that the proposed designs offer less latency and better device utilization than the reference CORDIC design for fixed and known angles of rotation. Keywords: Coordinate rotation digital computer (CORDIC), digital signal processing (DSP) chip, very large scale integration (VLSI) _______________________________________________________________________________________________________ I. INTRODUCTION The advances in the very large scale integration (VLSI) technology and the advent of electronic design automation (EDA) tools have been directing the current research in the areas of digital signal processing (DSP), communications, etc. in terms of the design of high speed VLSI architectures for real-time algorithms and systems which have applications in the above mentioned areas.
    [Show full text]
  • Master's Thesis
    Implementation of the Metal Privileged Architecture by Fatemeh Hassani A thesis presented to the University of Waterloo in fulfillment of the thesis requirement for the degree of Masters of Mathematics in Computer Science Waterloo, Ontario, Canada, 2020 c Fatemeh Hassani 2020 Author's Declaration I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. ii Abstract The privileged architecture of modern computer architectures is expanded through new architectural features that are implemented in hardware or through instruction set extensions. These extensions are tied to particular architecture and operating system developers are not able to customize the privileged mechanisms. As a result, they have to work around fixed abstractions provided by processor vendors to implement desired functionalities. Programmable approaches such as PALcode also remain heavily tied to the hardware and modifying the privileged architecture has to be done by the processor manufacturer. To accelerate operating system development and enable rapid prototyping of new operating system designs and features, we need to rethink the privileged architecture design. We present a new abstraction called Metal that enables extensions to the architecture by the operating system. It provides system developers with a general-purpose and easy- to-use interface to build a variety of facilities that range from performance measurements to novel privilege models. We implement a simplified version of the Alpha architecture which we call µAlpha and build a prototype of Metal on this architecture.
    [Show full text]
  • Arithmetic and Logical Unit Design for Area Optimization for Microcontroller Amrut Anilrao Purohit 1,2 , Mohammed Riyaz Ahmed 2 and R
    et International Journal on Emerging Technologies 11 (2): 668-673(2020) ISSN No. (Print): 0975-8364 ISSN No. (Online): 2249-3255 Arithmetic and Logical Unit Design for Area Optimization for Microcontroller Amrut Anilrao Purohit 1,2 , Mohammed Riyaz Ahmed 2 and R. Venkata Siva Reddy 2 1Research Scholar, VTU Belagavi (Karnataka), India. 2School of Electronics and Communication Engineering, REVA University Bengaluru, (Karnataka), India. (Corresponding author: Amrut Anilrao Purohit) (Received 04 January 2020, Revised 02 March 2020, Accepted 03 March 2020) (Published by Research Trend, Website: www.researchtrend.net) ABSTRACT: Arithmetic and Logic Unit (ALU) can be understood with basic knowledge of digital electronics and any engineer will go through the details only once. The advantage of knowing ALU in detail is two- folded: firstly, programming of the processing device can be efficient and secondly, can design a new ALU architecture as per the various constraints of the use cases. The miniaturization of digital circuits can be achieved by either reducing the size of transistor (Moore’s law) or by optimizing the gate count of the circuit. The first has been explored extensively while the latter has been ignored which deals with the application of Boolean rules and requires sound knowledge of logic design. The ultimate outcome is to have an area optimized architecture/approach that optimizes the circuit at gate level. The design of ALU is for various processing devices varies with the device/system requirements. The area optimization places a significant role in the chip design. Here in this work, we have attempted to design an ALU which is area efficient while being loaded with additional functionality necessary for microcontrollers.
    [Show full text]
  • Using LLVM for Optimized Lightweight Binary Re-Writing at Runtime
    Using LLVM for Optimized Lightweight Binary Re-Writing at Runtime Alexis Engelke, Josef Weidendorfer Department of Informatics Technical University of Munich Munich, Germany EMail: [email protected], [email protected] Abstract—Providing new parallel programming models/ab- helpful in reducing any overhead of provided abstractions. stractions as a set of library functions has the huge advantage But with new languages, porting of existing application that it allows for an relatively easy incremental porting path for code is required, being a high burden for adoption with legacy HPC applications, in contrast to the huge effort needed when novel concepts are only provided in new programming old code bases. Therefore, to provide abstractions such as languages or language extensions. However, performance issues PGAS for legacy codes, APIs implemented as libraries are are to be expected with fine granular usage of library functions. proposed [5], [6]. Libraries have the benefit that they easily In previous work, we argued that binary rewriting can bridge can be composed and can stay small and focused. However, the gap by tightly coupling application and library functions at libraries come with the caveat that fine granular usage of runtime. We showed that runtime specialization at the binary level, starting from a compiled, generic stencil code can help library functions in inner kernels will severely limit compiler in approaching performance of manually written, statically optimizations such as vectorization and thus, may heavily compiled version. reduce performance. In this paper, we analyze the benefits of post-processing the To this end, in previous work [7], we proposed a technique re-written binary code using standard compiler optimizations for lightweight code generation by re-combining existing as provided by LLVM.
    [Show full text]
  • Relational Representation of the LLVM Intermediate Language
    NATIONAL AND KAPODISTRIAN UNIVERSITY OF ATHENS SCHOOL OF SCIENCE DEPARTMENT OF INFORMATICS AND TELECOMMUNICATIONS UNDERGRADUATE STUDIES UNDERGRADUATE THESIS Relational Representation of the LLVM Intermediate Language Eirini I. Psallida Supervisors: Yannis Smaragdakis, Associate Professor NKUA Georgios Balatsouras, PhD Student NKUA ATHENS JANUARY 2014 ΕΘΝΙΚΟ ΚΑΙ ΚΑΠΟΔΙΣΤΡΙΑΚΟ ΠΑΝΕΠΙΣΤΗΜΙΟ ΑΘΗΝΩΝ ΣΧΟΛΗ ΘΕΤΙΚΩΝ ΕΠΙΣΤΗΜΩΝ ΤΜΗΜΑ ΠΛΗΡΟΦΟΡΙΚΗΣ ΚΑΙ ΤΗΛΕΠΙΚΟΙΝΩΝΙΩΝ ΠΡΟΠΤΥΧΙΑΚΕΣ ΣΠΟΥΔΕΣ ΠΤΥΧΙΑΚΗ ΕΡΓΑΣΙΑ Σχεσιακή Αναπαράσταση της Ενδιάμεσης Γλώσσας του LLVM Ειρήνη Ι. Ψαλλίδα Επιβλέποντες: Γιάννης Σμαραγδάκης, Αναπληρωτής Καθηγητής ΕΚΠΑ Γεώργιος Μπαλατσούρας, Διδακτορικός φοιτητής ΕΚΠΑ ΑΘΗΝΑ ΙΑΝΟΥΑΡΙΟΣ 2014 UNDERGRADUATE THESIS Relational Representation of the LLVM Intermediate Language Eirini I. Psallida R.N.: 1115200700272 Supervisor: Yannis Smaragdakis, Associate Professor NKUA Georgios Balatsouras, PhD Student NKUA ΠΤΥΧΙΑΚΗ ΕΡΓΑΣΙΑ Σχεσιακή Αναπαράσταση της ενδιάμεσης γλώσσας του LLVM Ειρήνη Ι. Ψαλλίδα Α.Μ.: 1115200700272 Επιβλέπων: Γιάννης Σμαραγδάκης, Αναπληρωτής Καθηγητής ΕΚΠΑ Γεώργιος Μπαλατσούρας, Διδακτορικός φοιτητής ΕΚΠΑ ΠΕΡΙΛΗΨΗ Περιγράφουμε τη σχεσιακή αναπαράσταση της ενδιάμεσης γλώσσας του LLVM, γνωστή ως LLVM IR. Η υλοποίηση μας παράγει σχέσεις από ένα πρόγραμμα εισόδου σε ενδιάμεση μορφή LLVM. Κάθε σχέση αποθηκεύεται σαν πίνακας βάσης δεδομένων σε ένα περιβάλλον εργασίας Datalog. Αναπαριστούμε το σύστημα τύπων καθώς και το σύνολο εντολών της γλώσσας του LLVM. Υποστηρίζουμε επίσης τους περιορισμούς της γλώσσας προσδιορίζοντάς τους με χρήση της προγραμματιστικής γλώσσας Datalog. ΘΕΜΑΤΙΚΗ ΠΕΡΙΟΧΗ: Μεταγλωτιστές, Γλώσσες Προγραμματισμού ΛΕΞΕΙΣ ΚΛΕΙΔΙΑ: σχεσιακή αναπαράσταση, ενδιάμεση αναπαράσταση, σύστημα τύπων, σύνολο εντολών, LLVM, Datalog ABSTRACT We describe the relational representation of the LLVM intermediate language, known as the LLVM IR. Our implementation produces the relation contents of an input program in the LLVM intermediate form. Each relation is stored as a database table into a Datalog workspace.
    [Show full text]
  • 8-Bit Barrel Shifter That May Rotate the Data in Both Direction
    © 2018 IJRAR December 2018, Volume 5, Issue 04 www.ijrar.org (E-ISSN 2348-1269, P- ISSN 2349-5138) Performance Analysis of Low Power CMOS based 8 bit Barrel Shifter Deepti Shakya M-Tech VLSI Design SRCEM Gwalior (M.P) INDIA Shweta Agrawal Assistant Professor, Dept. Electronics & Communication Engineering SRCEM Gwalior (M.P), INDIA Abstract Barrel Shifter isimportant function to optimize the RISC processor, so it is used for rotating and transferring the data either in left or right direction. This shifter is useful in lots of signal processing ICs. The Arithmetic and the Logical Shifters additionally can be changed by the Barrel Shifter Because with the rotation of the data it also supply the utility the data right, left changeall mathemetically or logically.A purpose of this paper is to design the CMOS 8 bit barrel shifter using universal gates with the help of CMOS logic and the most important 2:1 multiplexers (MUX). CMOS based 8 bit barrel shifter has implemented in this paper and compared in terms of delay and power using 90 nm and 45nm technologies. Key Words: CMOS, Low Power, Delay,Barrel Shifter, PMOS, NMOS, Cadence. 1. Introduction In RISC processor ALU plays math and intellectual operations. Number crunching operations operate enlargement, subtraction, addition and division such as sensible operations incorporates AND, OR, NOT, NAND, NOR, XNOR and XOR. RISC processor consist ofnotice in credentials used to keep the operand in store path. The point of control unit is to give a control flag that controls the operation of the processor which tells the small scale building design which operation is done after then the time Barrel shifter is a significant element among rise operation.
    [Show full text]
  • A Lisp Oriented Architecture by John W.F
    A Lisp Oriented Architecture by John W.F. McClain Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degrees of Master of Science in Electrical Engineering and Computer Science and Bachelor of Science in Electrical Engineering at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY September 1994 © John W.F. McClain, 1994 The author hereby grants to MIT permission to reproduce and to distribute copies of this thesis document in whole or in part. Signature of Author ...... ;......................... .............. Department of Electrical Engineering and Computer Science August 5th, 1994 Certified by....... ......... ... ...... Th nas F. Knight Jr. Principal Research Scientist 1,,IA £ . Thesis Supervisor Accepted by ....................... 3Frederic R. Morgenthaler Chairman, Depattee, on Graduate Students J 'FROM e ;; "N MfLIT oARIES ..- A Lisp Oriented Architecture by John W.F. McClain Submitted to the Department of Electrical Engineering and Computer Science on August 5th, 1994, in partial fulfillment of the requirements for the degrees of Master of Science in Electrical Engineering and Computer Science and Bachelor of Science in Electrical Engineering Abstract In this thesis I describe LOOP, a new architecture for the efficient execution of pro- grams written in Lisp like languages. LOOP allows Lisp programs to run at high speed without sacrificing safety or ease of programming. LOOP is a 64 bit, long in- struction word architecture with support for generic arithmetic, 64 bit tagged IEEE floats, low cost fine grained read and write barriers, and fast traps. I make estimates for how much these Lisp specific features cost and how much they may speed up the execution of programs written in Lisp.
    [Show full text]
  • Moscow ML Library Documentation
    Moscow ML Library Documentation Version 2.00 of June 2000 Sergei Romanenko, Russian Academy of Sciences, Moscow, Russia Claudio Russo, Cambridge University, Cambridge, United Kingdom Peter Sestoft, Royal Veterinary and Agricultural University, Copenhagen, Denmark This document This manual describes the Moscow ML library, which includes parts of the SML Basis Library and several extensions. The manual has been generated automatically from the commented signature files. Alternative formats of this document Hypertext on the World-Wide Web The manual is available at http://www.dina.kvl.dk/~sestoft/mosmllib/ for online browsing. Hypertext in the Moscow ML distribution The manual is available for offline browsing at mosml/doc/mosmllib/index.html in the distribution. On-line help in the Moscow ML interactive system The manual is available also in interactive mosml sessions. Type help "lib"; for an overview of built-in function libraries. Type help "fromstring"; for help on a particular identifier, such as fromString. This will produce a menu of all library structures which contain the identifier fromstring (disregarding the lowercase/uppercase distinction): -------------------------------- | 1 | val Bool.fromString | | 2 | val Char.fromString | | 3 | val Date.fromString | | 4 | val Int.fromString | | 5 | val Path.fromString | | 6 | val Real.fromString | | 7 | val String.fromString | | 8 | val Time.fromString | | 9 | val Word.fromString | | 10 | val Word8.fromString | -------------------------------- Choosing a number from this menu will invoke the
    [Show full text]
  • 4-Bit Barrel Shifter Using Transmission Gates
    4-BIT BARREL SHIFTER USING TRANSMISSION GATES M.Muralikrishna1, Nadikuda yadagiri2, GuntupallySai chaitanya3, PalugulaPranay Reddy4 1ECE, Assistant Professor, Anurag Group of Institutions/JNTU University, Hyderabad 2, 3, 4ECE, Anurag Group of Institutions/JNTU University, Hyderabad Abstract In Arithmetic shifter the procedure for Barrel shifter plays an important role in the left shifting is same as logical but in case of floating point arithmetic operations and right shifting the empty spot is filled by signed optimizing the RISC processor and used for bit. Funnel Shifter is combination of all shifters rotating andshifting the data either in left or and rotator In this paper barrel shifter is right direction. This shifter is useful in many designed using multiplexer and implemented signal processing ICs. The arithmetic and using CMOS logic.The MUX used is made with logical shifter are itself a type of barrel the help of universal gates so that the time delay shifter. The main objective of this paper is to and power dissipation is reduced. design a fully custom two bit barrel shifter using 4x1 multiplexer with the help of II. BARREL SHIFTER transmission gates and analyze the A barrel shifter is a digital circuit that can performance on basis of power consumption, shift a data word by a specified number of bits and no of transistors. The tool used to fulfill without the use of any sequential logic, only the purpose is cadence virtuoso using 180nm pure combinatorial logic. One way to technology. implement it is as a sequence of multiplexers Keywords: Barrel shifter, Transmission where the output of one multiplexer is gates, Multiplexer connected to the input of the next multiplexer in a way that depends on the shift distance.
    [Show full text]
  • Tms320c54x DSP Functional Overview
    TMS320C54xt DSP Functional Overview Literature Number: SPRU307A September 1998 – Revised May 2000 Printed on Recycled Paper TMS320C54x DSP Functional Overview This document provides a functional overview of the devices included in the Texas Instrument TMS320C54xt generation of digital signal processors. Included are descriptions of the central processing unit (CPU) architecture, bus structure, memory structure, on-chip peripherals, and the instruction set. Detailed descriptions of device-specific characteristics such as package pinouts, package mechanical data, and device electrical characteristics are included in separate device-specific data sheets. Topic Page 1.1 Features. 2 1.2 Architecture. 7 1.3 Bus Structure. 13 1.4 Memory. 15 1.5 On-Chip Peripherals. 22 1.5.1 Software-Programmable Wait-State Generators. 22 1.5.2 Programmable Bank-Switching . 22 1.5.3 Parallel I/O Ports. 22 1.5.4 Direct Memory Access (DMA) Controller. 23 1.5.5 Host-Port Interface (HPI). 27 1.5.6 Serial Ports. 30 1.5.7 General-Purpose I/O (GPIO) Pins. 34 1.5.8 Hardware Timer. 34 1.5.9 Clock Generator. 34 1.6 Instruction Set Summary. 36 1.7 Development Support. 47 1.8 Documentation Support. 50 TMS320C54x DSP Functional Overview 1 Features 1.1 Features Table 1–1 provides an overview the TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (hereafter referred to as the ’54x unless otherwise specified). The table shows significant features of each device, including the capacity of on-chip RAM and ROM, the available peripherals, the CPU speed, and the type of package with its total pin count.
    [Show full text]
  • The Implementation of Prolog Via VAX 8600 Microcode ABSTRACT
    The Implementation of Prolog via VAX 8600 Microcode Jeff Gee,Stephen W. Melvin, Yale N. Patt Computer Science Division University of California Berkeley, CA 94720 ABSTRACT VAX 8600 is a 32 bit computer designed with ECL macrocell arrays. Figure 1 shows a simplified block diagram of the 8600. We have implemented a high performance Prolog engine by The cycle time of the 8600 is 80 nanoseconds. directly executing in microcode the constructs of Warren’s Abstract Machine. The imulemention vehicle is the VAX 8600 computer. The VAX 8600 is a general purpose processor Vimal Address containing 8K words of writable control store. In our system, I each of the Warren Abstract Machine instructions is implemented as a VAX 8600 machine level instruction. Other Prolog built-ins are either implemented directly in microcode or executed by the general VAX instruction set. Initial results indicate that. our system is the fastest implementation of Prolog on a commercrally available general purpose processor. 1. Introduction Various models of execution have been investigated to attain the high performance execution of Prolog programs. Usually, Figure 1. Simplified Block Diagram of the VAX 8600 this involves compiling the Prolog program first into an intermediate form referred to as the Warren Abstract Machine (WAM) instruction set [l]. Execution of WAM instructions often follow one of two methods: they are executed directly by a The 8600 consists of six subprocessors: the EBOX. IBOX, special purpose processor, or they are software emulated via the FBOX. MBOX, Console. and UO adamer. Each of the seuarate machine language of a general purpose computer.
    [Show full text]