Metal-Semiconductor Junctions: Ohmic Contact and Schottky Junction
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PN Junction Is the Most Fundamental Semiconductor Device
Fundamentals of Microelectronics CH1 Why Microelectronics? CH2 Basic Physics of Semiconductors CH3 Diode Circuits CH4 Physics of Bipolar Transistors CH5 Bipolar Amplifiers CH6 Physics of MOS Transistors CH7 CMOS Amplifiers CH8 Operational Amplifier As A Black Box 1 Chapter 2 Basic Physics of Semiconductors 2.1 Semiconductor materials and their properties 2.2 PN-junction diodes 2.3 Reverse Breakdown 2 Semiconductor Physics Semiconductor devices serve as heart of microelectronics. PN junction is the most fundamental semiconductor device. CH2 Basic Physics of Semiconductors 3 Charge Carriers in Semiconductor To understand PN junction’s IV characteristics, it is important to understand charge carriers’ behavior in solids, how to modify carrier densities, and different mechanisms of charge flow. CH2 Basic Physics of Semiconductors 4 Periodic Table This abridged table contains elements with three to five valence electrons, with Si being the most important. CH2 Basic Physics of Semiconductors 5 Silicon Si has four valence electrons. Therefore, it can form covalent bonds with four of its neighbors. When temperature goes up, electrons in the covalent bond can become free. CH2 Basic Physics of Semiconductors 6 Electron-Hole Pair Interaction With free electrons breaking off covalent bonds, holes are generated. Holes can be filled by absorbing other free electrons, so effectively there is a flow of charge carriers. CH2 Basic Physics of Semiconductors 7 Free Electron Density at a Given Temperature E n 5.21015T 3/ 2 exp g electrons/ cm3 i 2kT 0 10 3 ni (T 300 K) 1.0810 electrons/ cm 0 15 3 ni (T 600 K) 1.5410 electrons/ cm Eg, or bandgap energy determines how much effort is needed to break off an electron from its covalent bond. -
Junction Field Effect Transistor (JFET)
Junction Field Effect Transistor (JFET) The single channel junction field-effect transistor (JFET) is probably the simplest transistor available. As shown in the schematics below (Figure 6.13 in your text) for the n-channel JFET (left) and the p-channel JFET (right), these devices are simply an area of doped silicon with two diffusions of the opposite doping. Please be aware that the schematics presented are for illustrative purposes only and are simplified versions of the actual device. Note that the material that serves as the foundation of the device defines the channel type. Like the BJT, the JFET is a three terminal device. Although there are physically two gate diffusions, they are tied together and act as a single gate terminal. The other two contacts, the drain and source, are placed at either end of the channel region. The JFET is a symmetric device (the source and drain may be interchanged), however it is useful in circuit design to designate the terminals as shown in the circuit symbols above. The operation of the JFET is based on controlling the bias on the pn junction between gate and channel (note that a single pn junction is discussed since the two gate contacts are tied together in parallel – what happens at one gate-channel pn junction is happening on the other). If a voltage is applied between the drain and source, current will flow (the conventional direction for current flow is from the terminal designated to be the gate to that which is designated as the source). The device is therefore in a normally on state. -
The P-N Junction (The Diode)
Lecture 18 The P-N Junction (The Diode). Today: 1. Joining p- and n-doped semiconductors. 2. Depletion and built-in voltage. 3. Current-voltage characteristics of the p-n junction. Questions you should be able to answer by the end of today’s lecture: 1. What happens when we join p-type and n-type semiconductors? 2. What is the width of the depletion region? How does it relate to the dopant concentration? 3. What is built-in voltage? How to calculate it based on dopant concentrations? How to calculate it based on Fermi levels of semiconductors forming the junction? 4. What happens when we apply voltage to the p-n junction? What is forward and reverse bias? 5. What is the current-voltage characteristic for the p-n junction diode? Why is it different from a resistor? 1 From previous lecture we remember: What happens when you join p-doped and n-doped pieces of semiconductor together? When materials are put in contact the carriers flow under driving force of diffusion until chemical potential on both sides equilibrates, which would mean that the position of the Fermi level must be the same in both p and n sides. This results in band bending: - + - + + - - Holes diffuse + Electrons diffuse The electrons will diffuse into p-type material where they will recombine with holes (fill in holes). And holes will diffuse into the n-type materials where they will recombine with electrons. 2 This means that eventually in vicinity of the junction all free carriers will be depleted leaving stripped ions behind, which would produce an electric field across the junction: The electric field results from the deviation from charge neutrality in the vicinity of the junction. -
Manipulation of Electrical Resistivity and Optical Properties of Zinc Oxide Thin Films Grown by Pulsed Laser Deposition and the Sol-Gel Method
MANIPULATION OF ELECTRICAL RESISTIVITY AND OPTICAL PROPERTIES OF ZINC OXIDE THIN FILMS GROWN BY PULSED LASER DEPOSITION AND THE SOL-GEL METHOD by Ryan W. Crisp A thesis submitted to the Faculty and the Board of Trustees of the Colorado School of Mines in partial fulfillment of the requirements for the degree of Master of Science (Applied Phsyics). Golden, Colorado Date Signed: Ryan W. Crisp Signed: Dr. Reuben T. Collins Thesis Advisor Golden, Colorado Date Signed: Dr. Thomas E. Furtak Professor and Head Department of Physics ii ABSTRACT Adjusting and optimizing the electrical resistivity and optical transparency of transparent conducting oxides (TCOs) is critically important to the quality of many solid state devices. In this work, the electrical and optical properties of zinc oxide thin films grown by the sol- gel method and by pulsed laser deposition are studied. A minimum electrical resistivity of 5.7×10−4 Ω·cm at an oxygen partial pressure of 0.01 mbar for room temperature (RT) growth by pulsed laser deposition (PLD) was achieved. This optimal film had a calculated transparency >90% in the visible region. The measurement techniques used and a full ex- ploration of the various growth parameters (growth temperature, ambient gas type, ambient gas pressure, and annealing treatments) are discussed. The optimized growth parameters were applied to create a TCO top contact to nanorod structures that are potentially useful as solar cell devices. The application of this optimized film offers future work possibilities to perfect a promising up and coming device. iii TABLE OF CONTENTS ABSTRACT . iii LIST OF FIGURES . -
The Pennsylvania State University the Graduate School THE
The Pennsylvania State University The Graduate School THE EFFECTS OF INTERFACE AND SURFACE CHARGE ON TWO DIMENSIONAL TRANSITORS FOR NEUROMORPHIC, RADIATION, AND DOPING APPLICATIONS A Dissertation in Electrical Engineering by Andrew J. Arnold © 2020 Andrew J. Arnold Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy August 2020 The dissertation of Andrew J. Arnold was reviewed and approved by the following: Thomas Jackson Professor of Electrical Engineering Co-Chair of Committee Saptarshi Das Assistant Professor of Engineering Science and Mechanics Dissertation Advisor Co-Chair of Committee Swaroop Ghosh Assistant Professor of Electrical Engineering Rongming Chu Associate Professor of Electrical Engineering Sukwon Choi Assistant Professor of Mechanical Engineering Kultegin Aydin Professor of Electrical Engineering Head of the Department of Electrical Engineering ii Abstract The scaling of silicon field effect transistors (FETs) has progressed exponentially following Moore’s law, and is nearing fundamental limitations related to the materials and physics of the devices. Alternative materials are required to overcome these limitations leading to increasing interest in two dimensional (2D) materials, and transition metal dichalcogenides (TMDs) in particular, due to their atomically thin nature which provides an advantage in scalability. Numerous investigations within the literature have explored various applications of these materials and assessed their viability as a replacement for silicon FETs. This dissertation focuses on several applications of 2D FETs as well as an exploration into one of the most promising methods to improve their performance. Neuromorphic computing is an alternative method to standard computing architectures that operates similarly to a biological nervous system. These systems are composed of neurons and operate based on pulses called action potentials. -
Lecture 16 the Pn Junction Diode (III)
Lecture 16 The pn Junction Diode (III) Outline • Small-signal equivalent circuit model • Carrier charge storage –Diffusion capacitance Reading Assignment: Howe and Sodini; Chapter 6, Sections 6.4 - 6.5 6.012 Spring 2007 Lecture 16 1 I-V Characteristics Diode Current equation: ⎡ V ⎤ I = I ⎢ e(Vth )−1⎥ o ⎢ ⎥ ⎣ ⎦ I lg |I| 0.43 q kT =60 mV/dec @ 300K Io 0 0 V 0 V Io linear scale semilogarithmic scale 6.012 Spring 2007 Lecture 16 2 2. Small-signal equivalent circuit model Examine effect of small signal adding to forward bias: ⎡ ⎛ qV()+v ⎞ ⎤ ⎛ qV()+v ⎞ ⎜ ⎟ ⎜ ⎟ ⎢ ⎝ kT ⎠ ⎥ ⎝ kT ⎠ I + i = Io ⎢ e −1⎥ ≈ Ioe ⎢ ⎥ ⎣ ⎦ If v small enough, linearize exponential characteristics: ⎡ qV qv ⎤ ⎡ qV ⎤ ()kT (kT ) (kT )⎛ qv ⎞ I + i ≈ Io ⎢e e ⎥ ≈ Io ⎢e ⎜ 1 + ⎟ ⎥ ⎣⎢ ⎦⎥ ⎣⎢ ⎝ kT⎠ ⎦⎥ qV qV qv = I e()kT + I e(kT ) o o kT Then: qI i = • v kT From a small signal point of view. Diode behaves as conductance of value: qI g = d kT 6.012 Spring 2007 Lecture 16 3 Small-signal equivalent circuit model gd gd depends on bias. In forward bias: qI g = d kT gd is linear in diode current. 6.012 Spring 2007 Lecture 16 4 Capacitance associated with depletion region: ρ(x) + qNd p-side − n-side (a) xp x = xn vD VD − qNa = − QJ qNaxp ρ(x) + qNd p-side −x −x n-side (b) p p x xn xn = + > > vD VD vd VD-- − qNa x < x |q | < |Q | p p, J J = − qJ qNaxp = ∆ ∆ρ = ρ − ρ qj qNa xp (x) (x) (x) + qNd X p-side d n-side (c) x n xn − − xp xp x q = q − Q > j j j 0 − qN = −qN x − −qN a − = − ∆ a p ( axp) qj qNd xn = − qNa (xp xp) ∆ = qNa xp Depletion or junction capacitance: dqJ C j = C j (VD ) = dvD VD qεsNa Nd C j = A 2()Na + Nd ()φB −VD 6.012 Spring 2007 Lecture 16 5 Small-signal equivalent circuit model gd Cj can rewrite as: qεsNa Nd φB C j = A • 2()Na + Nd φB ()φB −VD C or, C = jo j V 1− D φB φ Under Forward Bias assume V ≈ B D 2 C j = 2C jo Cjo ≡ zero-voltage junction capacitance 6.012 Spring 2007 Lecture 16 6 3. -
Electrical Properties of Silicon Nanowires Schottky Barriers Prepared by MACE at Different Etching Time
Electrical Properties of Silicon Nanowires Schottky Barriers Prepared by MACE at Different Etching Time Ahlem Rouis ( [email protected] ) Universite de Monastir Faculte des Sciences de Monastir https://orcid.org/0000-0002-9480-061X Neila Hizem Universite de Monastir Faculte des Sciences de Monastir Mohamed Hassen Institut Supérieur des Sciences Appliquées et de Technologie de Sousse: Institut Superieur des Sciences Appliquees et de Technologie de Sousse Adel kalboussi Universite de Monastir Faculte des Sciences de Monastir Original Research Keywords: Electrical Properties of Silicon, Etching Time, symmetrical current-voltage, capacitance-voltage Posted Date: February 11th, 2021 DOI: https://doi.org/10.21203/rs.3.rs-185736/v1 License: This work is licensed under a Creative Commons Attribution 4.0 International License. Read Full License Electrical properties of silicon nanowires Schottky barriers prepared by MACE at different etching time Ahlem Rouis 1, *, Neila Hizem1, Mohamed Hassen2, and Adel kalboussi1. 1Laboratory of Microelectronics and Instrumentation (LR13ES12), Faculty of Science of Monastir, Avenue of Environment, University of Monastir, 5019 Monastir, Tunisia. 2Higher Institute of Applied Sciences and Technology of Sousse, Taffala City (Ibn Khaldoun), 4003 Sousse, Tunisia. * Address correspondence to E-mail: [email protected] ABSTRACT This article focused on the electrical characterization of silicon nanowires Schottky barriers following structural analysis of nanowires grown on p-type silicon by Metal (Ag) Assisted Chemical Etching (MACE) method distinguished by their different etching time (5min, 10min, 25min). The SiNWs are well aligned and distributed almost uniformly over the surface of a silicon wafer. In order to enable electrical measurement on the silicon nanowires device, Schottky barriers were performed by depositing Al on the vertically aligned SiNWs arrays. -
Bulk Foil Pt-Rh Micro-Relays for High Power Rf and Other Applications
BULK FOIL PT-RH MICRO-RELAYS FOR HIGH POWER RF AND OTHER APPLICATIONS by Fatih Mert Ozkeskin A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Mechanical Engineering) in The University of Michigan 2011 Doctoral Committee: Professor Yogesh B. Gianchandani, Chair Professor Kamal Sarabandi Associate Professor Katsuo Kurabayashi Assistant Professor Mina Rais-Zadeh © Fatih Mert Ozkeskin 2011 To father, Tayfur Ozkeskin ii ACKNOWLEDGEMENTS First of all, I would like to thank and express my deepest gratitude to my research advisor Professor Yogesh B. Gianchandani for his endless support, mentoring and encouragement throughout my doctoral study. Second of all, I would like to thank Professor Kamal Sarabandi for his invaluable guidance. I would also like to thank Professor Katsuo Kurabayashi and Professor Mina Rais-Zadeh for being in my dissertation committee. I would like to thank Dr. Tao Li and Dr. Mark Richardson for being great mentors and for training me on the µEDM which I have used extensively. I would also like to thank to Sangjo Choi, for spending a great deal of effort and countless of hours for RF design and testing. I would like to thank to Dr. Adip Nashashibi for helping with RF testing equipment. I am also indebted to all the WIMS and SSEL staff especially to Trasa Bukhardt and Fran Doman for taking care of all my administrative work and research purchases. I would like to thank my research group members Tao, Naveen, Karthik, Christine, Scott Wright, Scott Green, Allan, Heidi, Erwin, Jun, Ravish, Seungdo and Xin. It has been a wonderful experience working with them all along. -
MOCVD Regrown Ohmic Contacts to Algan/Gan Heterostructures
MOCVD Regrown Ohmic Contacts to AlGaN/GaN Heterostructures Savannah Benbrook ([email protected]) Yanni Dahmani ([email protected]) Mentor: Dr. Xiaqing Xu Spring 2018 Abstract: AlGaN/GaN transfer length method (TLM) and Hall devices were fabricated with n+ doped GaN recessed Ohmic contact regions by metal-organic chemical vapor deposition (MOCVD) regrowth technology. The impact of MOCVD regrowth temperature and precursor flow rates on the quality and growth rate of n+ GaN were qualitatively evaluated through scanning electron microscopy (SEM). Ti/Al/Pt/Au metallized regrown n+ GaN Ohmic contacts -3 2 exhibited a minimum specific contact resistivity of 1.3 x 10 Ω cm and sheet resistance of 150 Ω/sq. It is hypothesized that carbon traces remaining on the AlGaN/GaN samples prior to re-entering the MOCVD chamber for regrowth is the cause of abnormal porous regions and defect density in the n+GaN film and the subsequently high specific contact resistivities. I. Introduction & Motivation Gallium Nitride (GaN)-based heterostructures are frequently employed in high-frequency, high-power, and optoelectronic devices due to their wide bandgap, high breakdown voltage, high electron saturation velocity, and high thermal conductivity [1]. Furthermore, GaN heterostructured devices have demonstrated thermal stability up to 1000C in vacuum, making GaN-based devices of great interest to the high-temperature device community and enabling their use in extreme environment applications where traditional semiconductor materials like Silicon cannot survive, such as Venus exploration [2]. However, current GaN-based device reliability is dominated not by the robust heterostructured material itself, but by the accompanying contact metallization schemes. -
A Vertical Silicon-Graphene-Germanium Transistor
ARTICLE https://doi.org/10.1038/s41467-019-12814-1 OPEN A vertical silicon-graphene-germanium transistor Chi Liu1,3, Wei Ma 1,2,3, Maolin Chen1,2, Wencai Ren 1,2 & Dongming Sun 1,2* Graphene-base transistors have been proposed for high-frequency applications because of the negligible base transit time induced by the atomic thickness of graphene. However, generally used tunnel emitters suffer from high emitter potential-barrier-height which limits the tran- sistor performance towards terahertz operation. To overcome this issue, a graphene-base heterojunction transistor has been proposed theoretically where the graphene base is 1234567890():,; sandwiched by silicon layers. Here we demonstrate a vertical silicon-graphene-germanium transistor where a Schottky emitter constructed by single-crystal silicon and single-layer graphene is achieved. Such Schottky emitter shows a current of 692 A cm−2 and a capacitance of 41 nF cm−2, and thus the alpha cut-off frequency of the transistor is expected to increase from about 1 MHz by using the previous tunnel emitters to above 1 GHz by using the current Schottky emitter. With further engineering, the semiconductor-graphene- semiconductor transistor is expected to be one of the most promising devices for ultra-high frequency operation. 1 Shenyang National Laboratory for Materials Science, Institute of Metal Research, Chinese Academy of Sciences, 72 Wenhua Road, Shenyang 110016, China. 2 School of Materials Science and Engineering, University of Science and Technology of China, 72 Wenhua Road, Shenyang 110016, China. 3These authors contributed equally: Chi Liu, Wei Ma. *email: [email protected] NATURE COMMUNICATIONS | (2019) 10:4873 | https://doi.org/10.1038/s41467-019-12814-1 | www.nature.com/naturecommunications 1 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-12814-1 n 1947, the first transistor, named a bipolar junction transistor electron microscope (SEM) image in Fig. -
Photodetectors
Photodetectors • Convert light signals to a voltage or current. • The absorption of photons creates electron hole pairs. • Electrons in the CB and holes in the VB. • A p + n type junction describes a heavily doped p-type material(acceptors) that is much greater than a lightly doped n-type material (donor) that it is embedded into. • Illumination window with an annular electrode for photon passage. • Anti-reflection coating ( Si 3 N 4 ) reduces reflections. Vr (a) SiO 2 R Vout Electrode p+ Iph Photodetectors h" > E + g h e– n E + Antireflection Electrode • The side is on the order of less than a coating p W Depletion region micron thick (formed by planar diffusion ! (b) net into n-type epitaxial layer). eNd x • A space charge distribution occurs about the junction within the depletion layer. –eNa E (x) (c) • The depletion region extends x predominantly into the lightly doped n region ( up to 3 microns max) E max (a) A schematic diagram of a reverse biased pn junction photodiode. (b) Net space charge across the diode in the depletion region. Nd and Na are the donor and acceptor concentrations in the p and n sides. (c). The field in the depletion region. © 1999 S.O. Kasap, Optoelectronics (Prentice Hall) Photodetectors Short wavelengths (ex. UV) are absorbed at the surface, and longer wavelengths (IR) will penetrate into the depletion layer. What would be a fundamental criteria for a photodiode with a wide spectral response? Thin p-layer and thick n layer. What does thickness of depletion layer determine (along with reverse bias)? Diode capacitance. -
Microstructure and Properties of Aluminum Contacts Formed on Gaas(100) by Low Pressure Chemical Vapor Deposition with Dimethylethylamine Alane Source
Microstructure and Properties of Aluminum Contacts Formed on GaAs(100) by Low Pressure Chemical Vapor Deposition with Dimethylethylamine Alane Source V. SHASHKIN1, S. RUSHWORTH2 V. DANIL'TSEV1, A. MUREL1, Yu. DROZDOV1, S. GUSEV1, O. KHRYKIN1, and N. VOSTOKOV1 1.- Institute for Physics of Microstructures RAS, 603600, Nizhny Novgorod, Russia 2.- Epichem company, Bromborough, Wirral, UK We report on a low pressure chemical vapor deposition of metallic thin aluminum films on GaAs (001) with a dimethylethylamine alane (DMEAA) source and H2 as a carrier gas. The deposition temperatures varied in the range 130÷360°C. Integrated volumes for Al (111), (100), (110)R and (110) grains were estimated by the x-ray diffraction technique and the growth temperature values preferred for every type of grains were observed. The experimentally observed dominance of Al(110)R over Al(110), irrespective of the substrate miscut direction, supports the GaAs(100) inner anisotropy effect on the Al grain orientation. Electrical resistivity was 5 µΩ·cm for best Al films. The Schottky barrier heights were near an 0.7 eV level and the ideality factor n= 1.1. Nonalloyed ohmic contacts were fabricated on an n- type GaAs epitaxial layer with an additional set of Si δ-layers near the Al/GaAs interface. Specific 2 contact resistance ρc = 7 µΩ см was measured. Best contacts were obtained at a deposition temperature lower than 250°C. Key words: Aluminum films on GaAs, Schottky barrier, nonalloyed ohmic contact 2 INTRODUCTION Chemical vapor deposition of metallic aluminum layers using a dimethylethylamine alane (DMEAA) precursor as a metalorganic source has been actively investigated in the last few years.1-5 High purity Al films with electrical resistivity close to the bulk value,3 and selective growth of Al 4 into µm-size holes of SiO2 mask have been successfully demonstrated as a method of multilevel metallization in modern integrated circuit technology.