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||||||||IIIHIIII O USOO544551A United States Patent (19) 11) Patent Number: 5,144,551 Cepulis (45) Date of Patent: Sep ||||||||IIIHIIII o USOO544551A United States Patent (19) 11) Patent Number: 5,144,551 Cepulis (45) Date of Patent: Sep. 1, 1992 (54) COMPUTER MEMORY MANAGEMENT METHOD UTILIZING SEGMENTATION OTHER PUBLICATIONS AND PROTECTION TECHNIQUES Oct. 20, 1988 Intel Corporation letter and attachments from Ms. S. Roach regarding emulating 286 Loadall 75)75 InventorI : Darrenen J. Cepulis, Houston,s Tex instruction. Attachments include suggested code for (73) Assignee: Compaq Computer Corporation, emulation. Houston, Tex. Microprocessor and peripheral handbook, vol. I, Intel (21) Appl. No.: 714,552 Corp. 1988, pp. 4-121-4-127. e J. Crawford, P. Gelsinger, Programming the 80386, (22 Filed: Jun. 13, 1991 Sybex, 1987, pp. 54-59, 431-477, 488-489, 644-646. Related U.S. Application Data Primary Examiner-Kevin A. Kriess Attorney, Agent, or Firm-Pravel, Gambrell, Hewitt, 63) Continuation of Ser. No. 354,144, May 19, 1989, aban- Kimball & Krieger doned. ABST 5) Int. C. .............................................. G06F 12/00 (57)7 RAct 52) U.S. C. ............................. 395/425; 364/DIG. 1; A method for managing memory in a computer system 364/232.9, 364/246.6, 364/246.7:364/247; utilizing Intel Corporation's method of segmentation, 364/247.3; 364/247.2; 364/243; 364/243.4; memory management and protection techniques. The 364/243.41; 364/255.7; 364/255.1; 364/254.8; method is directed toward loading all computer regis 364/264; 364/264. 1; 364/DIG. 1; 395/650; ters and segment descriptor tables from a table of pre 395/700 stored values in memory while operating in real mode. 58) Field of Search ........................ 395/650, 700, 425 At least two of the registers addresses are in excess of the real mode boundary of 1 Mbyte. The method de (56) References Cited scribed permits these registers to be loaded, without the U.S. PATENT DOCUMENTS ... generation of illegal flag values or general protection 4,525,780 6/1985 Bratt et al. .......................... 364/200 violations. 4,580,217 4/1986 Celio ............... A. ... 364/200 4,761,737 8/1988 Duvall et al. ....................... 364200 3 Claims, 8 Drawing Sheets 14 1 O 16 ('-12 Ya NDEX P T RPL Ds 15 3 2 O U.S. Patent Sep. 1, 1992 Sheet 1 of 8 5,144,551 14 1 YaO INDEX 16? ( rp? 12 Ds 15 3 2 O F.G. 1A 24b N 26 18 240 22 BASE ATTRIBUTES BASELO LIMIT 63 56 55 4O 39 1615 O - - 7 - - - H - He 555453oxoavur 52 51 unpople,4847 45 4443 type40l 126 F.G. 1B VIRTUAL MEMORY | LINEAR ADDRESS SPACE IMT C 28 T Y 20 BASE B -- LIMIT B 16 44 DS INDEX DS DESCRIPTOR BASE B 18 BASE C - LIMIT C 42 LIMIT A BASE C SEGMENT A % BASE A -- LIMIT A 40 BASE A FG. 1 C U.S. Patent Sep. 1, 1992 Sheet 2 of 8 5,144,551 52 SI - O DATA SEG O SEGMENT2 FG. 2A FG. 2B LEVEL O U.S. Patent Sep. 1, 1992 Sheet 3 of 8 5,144,551 FG. 4 U.S. Patent Sep. 1, 1992 Sheet 4 of 8 5,144,551 80286 LOADALL memory format 80286 LOADALL memory format User Register Areo Segment Descriptor Area Offset Offset None MSW ES (BASE) None ES (AR) ES (LIMIT) TR CS (BASE) Flag Word CS (AR) SSCS (BASESSE SS (AR) SS (LIMIT) DS (BASE) DS (AR) DS (LIMIT) GOTR LDT DTR TSS F.G. 5B 5A 386 LOADALL BUFFER Field Type DS GDT LIMIT DS GDT BASE ES GDT LIMIT ES GDT BASE DS GDT 286 LIMIT DS GDT 286 BASELO DS GDT 286 BASEH DS GDT 286 ACCESS DS GOT 286 RESERVED WORD ES GDT 286 Li MIT ES GDT 286 BASELO ES GDT 286 BASEH ES GDT 286 ACCESS ES GDT 286 RESERVED WORD DS LDT 386 Li MIT LO DS LDT 386 BASELLO DS LDT 386 BASEMD DS LDT 386 ACCESS DS LDT 386 LIMIT. H F.G. 5C DS LDT 386 BASEH ES LDT 386 LIMITLO ES LDT 386 BASELLO ES LDT 386 BASEMD ES LDT 386 ACCESS ES LDT 386 LIMIT. H. ES LDT 386 BASEH U.S. Patent Sep. 1, 1992 Sheet 5 of 8 5,144,551 91 O START 7920 SAVE COMMAND STACK FRAME; FAULTING PROTECT INSTRUCTION REGISTERS 286 LOADALL 930 CAPTURE AND SAVE INTERRUPTED COMMAND FAULTING NSTRUCTION 940 386 LOADALL DETERMINE FAULTING WORD AND INSTRUCTION RESTORE STACK FRAME, REGISTERS; CHAN TO FAULTING WORD = LOCK INTERRUPT 6 PREFX 1 120 TERMINATE INCREMENT NSTRUCTION POINTER PAST 1130 LOCK PRINT ERROR MESSAGE AND 970 HANG MACHINE RESTORE COMMAND STACK FRAME AND REGISTERS 98O TERMINATE F.G. 6A U.S. Patent Sep. 1, 1992 Sheet 6 of 8 5,144,551 1150 ENABLE WRITE TO ROM 1220 1160 PONT DS:S TO SET ES REGISTER 28S CACHE TO CODE SEGMENT DESCRIPTOR 1170 1230 SET ES:D INCREMENT DI TO 386 LOADALL TO POINT TO 286 CACHE EMULATION BUFFER 1240 1 18O TRANSFER LIMIT, SET DS: O TO BASE FROM 286 286 LOADALL LOADALL BUFFER BUFFER TO DS GDTR 1250 1190. CLEAR DIRECTION SET DS DESCRIPTOR FLAGS; SET CACHE PRIVLEGE LEVEL = 3 N GNORE - INTERRUPT 386 LOADALL EMULATION BUFFER 12OO RETRIEVE DS SELECTOR FROM 286 LOADALL BUFFER 1270 RETRIEVE ES SELECTOR DESCRIPTOR = SPECIAL FLAG CACHE SELECTOR FROM 286 LOADALL BUFFER SELECTOR SPECIAL FLAG U.S. Patent Sep. 1, 1992 Sheet 7 of 8 5,144,551 POINT DS:S TO 286 ES CACHE DESCRIPTOR 14OO ES:D LOAD LOCAL DESCRIPTOR TABLE FROM LOADALL TRANSFER LIMIT EMULATION BUFFER AND BASE FROM ES 286 LOADAL 1410 BUFFER RETREVE ES SELECTOR FROM 286 SET ES DESCRIPTOR LOADALL BUFFER CACHE PRIV = 3 SELECTOR RETREVE FLAG 1 DS SELECTOR (INVALID) 1350 SELECTOR REPLACE WITH FLAG = 1 SPECIAL FLAG REPLACE WITH (INVALID)p (VALID SELECTOR) SEAL 1350 STORE SELECTOR N D 136O VALID LOAD KNOWN SELECTOR NVALID SELECTOR VALUE NTO VALUE D REGISTER 1380 RETRIEVE DS DESCRIPTOR, CALCUATE PHYS. ADDRESS AND DS DESC. BASE F.G. 6C U.S. Patent Sep. 1, 1992 Sheet 8 of 8 5,144,551 1530 LOAD DTR SAVE ES SELECTOR WITH NEW N S REGISTER ES SELECTOR - 1540 LOAD DS GLOBAL DESCRIPTOR TABLE VALID LOAD KNOWN SELECTOR REGISTERS FROM SELECTOR VALUE VALUE INTO S DS LOADALL EMULATION BUFFER 1550 CLEAR DS SELECTOR RETRIEVE ES DESCRIPTOR, REQUESTED CALCULATE PHYS. PRIVLEGE LEVEL ADDRESS AND DS DESC BASE 1560 LOAD LOTR WITH NEW LOAD LOCAL DS SELECTOR DESCRIPTOR TABLE FROM LOADALL 1570 EMULATION BUFFER RETURN TO REAL MODE SWITCH TO 158O PROTECTED MODE LOAD REMAINING REGISTERS FROM 286 LOADALL LOAD ES GLOBAL BUFFER DESCRIPTOR TABLE REGISTERS FROM 1590 ES 386 LOADALL EMULATION BUFFER CLEAR ES SELECTOR RECQUESTED PRIVILEGE LEVEL F.G. 6D 5,144,551 1 2 Realizing this limitation, Intel introduced with the COMPUTER MEMORY MANAGEMENT 80386 a mode known as 8086 virtual mode. The virtual METHOD UTILIZING SEGMENTATION AND mode supports the memory management and tech PROTECTION TECHNIOUES niques normally utilized by the 80386 and permits 8086 5 virtual tasks to operate as part of a multi-tasking system. This is a continuation of copending application Ser. Thus, the 80386 is capable of running multiple 8086 No. 07/354,144 filed on May 19, 1989 now abandoned. virtual tasks accessing memory addresses in excess of the 1 Mbyte real limit, as well as protected mode 80286 BACKGROUND OF THE INVENTION and 80386 tasks, 1. Field of the Invention 10 However, it will be appreciated that during this evo The present invention relates to memory manage lution of the Intel microprocessor family that a number ment of a computer system utilizing Intel Corporation of instructions written specifically for the 8086 and microprocessors. 80286 were necessarily supported in the 80386. The 2. Description of the Prior Art reason for supporting these machine specific instruc Many of the personal computers used today are based 15 tions is that operating systems or applications programs on the Intel Corporation's family of microprocessors, utilized these special commands as opposed to focusing including the 8088, 8088-2, 8086, 80186 (hereinafter on using the common core of commands. referred to collectively as the 8086), 80286 and 80386. It One of these commands is an undocumented instruc has been Intel's practice to maintain downward compat tion known as the LOADALL command. The LOA ibility throughout its line of microprocessors, such that 20 DALL command is designed to load all of the segment programs designed to run on the 8086 may generally selector registers and segment descriptor caches from run on the 80386 microprocessor. This is accomplished values stored in memory at physical address 800h by maintaining a consistent core of microprocessor (where the h suffix indicates hexadecimal notation). It instructions throughout the family. However, the was designed to be used primarily for Intel testing pur newer microprocessors, the 80286 and 80386, have ex 25 poses. However, its ability to rapidly load all registers panded sets of instructions. The 80286 instruction set is and descriptor caches with a single command resulted a superset of the 8086 instruction set. Similarly, the in its use by operating systems and several applications 80386 instruction set is a superset of the 80286 instruc programs. tion set. In 1988, Intel announced that it was discontinuing However, this compatibility is not without its price. 30 support for the 80386 LOADALL instruction and was The 8086 microprocessor has several limitations. First, going to remove it from the 80386 instruction set. This the 8086 does not support multi-tasking operations. 80386 instruction was used to emulate the 80286 LOA Multi-tasking refers to a computer's ability to run more DALL instruction. Like the 80286 LOADALL instruc than one application at a single time or to run back tion the 386 LOADALL was undocumented.
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