Ultimate CMOS Scaling

nano-KISS 2013 July 3, 2013, Daejon, Korea

Ultimate CMOS scaling

Hiroshi Iwai Frontier Research Center Tokyo Institute of Technology

1 1. Back ground for nano-electronics

2 1900 “Electronics” started. Device: Vacuum tube Device feature size: 10 cm Major Appl.: Amplifier (Radio, TV, Wireless etc.)

Technology Revolution

1970 “Micro-Electronics” started. Device: Si MOS integrated circuits Device feature size: 10 µm Major Appl.: Digital (Computer, PC, etc.)

Technology Revolution

3 2000 “Nano-Electronics” started. Device: Still, Si CMOS integrated circuits Device feature size: 100 nm Major Appl.: Digital (µ-processor, cell phone, etc.)

Technology Revolution?? Maybe, just evolution or innovation!

But very important so many innovations!

4 Now, 2013 “Nano-Electronics” continued. Device: Still, Si CMOS integrated circuits Device feature size: near 10 nm Major Appl.: Still Digital (µ-processor, cell phone, etc.)

Still evolution and innovation.. But, so many important emerging applications for smart society.

5 Questions for future

Future, “Nano-Electronics” still continued? Device: Still, Si CMOS integrated circuits? Device feature size: ? nm, what is the limit?

Application: New application?

Any Technology Revolution?

6 What is special or new for Nano-Electronics?

In 1990’s, people expected completely new mechanism or operational principle due the nano size, like quantum mechanical effects.

However, no fancy new operational principle was found.

At least for logic application, there is no success story for “Beyond CMOS devices” to replace Si-CMOS.

Of course, I do not deny the importance of Beyond CMOS technology development. It is becoming very important as CMOS approach its limit.

7 Ballistic conduction will not happen Ballistic transport will never even decreasing channel lengh. happen for MOSFET because L of back scattering at drain source drain λ ：Mean free path L >> λ Diffusive transport With decreasing channel length, L ~ λ Drain current increase continue. Quasi-Ballistic R transport M L < λ Ballistic transport Back scattering from drain

Also, 1D quantum conduction, or ballistic conduction will not happen. 8 (1D quantum conduction: 77.8µS regardless of the length and material). 2. Importance of nano-electronics as integrated circuits

9 First Computer Eniac: made of huge number of vacuum tubes 1946 Big size, huge power, short life time filament  dreamed of replacing vacuum tube with solid-state device

Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption

10 1960: First MOSFET by D. Kahng and M. Atalla Top View

SiO2

Si/SiO2 Interface is extraordinarily good

11 1970,71: 1st generation of LSIs

DRAM Intel 1103 MPU Intel 4004

12 In 2012 Most Recent SD Card

128GB (Bite) = 128G X 8bit = 1T(Tera)bit

1T = 1012 = １Trillion

World Population：7 Billion Brain Cell：10～100 Billion Stars in Galaxy：100 Billion 13 128 GB = 1Tbit 2.4cm X 3.2cm X 0.21cm

Volume：1. 6cm³ Weight：2g

Voltage：2.7 - 3.6V

Old Vacuum Tube： 5cm X 5cm X 10cm, 100g, 50W

What are volume, weight, power consumption for 1Tbit

Old Vacuum Tube： 1Tbit = 10,000 X 10,000 X 10,000 bit 5cm X 5cm X 10cm Volume = (5cm X 10,000) X (5cm X 10,000) X (10cm X 10,000) = 0.5km X 0.5km X 1km

Burji Khalifa 500 m Dubai, UAE Pingan Intenational Indian Tower (Year 2010) Finance Center Mumbai, India Shanghai, China (Year 2016) (Year 2016) 1,000 m 828 m 700 m 700 m

1Tbit

15 Old Vacuum Tube： 1Tbit = 1012bit 100W Power = 0.05kWX1012=50 TW Nuclear Power Generator 1MkW=1BW We need 50,000 Nuclear Power Plant for just one 128 GB memory

In Japan we have only 54 Nuclear Power Generator

Last summer Tokyo Electric Power Company (TEPCO) can supply only 55BW.

We need 1000 TEPCO just one 128 GB memory Imagine how many memories are used in the world! 16 So progress of integrated circuits is extremely important for power saving

17 Brain: Integrated Circuits Ear, Eye：Sensor Mouth：RF/Opto device

Stomach：PV device

Hands, Legs：Power device

18 Near future smart-society has to treat huge data. Demand to high-performance and low power CMOS become much more stronger.

19 Semiconductor Device Market will grow 5 times in 12 years, even though, it is very matured market!!

2011 2015

300B USD 1,500B USD

Gartner: By K. Kim, CSTIC 2012 20 2. Current status of Si-CMOS device technologies

21 Downsizing Important for Decreasing cost, power Increasing performance

22 Feature Size / Technology Node

(1970) 10 μm  8 μm  6 μm  4 μm  3 μm  2 μm  1.2 μm

0.8 μm  0.5 μm  0.35 μm  0.25 μm  180 nm  130 nm 

90 nm  65 nm  45 nm  32 nm  22 nm (2012)

From 1970 to 2013 (This year)

43 years 1 generation 18 generations 2.5 years Line width: 1/450 Line width: 1/1.43 = 0.70 Area: 1/200,000 Area: 1/2 = 0.5 23 Problem for downsizing Region governed Region governed DL touch with S by gate bias 0V By drain bias Region (DL) 0V Gate metal V Large IOFF dd 0V Gate oxide 1V 0V 1V Source Drain No tox 0V thinning ＜＜ 0V < Vdep 1V 0V < Vdep 1V Channel Large IOFF 0V 0V Substrate 0V V Depletion 0V dd Region (DL) 0.5V 0V

tox and Vdd have to be decreased for better  channel potential control IOFF Suppression 24 Lgate and tox(EOT) scaling trend A. Toriumi (Tokyo Univ), IEDM 2006, Short Course (

(

ox t

25 Our Work at TIT: High-k

EOT=0.40nm 1.0 L/W = 5/20µm Vg= 1.0V /Vsec] T = 300K 2 0.8 × 16 -3 Vg= 0.8V Nsub = 3 10 cm

0.6 EOT = 0.40nm Vg= 0.6V L/W = 5/20µm

0.4 T = 300K Vg= 0.4V × 16 -3 Drain Current (mA) Nsub = 3 10 cm Electron Mobility [cm 0.2 Vg= 0.2V Vg= 0 V 0 0.2 0.4 0.6 0.8 1.0 Eeff [MV/cm] Drain Voltage (V)

26 What would be the limit of downsizing! 3 nm

Tunneling distance

Channel Source Drain

27 Subtheshold leakage current of MOSFET

Id Subthreshold Current Ion Is OK at Single Tr. level

OFF ON But not OK For Billions of Trs. Subthreshould Leakage Current Ioff Vg Vg=0V

Subthreshold Vth region (Threshold Voltage) 28 Subthreshold leakage current will limit the downsizing

Id (A/µm)

Ion Electron Energy 10-5 Boltzmann statics Exp (-qV/kT) Vd 10-7 0.5 V 1.0 V

10-9 Vth Ioff 0.15 V 0.3 V

10-11

0 0.5 1 Vg (V)

29 The limit is deferent depending on application 100 e)

1 Operation Frequency OperationFrequency (a.u.)

Subthreshold Leakage (A/µm) 30 Source: 2007 ITRS Winter Public Conf. How far can we go for production?

Past 0.7 times per 2.5 years In 43 years: 18 generations, Size 1/450, Area 1/200,000 1970年 10µm  8µm  6µm  4µm  3µm  2µm  1.2µm  0.8µm  0.5µm  0.35µm  0.25µm  180nm  130nm  90nm  65nm  45nm  32nm

Now Future  22nm  16nm  11.5 nm  8nm  5.5nm?  4nm?  2.9 nm?

・At least 4,5 generations to 8 ~ 5 nm

31 Suppression of subthreshold leakage by surrounding gate structure

0V 0V

G 0V 0V G 1V 1V

S S 0V D

0V ＜V＜1V G 0V

Planar Surrounding gate

32 Because of off-leakage control, 0V S Planar  Ｆｉｎ Nanowire 0V G G 0V 1 0V 1V

S D D Wdep

Leakage current

Gate Source Drain

Planar FET Fin FET Nanowire FET33 Nanowire structures in a wide meaning

G G G G

Fin Tri-gate Ω-gate All-around

34 Our work at TIT: Ω-gate Si Nanowire

S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.) Lg=65nm 101.E-03-3 1.E-04-4 Vd=-1V Vd=1V Poly-Si 10 SiO 2 12 nm 101.E-05-5 NW 1.E-06-6 10 Vd=50mV Vd=-50mV 101.E-07-7 SiN SiN pFET nFET 19 nm 101.E-08-8 SiO2 101.E-09-9 101.E-10-10 1.E-11 Drain Current (A) 10-11 101.E-12-12 -1.5 -1.0 -0.5 0.0 0.5 1.0 Gate Voltage (V) ・Conventional CMOS process ・High drive current

(1.32 mA/µm @ IOFF=117 nA/µm) Lg=65nm 0 0.5 1 1.5 2 ・DIBL of 62mV/V and SS of 70mV/dec µ 35 ION (mA/ m) for nFET More Moore to More More Moore Technology node Now Future

65nm 45nm 32nm 22nm 15nm, 11nm, 8nm, 5nm, 3nm

Lg 35nm Lg 30nm

Main stream (Fin,Tri, Nanowire)

Planar Tri-Gate Alternative Si channel Si (ETSOI) ET: Extremely Thin Si is still main stream for future !!

M. Bohr, pp.1, IEDM2011 (Intel) Alternative (III-V/Ge) P. Packan, pp.659, IEDM2009 (Intel) Channel FinFET C. Auth et al., pp.131, VLSI2012 (Intel) Others T. B. Hook, pp.115, IEDM2011 (IBM) Emerging 36 S. Bangsaruntip et al., pp.297, IEDM2009 (IBM) Devices High-k gate dielectrics Hf-based oxides

45nm 32nm 22nm 15nm, 11nm, 8nm, 5nm, 3nm, EOT:1nm EOT:0.95nm EOT:0.9nm

SiO2 IL (Interfacial Layer) is used at Si interface to Technology for direct contact of realize good mobility high-k and Si is necessary TiN EOT=0.52 nm

Remote SiO2-IL EOT=0.9nm HfO2 scavenging SiO2 HfO2/SiO2 HfO2 (IBM) (IBM) Si EOT=0.37nm EOT=0.40nm EOT=0.48nm Continued research MG and development La-silicate K. Mistry, et al., p.247, IEDM 2007, (Intel) T.C. Chen, et al., p.8, VLSI 2009, (IBM) T. Ando, et al., p.423, IEDM2009, (IBM) T. Kawanago, et al., T-ED, vol. 59, no. Si 0.48 → 0.37nm Increase of Id at 30% 2, p. 269, 2012 (Tokyo Tech.) K. Kakushima, et al., p.8, IWDTF 2008, Direct contact with La-silicate (Tokyo.Tech)37 (Tokyo Tech.) ION and IOFF benchmark NMOS Supply voltage affects very much! PMOS 10000 10000 Intel [1] Intel [1] Intel [2] Intel [1] Intel [2] Intel [1] Bulk 32nm Tri-Gate 22nm Bulk 45nm Bulk 32nm Bulk 45nm Tri-Gate 22nm VDD=0.8V VDD=1V VDD=0.8V VDD=0.8V VDD=1V VDD=0.8V Samsung [3] 1000 Bulk 20nm 1000 IBM [10] IBM [7] ETSOI ETSOI

V =0.9V DD Tokyo Tech. [9] VDD=0.9V VDD=0.9V IBM [7]

m] Ω IBM [10] -gate NW m] Ieff ETSOI µ ETSOI VDD=1V µ V =1V Samsung [3] DD VDD=0.9V IBM [7] Bulk 20nm [nA/ 100 Ieff [nA/ 100

ETSOI Toshiba [4] VDD=0.9V IBM [7] VDD=1V OFF OFF

I Tri-Gate NW ETSOI I VDD=1V V =0.9V IBM [6] DD IBM [6] FinFET 25nm 10 10 FinFET 25nm VDD=1V STMicro. [8] V =1V DD STMicro. [8] STMicro. [8] GAA NW IBM [5] GAA NW GAA NW VDD=1.1V IBM [5] GAA NW VDD=1.1V VDD=0.9V GAA NW VDD=1V VDD=1V 1 1 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ION [mA/µm] ION [mA/µm]

[1] C. Auth et al., pp.131, VLSI2012 (Intel). [6] T. Yamashita et al., pp.14, VLSI2011 (IBM). [2] K. Mistry et al., pp.247, IEDM2007 (Intel). [7] A. Khakifirooz et al., pp.117, VLSI2012 (IBM). [3] H.-J. Cho et al., pp.350, IEDM2011 (Samsung). [8] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics). 38 [4] S. Saitoh et al., pp.11, VLSI2012 (Toshiba). [9] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.) [5] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM). [10] K. Cheng et al., pp.419, IEDM2012 (IBM) Benchmark of device characteristics

Intel Intel Toshiba IBM Samsung IBM STMicro. Tokyo Tech (IEDM2007, 2009) (VLSI2012) (VLSI2012) (IEDM2012) (IEDM2012) (IEDM2009) (VLSI2008) (ESSDERC2010)

Bulk Planar Tri-Gate Structure Tri-Gate NW ETSOI Bulk Planar GAA NW GAA NW Ω-gate NW 45nm 32nm 22nm

35/25 22/30 L (nm) 35 30 30 14 22 20 65 g (nFET/pFET) (nFET/pFET)

Gate Hf-based Hf-based SiO HfO HfO ? Hf-based HfZrO SiO Dielectrics 2 2 2 2 2

EOT (nm) 1 0.95 0.9 3 ~1 - 1.5 - 3

Vth (V) ~0.4 ~0.3 ~0.2 -0.15 (nFET) 0.3~0.4 ~0.3 0.3~0.4 ~0.5 -0.2 (nFET)

VDD (V) 1 1 0.8 1 0.9 0.9 1 1.1 1

I (mA/um) ON 1.36/1.07 1.53/1.23 1.26/1.1 0.83 (nFET) 0.59/0.62 (I ) 1.2/1.05 0.83/0.95 2.05/1.5 1.32 (nFET) nFET/pFET eff

DIBL (mV/V) ~150 ~200 46/50 <50 - 104/115 65/105 56/9 62 nFET/pFET

SS - ~100 ~70 <80 - 87 85 <80 70 (mV/dec)

39 Ω-gate Si Nanowire

(1.32 mA/µm @ IOFF=117 nA/µm) Lg=65nm 0 0.5 1 1.5 2 ・DIBL of 62mV/V and SS of 70mV/dec µ 40 ION (mA/ m) for nFET 41 Electron Density 電子濃度(x1019cm-3) 6 角の部分 5 Edge portion 4 3 平らな部分Flat portion 2 1 0

Distance from SiNW Surface (nm)

42 Tri-gate implementation for transistors C. Auth et al., pp.131, VLSI2012 (Intel)

HP MP SP Tri-gate has been implemented TOX,E (nm) 0.9 0.9 0.9 since 22nm node, enabling

LGATE (nm) 30 34 34 further scaling

43 IOFF (nA/um) 20-100 5-20 1-5 Comparison with ITRS

40 2 1.4 1.4 45nm ITRS2007~2011 ITRS2007~2011 35 Intel 1.8 VDD 32nm 1.2 1.2 22nm 30 1.6 Lg 1 1 EOT (nm)

25 Bulk Planar 1.4 45nm 32nm V 0.8 0.8 th (V)

20 1.2 Intel (V)

(nm) 22nm

Multi-Gate DD

g 0.6 0.6 V L 22nm 15 1 45nm Intel Bulk Planar Multi-Gate 0.4 32nm 0.4 10 45nm 32nm 0.8 Intel 5 0.6 0.2 0.2 EOT Vth 22nm 0 0.4 0 0 2006 2008 2010 2012 2014 2016 2018 2020 2006 2008 2010 2012 2014 2016 2018 2020 Year Year

・Lg and EOT are larger than ITRS requirements

・Implementation of Tri-gate and lower Vth/Vdd since 22nm

K. Mistry et al., pp.247, IEDM2007 (Intel). 44 P. Packan et al., pp.659, IEDM2009 (Intel). C. Auth et al., pp.131, VLSI2012 (Intel). Tri-gate width/height optimization C. Auth et al., pp.131, VLSI2012 (Intel) Intel’s fin is triangle shape!

PMOS channel S/D region showing under the gate the SiGe epitaxy

A fin width of 8nm to balance SCE and Rext A fin height of 34nm to balance drive current vs. capacitance 45 Tri-gate Id-Vg characteristics and Vth C.-H. Jan et al ., pp.44, IEDM2012 (Intel) Very good Vth control!

・SS of 71 and 72 mV/dec for HP NMOS and PMOS, respectively ・DIBL of 30 and 35 mV/V for NMOS and PMOS, respectively ・ Vth of 22 nm is about 0.1 ~0.2 V lower than that of 32nm 46 Extremely Thin SOI (ETSOI) K. Cheng et al., pp.419, IEDM2012 (IBM) Also, ET-SOI works very good! ・Hybrid CMOS Si Channel nFET Strained SiGe Channel pFET ・RO delay improvement over FinFET with FO = 2

47 Gate All Around Nanowire (GAA NW) S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)

・Lg = 25~35nm GAA NW ・Hydrogen anneal provide smooth channel surface ・Competitive with conventional CMOS technologies ・Scaling the dimensions of NW leads to suppressed SCE 48 3. Problems

49 Short-channel effect T. Skotnicki, IEDM 2009 Short Course (STMicroelectronics)

50 Drain-induced barrier lowering T. Skotnicki, IEDM 2010 Short Course (STMicroelectronics)

51 Sub-threshold Slope T. Skotnicki, IEDM 2010 Short Course (STMicroelectronics)

95 mV/dec

110 mV/dec

85 mV/dec

75 mV/dec

65 mV/dec 52 Problems in Multi-gate S. Bangsaruntip et al., pp.297, IEDM2009 (IBM), K. Tachi et al., pp.313, IEDM2009 (CEA-LETI) µ Need to decrease Significant degradation diameter for SCH at diameter < 10 nm

Decreasing the diameter of NW Improved Severe mobility

short-channel control degradation 53 Impact of Si thickness in FinFET J. B. Chang et al., pp.12, VLSI2012 (IBM)

・Replacement Gate process

・TaN/HfO2 gate stack

・Reduced gm and higher Vth with decreasing Fin width 54 Problems in SOI K. Uchida et al., pp.47, IEDM2002 (Toshiba)

Mobility is also decreased with decreasing the Si thickness of SOI

transistor similar to the NW transistor. 55 Problem for nanowire When wire diameter becomes less than 10 nm, sudden drop of Id

Id Diameter 1. Electron Scattering of every surface 10 nm 2. Decrease of DOS If diameter cannot be scaled, SCE cannot be suppressed. Then, again aggressive EOT scaling of 56 high-k is necessary. Increase the Number of quantum channels

By Prof. Shiraishi of Tsukuba univ.

4 channels can be used

Energy band of Bulk Si

Energy band of 3 x 3 Si wire

57 Diameter dependence

By Profs. Oshiyama and Iwata, U. of Tokyo 58 Wire cross section dependence. What cross section gives best solution for SCE suppression and drive current?.

By Profs. Oshiyama and Iwata, U. of Tokyo 59 Vth variability J. B. Chang et al., pp.12, VLSI2012 (IBM)

nFETs pFETs

Significant increase in Vth variability with decreasing Fin width

60 EOT Scaling Trends K. Kim, pp.1, IEDM2010 (Samsung)

ITRS2011

Fin width

Multi- Gate Planar

Smaller wire/fin width is necessary for SCE suppression

But mobility and ION severely degrade with wire/fin width reduction

Therefore even in multi-gate structures, EOT scaling should be accelerated to provide SCE immunity 61 High-k beyond 0.5 nm

62 Limit in tox thinning Gate oxide should be thicker than mono atomic layer 0.8 nm gate oxide thickness MOSFETs operate 0.8 nm  Distance of 3 Si atoms  2 mono layers

R.Chau, et al., (Intel) IWGI 2003

63 Limit in tox thinning W.F.Clark, (IBM) VLSI 2007 Short Course R.Chau, et al., (Intel) IWGI 2003

1000 ] 2 100 Active Power

1 Passive Power

0.1 Gate Leakage 0.01 Power Density [W/cm

0.001 1 0.1 0.01 Gate Length [µm]

Gate Leakage Power Density becomes significantly large with Lg reduction, and thus, with tox thinning!! 64 Solution To use high-k dielectrics K: Dielectric Constant Thick high-k

Thin SiO2 dielectrics 5 times thicker SiO2 High-k

K=4 Small Almost the same K=20 leakage electric characteristics Current

65 However, very difficult and big challenge! Equivalent Oxide Thickness (EOT) Combination of high-k and metal gate is important K. Natori, et al., (Tsukuba Univ) SSDM 2005, p.286

Metal 20 -3 Poly-Si(10 cm ) Poly-Si CMetal Cmetal (EOT: 0.1 nm) C Poly Depletion High-k (EOT: 0.3 nm) COX SiO2 COX C C S Si D S Si D

Silicon Substrate Silicon Substrate

Equivalent Oxide Thickness (EOT): gate dielectrics itself, C Capacitance Equivalent Thicknessox (CET): entire gate

stack, Cmetal is finite because of quantum effect. In other words Metal gate can eliminate the poly-Si depletion.electron is not a point charge Inversion CET = Tinv ≈ EOT + 0.4nm located at the interface but 66 with metal gate electrode distributed charge. Choice of High-k elements for oxide

● Gas or liquid Candidates HfO2 based dielectrics at 1000 K are selected as the ● Unstable at Si interface ○ Radio active ● first generation H He materials, because of ① Si + MO M + SiO X 2 ● ● ● ● ● ● their merit in Li Be ② Si + MOX MSiX + SiO2 B C N O F Ne 1) band-offset, 2) dielectric constant ① ③ ● ● ● ● Si + MOX M + MSi X OY 3) thermal stability Na Mg Al Si P S Cl Ar ② ① ① ① ① ① ① ① ① ① ① ● ● ● ● K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr

● ① ① ① ① ① ● ① ① ① ① ① ● ● La2O3 based Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe dielectrics are ● ③ ★ Hf ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○ thought to be the next Cs Ba Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn generation materials, ○ ○ ○ ○ ○ ○ ○ ○ ☆ which may not need a Fr Ra Rf Ha Sg Ns Hs Mt thicker interfacial ○ layer ★ La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yｂ Lu ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ☆ Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr R. Hauser, IEDM Short Course, 1999 Hubbard and Schlom, J Mater Res 11 2757 (1996) 67

Issues in high-k/metal gate stack

Oxygen concentration control Suppression of gate Reliability: PBTI, for prevention of EOT increase leakage current NBTI, TDDB and oxygen vacancy Endurance for high formation in high-k temperature process Oxygen diffusion control for Flat metal/high-k O prevention of EOT increase interface for better and oxygen vacancy mobility formation in high-k

Suppression of Workfunction engineering for Metal metal diffusion Vth control

Suppression of Suppression of FLP oxygen vacancy formation High-k Interface dipole control for Vth tuning Small interfacial state density at high-k/Si SiO2-IL Remove contamination introduced by CVD

Control of interface reaction Si-sub. and Si diffusion to high-k Thinning or removal of 68 SiO2-IL for small EOT Conduction band offset vs. Dielectric Constant Leakage Current by Tunneling

Oxide ] SiO2 V 4 e [ Band y t offset i 2 Si u n i

t 0 n o

c -2 s i D

-4 d n

a -6 B 0 10 20 30 40 50 Dielectric Constant XPS measurement by Prof. T. Hattori, INFOS 2003

69 Direct high-k/Si by silicate reaction

HfO2 case La2O3 case Our approach

Low PO2 High PO2 Low PO2 High PO2 I IO O IO VO VO IO V La O IO V O 2 3 V HfO2 O O IO VO VO IO silicate La-rich Si-rich SiO2-IL LaSi HfSi x x (k~4) SiO2-IL Si substrate Si substrate (k~4)

SiO2 IL formation silicate formation

Si substrate Si substrate

Direct contact can be achieved with La2O3 by forming silicate at interface Control of oxygen partial pressusre is the key for processing. 70 K. Kakushima, et al., VLSI2010, p.69 SiOx-IL growth at HfO2/Si Interface TEM image500 oC 30min

) XPS Si1s spectrum W o a.u 500 C Hf Silicate SiO2 HfO2k=16 Si sub. SiOx-IL

Intensity ( 1846 1843 1840 1837 k=4 Binding energy (eV) 1 nm Phase separator

HfO2 + Si + O2 → HfO2 + Si + 2O*→HfO2+SiO2 H. Shimizu, JJAP, 44, pp. 6131 Oxygen supplied from W gate electrode D.J.Lichtenwalner, Tans. ECS 11, 319 SiOx-IL is formed after annealing 71 Oxygen control is required for optimizing the reaction La-Silicate Reaction at La2O3/Si Direct contact high-k/Si is possible XPS Si1s spectra TEM image 500 oC, 30 min

as depo. La-silicate

Si sub. W ) a.u 300 oC La2O3 k=23 La-silicate

Intensity ( k=8~14

500 oC 1 nm

1846 1840 1843 1837 La2O3 + Si + nO2 Binding energy (eV) → La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc. 72 La2O3 can achieve direct contact of high-k/Si Cluster tool for HKMG Stack

EB Deposition for HK

Flash Lamp

Sputter for MG

Robot

ALD 5m Entrance RTA 5m 73 Cluster Chambers for HKMG Gate Stack EB Deposition: HK Flash Lamp Sputter: MG Anneal

ALD: HK

Robot Entrance RTA 74 75 76 SiO2 n+S n+DS p-Si 1cm 30 different Trs

L=0.5~100µm (8 kinds)

W=10, 20, 50, 100µm(4 kinds)

1cm 26 chips 26

77 1cm×1cm 15cm Chip

Metal Metal Metal Metal high-k Si Si Si Si

Shutter movement Thin Thick

3.5E-03 Vg=0V Vg=0V Vg=0V 3.0E-03 Vg=0.2V Vth=-0.06V Vg=0.2V Vth=-0.05V Vg=0.2V Vth=-0.04V Vg=0.4V Vg=0.4V Vg=0.4V 2.5E-03 Vg=0.6V Vg=0.6V Vg=0.6V Vg=0.8V Vg=0.8V Vg=0.8V (V) 2.0E-03 Vg=1.0V Vg=1.0V Vg=1.0V

d Vg=1.2V Vg=1.2V Vg=1.2V I 1.5E-03

1.0E-03

5.0E-04

0.0E+00 0 0.2 0.4 0.6 0.8 10 0.2 0.4 0.6 0.8 10 0.2 0.4 0.6 0.8 1

78 Gate Leakage vs EOT, (Vg=|1|V) Al2O3 1.E+01 HfAlO(N) HfO2 HfO2 1.E+00 HfSiO(N) ) 2 HfTaO La2O3 1.E-01 La2O3 Nd2O3 Pr2O3 1.E-02 PrSiO PrTiO 1.E-03 SiON/SiN Sm2O3

Current density ( A/cm ( density Current SrTiO3 1.E-04 Ta2O5 TiO2 1.E-05 ZrO2(N) 0 0.5 1 1.5 2 2.5 3 ZrSiO ZrAlO(N) EOT ( nm ) 79 However, high-temperature anneal is necessary for the good interfacial property

FGA500oC 30min FGA700oC 30min FGA800oC 30min

A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC) 80 Physical mechanisms for small Dit

① silicate-reaction-formed ② stress relaxation at interface fresh interface by glass type structure of La silicate.

La atom metal metal La-O-Si bonding

La2O3 La-silicate Si Si SiO4 tetrahedron network Si sub. Si sub. Si sub.

Fresh interface with FGA800oC is necessary to silicate reaction reduce the interfacial stress

J. S. Jur, et al., Appl. Phys. Lett., S. D. Kosowsky, et al., Appl. Phys.81 Lett., Vol. 87, No. 10, (2007) p. 102908 Vol. 70, No. 23, (1997) pp. 3119 La2O3 W TiN/W Si/TiN/WMIPS MG

Si 2nm 2nm 2nm

Kav ~ 8 Kav ~ 12 Kav ~ 16

No interfacial layer can be confirmed with Si/TiN/W

82 La2O3/silicate/n-Si CV )

2 3 W/La2O3(4nm)/n-Si 600oC, 30min F/cm µ 2

1kHz 1 ∆ 1MHz Vfb

Cfb 0 -1.5 -1.0 -0.5 0.0 0.5 Capacitance density ( Gate voltage (V)

83 Dit, Dslow (FG anneal) 400℃ ) 14 Dslow 10 Dslow 500℃ /eV 2 - 1013 cm 600℃ ( 1012 slow Dit Dit , D it 1011 D as 200 400 600 800 1000 Annealing temperature (oC)

84 Slow trap state 10-11 ) 2 10-12 σit (cm 10-13 σslow slow σ 10-14 D ,

it  t  slow σ = σ − silicate Vg σ slow 0 exp  10-15  λ  (λ=0.8nm) Dit 0.0 E C f

La2O3 ) ∆Vfb=CLa2O3/qDslow

V -0.1 ( fb

n-Si V

∆ -0.2 La2O3 13 -2 Dslow=2.8x10 cm /eV silicate (tsilicate) -0.3 as 200 400 600 800 1000 Annealing temperature (oC) It is important to change the La2O3 to La-silicate completely 85 TiN(45nm)/W(6nm) 2.0 EOT=0.55nm Annealed for 2 s 4.5 1.8 La2O3(3.5 nm) Experiment 4 1.6 CvcTheory fitting W(60 nm) 3.5 1.4

) 3 2 TaN/(45nm)/W(3nm) 1.2 2.5 900oC, 30min 1.0 EOT (nm) 2 TiN/W(12 nm) EOT=0.55nm 0.8 1.5 Cg (uF/cm Cg 0.6 TiN/W(6 nm) 1 ～～ 0.5 0.4 As600 depo 700 800 900 1000 0 Annealing temperature (oC) -1 -0.5 0 0.5 Vg (V)

86 0.2 TaN(45nm)/W(3nm) 0.1

-0.1 × 11 -2 -0.2 Qfix=1 10 cm band voltage(V) band voltage(V)

- -0.3 900oC, 30min

Flat -0.4 0.5 0.55 0.6 0.65 0.7 EOT（nm) Fixed Charge density: 1×1011 cm-2

87 151cm2/Vs EOT=0.53nm Eeff=1MV/cm SiO2 2 S D 150cm /Vs 300 180 L/W = 20/20µm

Si-sub A) Vg= 1.0V 160 250 µ T = 300K

/Vsec] 140 × 16 -3 2 Nsub = 3 10 cm 200 Vg= 0.8V 120 EOT = 0.53nm 100 EOT = 0.53nm 150 Vg= 0.6V 80 L/W = 20/20µm 60 T = 300K 100 Vg= 0.4V 40 × 16 -3 Drain Current ( Drain Current Nsub = 3 10 cm

Si-sub 50 Vg= 0.2V 20 Electron Mobility [cm Vg= 0 V 熱処理 0 TaN/ W Al 0 0.2 0.4 0.6 0.8 1.0 0 0.5 1 1.5 2 La2O3 Drain Voltage (V) Eeff [MV/cm]

Si-sub

88 104

) ITRSの要求値 2 103 102 x1/100 101 100 10-1 10-2 TaN/W/LaSiOx/nFET 10-3 W /L =20/20µm -4 g g Gate current (A/cm current Gate 10 EOT=0.55nm 10-5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Gate voltage (V) 89 Recent results by my group. 300 L/W = 20/20µm 180

A) Vg= 1.0V 160 250 µ T = 300K

/Vsec] 140 × 16 -3 2 Nsub = 3 10 cm 200 Vg= 0.8V 120 EOT = 0.53nm 100 EOT = 0.53nm 150 Vg= 0.6V 80 L/W = 20/20µm 60 100 T = 300K Vg= 0.4V × 16 -3 Drain Current ( Drain Current 40 Nsub = 3 10 cm 50 Vg= 0.2V 20 Electron Mobility [cm Vg= 0 V 0 0 0.2 0.4 0.6 0.8 1.0 0 0.5 1 1.5 2

Drain Voltage (V) Eeff [MV/cm]

90 Benchmark of La-silicate dielectrics

T. Kawanago, et al., (Tokyo Tech.) T-ED, vol. L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng, 59, no. 2, p. 269, 2012 vol. 88, no. 7, pp. 1317–1322, Jul. 2011. T. Ando, et al., (IBM) IEDM 2009, p.423 1.E+04 300 ITRS requirement at 1 MV/cm 1.E+03 250

) 2 1.E+02 200 /Vsec) 2

1.E+01 150 at 1 V (A/cm

g 1.E+00 100 J Mobility (cm Mobility

1.E-01 50 Solid : La-silicate oxide Open : Hf-based oxides 1.E-02 0 0.3 0.4 0.5 0.6 0.7 0.8 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 EOT (nm) EOT (nm)

Gate leakage is one order Electron mobility is comparable of magnitude lower than to record mobility with Hf-based that of ITRS. oxides. 91 Si benchmark (nMOSFET)

Gate stack EOT Mobility Vth SS DIBL Ref.

110cm2/Vs ~0.4V IBM TiN/Cap/HfO2 0.52nm 13 -2 90mV/dec 147mV/V (at 1x10 cm ) (Lg=24nm) VLSI2011

140cm2/Vs IBM TiN/Cap/HfO 0.55nm 2 (at 1MV/cm) VLSI2009

115cm2/Vs 0.3V IMEC TiN/Cap/HfO2 0.45nm 13 -2 (at 1x10 cm ) (Lg=10um) MEE2011

130cm2/Vs 0.45V Sematech Metal/HfO2 0.59nm 75mV/dec (at 1MV/cm) (Lg=1um) VLSI2009

0.3~0.4V Samsung Metal/Hf-based 0.65nm 90mV/dec 100mV/V (Lg=~30nm) VLSI2011

~0.3V Intel Metal/Hf-based 0.95nm 100mV/dec ~200mV/V (Lg=30nm) IEDM2009

155cm2/Vs -0.08V Tokyo Tech. W/La-silicate 0.62nm ~70mV/dec (at 1MV/cm) (Lg=10um) T-ED2012 92 ALD of La2O3 K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr. the 16th Workshop on Gate Stack Technology and Physics., 2011, p.107.

Precursor C H C 3H 7 3 7 (ligand) N La C H La N

3 C3H7 La(iPrCp)3 La(FAMD)3

ligand H 1 cycle La O

substrate substrate substrate substrate

①La gas ②Ar purge ③H2O ④Ar purge feed feed ALD is indispensable from the manufacturing viewpoint 93 - precise control of film thickness and good uniformity Metal S/D Advantages of metal S/D L. Hutin, pp.45, IEDM2009 (CEA-LETI) - atomically abrupt junction - low parasitic resistance S Si D - reduced channel dopant concentration BOX Issues in metal S/D Dopant Segregation - two different φB for p/n-ch FETs layer - underlap/overlap to the gate - narrow process temperature window Metal S/D is considered for alternative channel material such as InGaAs and Ge

Ni is used both on InGaAs and Ge to form alloy. 94

S.-H. Kim, IEDM (2010) 596 K. Ikeda, VLSI (2012) 165 4. Alternative channel devices

95 Ge,III-V bulk properties

96 S. Takagi., IEDM2011, Short course (Tokyo Uni) Multi-gate III-V and Si benchmark 1.E-05 nMOS 1.E-05 pMOS InGaAs GAA Lch=50nm, Dielectric: 10nm Al2O3 GOI Tri-gate V =0.5V (Purdue Uni.) [1] DS Lg: 65nm. EOT 3.0nm Si-FinFET 22nm Si-FinFET 32nm VD=-1V (AIST Tsukuba)[6] Intel VDD=0.8V [10] 1.E-06 Intel VDD=0.8V [10] 1.E-06 InGaAs Tri-gate Ge FinFET

L =60 nm,EOT 12A g L =4.5 mm, Si-FinFET 32nm V =0.5V (Intel) [2] g DS Dielectric: SiON, V =-1V Intel VDD=0.8V [10]

m) DS Si-FinFET 22nm (Stanford Uni.)[7] µ InGaAs FinFET 1.E-07 Intel VDD=0.8V [10] 1.E-07 Lch=130nm

(A/ EOT 3.8nm Si-bulk 45nm VDS=0.5V (NUS)[3] Intel VDD=1V[11] Ge GAA Lg= 300nm, OFF

I InGaAs Nanowire dielectric: GeO2(7nm)-HfO2(10nm) Lg= 200nm, Tox 14.8nm VD= -0.8V (ASTAR Singapore)[8] 1.E-08 VDS=0.5V(Hokkaido Uni.)[4] 1.E-08 Metal S/D InGaAs-OI Lch= 55nm, EOT 3.5nm VDS=0.5V(Tokyo Uni.)[5] Ge Tri-gate Si-bulk 45nm L =183nm, EOT 5.5nm g Intel VDD=1V VD=-1V (NNDL Taiwan)[9] 1.E-09 1.E-09 0 0.4 0.8 1.2 0 0.4 0.8 1.2 ION (mA/µm) ION (mA/µm) [1] J. J. Gu et al., pp.769, IEDM2011 (Purdue). [6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba). [11] K. Mistry et al., pp.247, [2] M. Radosavljevic et al., pp.765, IEDM201(Intel). [7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni) IEDM2007 (Intel). [3] H. –C. Chin et al., EDL 32, 2 (2011) (NUS) [8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore) 97 [4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni). [9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan) [5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni) [10] C. Auth et al., pp.131, VLSI2012 (Intel). ION/IOFF Benchmark of Ge pMOSFET

98 III-V/Ge benchmark for various structures

Planar Gate-all-around FinFET Tri-gate Nanowire (metal S/D, Strain, Buffer…) MOSFET material InGaAs Ge InGaSn InGaAs Ge InGaAs Ge InGaAs Ge InGaAs Ge (multishell)

7.6 Ao 5.5 nm 10nm- Dieletric Al2O3/ 5nm ALD 5nm ALD HfO2: HfAlO 3.0 nm HfO + SiON 1.2 nm (Al O + ALD 2 2 3 (ALD Al O ) /EOT 3.5 nm Al2O3 Al2O3 11nm 14.8 nm 2 3 Al2O3+GeO2 GeO2) Al2O3

Ns: 5e12 ~600 e: 200 ~700 701 ~500 ~850 Mobility - 2 - - - - 2 (cm /Vs) h: 400 (µS/µm) (µS/µm) (µS/µm) (cm /Vs) (cm2/Vs)

W/L= L (nm) 55 50 µm 100 4.5 µm 60 183 50 200 200 65 ch 30/5 µm

DIBL 84 - - 180 - ~50 - 210 - - - (mV/V)

150K SS 61pMOS 105 - 145 750 90 130 150 160 - - (mV/dec) 33nMOS 120K

I 10 400 235 180 731 ON 278 3 4 (n,p) - 604 100 (µA/µm) (VD=0.5V) (VD=-0.2V) (VD=0.5V) (VD=0.5V) (VD=0.5V) (VD=-1V) (VD=0.5V) (VD=-0.5V) (VD=0.5V) (VD=-1V)

ASTAR Stanford Purdue Stanford Intel NNDL Purdue Hokkaido AIST Research Tokyo Uni Tokyo Uni Singapore Uni VLSI Uni IEDM Uni ELD IEDM Taiwan Uni IEDM Uni, IEDM 99Tsukuba Group VLSI 2012 VLSI 2012 IEDM 2012 2009 2007 2011 IEDM 2011 2011 2011 VLSI 2012 2009 InGaSb as channel material (stanford) Z. Yuan et al., pp.185, VLSI2012 (Stanford Uni)

Hole Mobility Electron Mobility InGaSb InGaSb

Si Si

AlGaSb creates barrier for both electrons and holes Achieving both N- and P-type MOSFET on a single channel is possible In-content of 20-40% improves perfomance electron/hole mobility > 4000/900cm2/Vs was gained in a single channel material µ µ ION at LG = 50 µm pMOS: 4 A/ m100 nMOS: 3.8 µA/µm Metal S/D InGaAs MOSFET (Tokyo Uni)

Metal S/D and InAs buffer layer are used as performance boosters. DIBL=84 mV/V and SS=105 mV/V was

shown for Lch = 55 nm when In-content was higher.

101 S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni) Common InGaAs-GeSn gate stack (NUS) X. Gong, et al. (National Uni of Singapore), VLSI2012, p.99.

～ VGS-VTH= 0 2.0V Common gate stack (gate metal and LG= 5µm dielectric) were used for both p- and n-type

Si2H6 plasma passivation is employed which creates Si layer at interface. SS: nMOS: 90 (mV/decade) pMOS: 190 (mV/decade)

High intrinsic peak GM,Sat=of ~465 μS/μm at VDS=-1.1 V was achieved102 for LG=250 nm. InGaAs nanowire transistor(Hokkaido Uni)

T. Fukui, et al. (Hokkaido Univ), IEDM2011, p.773.

Core-multishell InGaAs nanowires grown without buffer layer on Si substrate (bottom up approach)

At Vd = 1 V peak transconductance of 500 mS/mm is achieved (roughly x3 InGaAs nanowire) 103 Tri-gate InGaAs QW-FET(Intel)

M. Radosavljevic, et al.(Intel), IEDM2011, p.765.

Tri-gate structure has superiority electrostatic controllability compared to ultra-thin body planar structure Steepest SS and smallest DIBL 104 ever reported (Wfin = 30nm) Gate all around InGaAs MOSFET(Purdue)

P. D. Ye, et al (Purdue Univ)., IEDM2011, Wfin= 50nm p.769.

Wfin= 30nm

Inversion mode In0.53Ga0.47As MOSFET with ALD Al2O3/WN with well electrostatic properties DIBL was suppressed down to

Lch = 50nm and

Gm,max =701mS/mm at Vds = 1V 105 InGaAs FinFET (NSU) H.C. Chin, et al. (National Uni of Singapore)., EDL2011,Vol.32 p.146.

LCH= 130nm

DIBL =135 mV/V and drive current

over 840 µA/µm at Lch = 130nm

and Vds = 1.5V was achieved 106 Ge-nanowire pMOSFET (AIST,Tsukuba) K. Ikeda, et al. (AIST, Tsukuba), VLSI2012, p.165.

Lg= 65nm Wwire= 20nm Using Ni-Ge alloy as metal S/D V = -1V D V -V = -2V g th Significantly reduces contact resistance VD= -0.5V

VD= High saturation current and high mobility -0.05V 2 12 -2 μeff = 855 cm /Vs at Ns =5x10 cm and saturation drain current of 107 731μA/μm at Vd = -1V Ge triangular pMOSFET (NNDL,Taiwan) S-H. Hsu, et al. (NNDL,Taiwan), IEDM2011, p. 825.

Lg>2Wfin Lg<2Wfin

Ge Rectangular Selective etching of high defect Ge near Ge/Si interface is used which improves gate controllability.

5 ION/IOFF = 10 and SS= 130 mV/dec Ge Triangular And ION= 235 µm/µm at VD= -1V

108 Implementing high-k material to III-V,Ge III-V (InGaAs, InAs,InGaSb,…) ALD-Al2O3 is most commonly used as gate dielectric in planar or Multi-gate

HfO2-only stacks have high Dit (combination of Al2O3 or Al or Si is used)

Al2O3 Si-HfO2 Al2O3+HfO2 HfAlOx TaSiOx

3.4 nm 1.2 nm

In0.7Ga0.3As In0.53Ga0.47As

NUS, VLSI 2012 L. Chu, et al.,APL99, 042908 Hokkaido Uni, IEDM 2011 Intel, IEDM 2010 E. Kim, et al., APL96, 012906 Ge By controlling the formation of GeOx at the interface, HfO2 and Al2O3 show good results. 109 R. Zhang et al., VLSI2012,p161 5. Emerging devices

110 Emerging devices(future scaling trends) Carbon-based FET J. P. Colinge et al., Nature Nano. 5(2010)225 Carbon nanotube Graphene Junctionless Transistor

L. Liao, et al., Nature ,Vol.467 p.305. A. D. Franklin et al., pp.525, IEDM2011 (IBM) GaAs mHEMT (20nm) SiMOSFET 1000 GaAs pHEMT (29nm) (100nm) All-spin logic device 100 CNT

Graphene 10 off frequency ( ( GHz) off frequency - J. P. Colinge et al., Nature Nano. 5(2010)266

Cut Input and output related via 10 100 1000 111 Gate length (nm) Spin-coherent channel F. Schwlerz, Nature Nano ,Vol.5 p.487. M. Lemme, Nanotech workshop ,2012 Tunnel FET A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)

Band to band tunneling

Low IOFF, Low VDD, SS<60mV/decade 112 TFET vs. MOSFET at low VDD A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)

VDD 0.3~0.35V TFET 8x faster at the same power “parameter variation is not a significant factor for differentiation between MOSFET and TFET” 113 Tunnel FET (Si) A. Villalon, pp.49, VLSI 2012 (CEA-LETI)

X in Si1-xGex is optimized to allow for efficient BTBT LG= 200nm 5 ION/IOFF~10

Reducing SiGe Body thickness improves Subthreshold swing. 130mV/dec

114 Gate Voltage (V) 190mV/dec Tunnel FET (III-V) K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University) SS=21mV/dec SS=110mV/dec

VDS=1V

HfAlOx Gate Conventional FET limit SS= 60 mV/dec

VDS= 1V

NW Diameter= 30nm

SS of TFET is function of VG due to Zener tunnel current Minimum SS= 21 mV/dec is reached due to optimized series resistance of contact, undoped InAs and InAs/Si 6 115 ION/IOFF~10 at VDS= 1.0V (ION= 1Aµ/µm) Device structure A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)

116 K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University) Tunnel FET performance comparison A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame) measured III-V channel TFETs

Most common SS which is Average SS: SMIN: the inverse of I -V slope D GS Ith at the steepest part D I VOFF=0 VTH=VDD/2 SEFF: Is the average swing when IOFF VTH=VDD/2 Effective SS: V =0 OFF Voff VTH 117 VGS ION and IOFF of TFETs [1] G. Zhou et al., pp. 782, vol. 33, no. 6, EDL 2012 (University of Notre Dame)

10000

Si MOSFET 1000 TFET Intel 100 VDS=0.75V m] Bulk 32nm µ V =0.8V TFET DD Intel Bulk 45nm [nA/ 10 VDS=1.05V VDD=1V OFF I 1 TFET VDS=1V Intel 0.1 Tri-Gate 22nm VDD=0.8V

0.01 0.01 0.1 1 10 ION [mA/µm]

C. Auth et al., pp.131, VLSI2012118 (Intel). K. Mistry et al., pp.247, IEDM2007 (Intel). MEMS relay

10 ION/IOFF of ~10

Ultra-low-power digital logic applications. state resistance [Ohm] -

ON Number of Operation Cycles Frequency of 1, 5, 25kHz under operation 119 T. K. Liu et al., pp. 43, VLSI2012 (UC Berkeley) Si Junctionless Transistor (Intel) R. Rios et al., EDL. 32(2011)1170 (Intel)

20 30 40 20 30 40 20 30 40 Lg (nm) Lg (nm) Lg (nm) IM : Conventional Inversion Mode JAM LD : Janctionless Accumulation Mode with low dope JAM HD : Janctionless Accumulation Mode with high dope JAM devices have reduced gate control and degraded short- channel characteristics relative to IM 120 Not suitable for high-performance logic (high Ion and moderate Ioff) Nanowire Junctionless Transistor J. P. Colinge et al., Nature Nano. 5(2010)225

Lg= 1µm

Wwire= 30nm

Lg= 1µm

Near-ideal subthreshold slope, close to 60 mV/dec at room temperature, and extremely low leakage currents Silicon nanowire is uniformly doped 6 Gate material is opposite ION/IOFF~1x10 (-1

SWCNT : single wall carbon nanotube GNR : graphene nano ribbon

Carbon materials for FET applications ・ an ultra-thin body for aggressive channel length scaling ・ excellent intrinsic transport properties similar to carbon nanotubes 122 ・ pattern the desired device structures Sub-10nm carbon nanotube transistor A. D. Franklin et al., pp.525, IEDM2011 (IBM)

Transistor operation with Lch of 9nm 123 Graphene Field-effect Transistor Z. Chen et al., pp.509, IEDM2008 (IBM) J. B. Oostinga et al., Nature Materials 7 (2008) 151

・Ambipolar Characteristics ・Bi-layer graphene and double gates can open the gap

124 2D material : single layer MoS2 H. Wang et al., pp.88, IEDM2012 (MIT)

・ 2 Mobility of 190 cm /Vsec Candidate : MoS2, MoSe2, 125 ・Ion of 1 µA/µm at VDD = 1V WS2, WSe2, MoTe2, WTe 2 Spin transfer Torque Switching MOSFET

T. Marukame et al., pp.215, IEDM2009 (Toshiba) Magnetic tunnel junction on S/D

Lg = 1µm

Read/write are enabled by using ferromagnetic electrodes and 126 Spin-polarized current Summary of Emerging Technology pro/cons

Advantage Issues

Lower V Integration TFET dd Lower IOFF higher ION

Higher transport velocity High density and CNT FET alignment, reproducibility, Lg scaling integration

RF application NOT a direct replacement Graphene FET Large area manufacturing for Silicon logic

Extremely low leakage Endurance MEMS Ultra-low digital logic Slow speed, scalability

CMOS process Worse gate control in Junctionless FET compatibility short-channel

Low power, suitable for Low efficiency of spin Spin FET memory (nonvolatile info injection 127 storage) Conclusions

128 Conclusions New device structures (FinFET, Tri-gate) are replacing conventional Planar CMOS Same performance at lower supply voltage

HKMG: Continuous innovation has enabled EOT scaling to 9 Ao, however, new material could be needed for further EOT scaling.

La-based high-k material

Recent advances in new channel material shows promising device performances but still far to cacth up Si-CMOS. The combination of III-V channel materials with a multi- gate structure appears to be a promising direction. (Higher performance in lower operating voltage) Device demonstration on emerging technologies (such as Tunnel FET, Junctionless FET, Carbon-based FET..) is increasing, But more time is needed for implementation of these technologies in future generation devices as mature technologies. 129