MGateE T R OProcess L O G Y Control

Pro fi ling the Gate and Improving Speed

J. Scott Hodges, Yu-Lun (Chris) Lin, Dale R. Burrows, and Ray H. Chiao, Incorporated Robert M. Peters, Srinivasan Rangarajan, Kamal Bhatia, and Suresh Lakkapragada, KLA-Tencor Corporation

Tighter control of gate profile parameters at 130 nm and below is the key to maximizing product yield and transistor per - formance. Furthermore, the ability to correlate physical inline profile measurements taken at gate patterning process steps to back end of line device parametric test results enables manufacturers to accurately screen out-of-spec product early in the process flow and minimize the cost per good die. Historical methods of inline metrology — low voltage scanning electron microscopy, atomic force microscopy, and electrical critical dimension metrology all face limitations with regards to precision, correlation, and throughput. Texas Instruments’ DMOS 6 300-mm fab utilized spectroscopic ellipsometry-based CD metrology for inline process control and product disposition at the gate lithography and etch process steps on 130 nm generation logic devices.

Introduction For the past several years, the predominant metrology The ability to control the cross-sectional methods used for inline control of the gate process have pro fi le of polysilicon gate struc t u r es on semi- been: 1) top-down measurement of the width (referred conductor devices is paramount to maximizing to as critical dimension, or CD) of the polysilicon gate product yield and transistor performance. using a low-voltage scanning electron microscope Tighter control of gate profile parameters (CD SEM); and 2) Electrical CD (ECD) measurements leads to a tighter distribution of tr a n s i s t o r conducted via a parametric test system immediately speeds, resulting in more optimized and con- after gate etch completion. Both methods have proven sistent device performance. The performa n c e to give precise measurement with relatively high of the transistor is only fully confirmed during throughput. However, both methods are limited in electrical testing after interconnect and metal- their ability to provide metrology or process character- lization have been completed. However, the ization beyond the one-dimensional CD value. process steps that define the physical dimen- sions of the polysilicon gate occur much earlier Other metrology techniques such as atomic force in the process flow. Typically, there is a lag microscopy (AFM) and cross-sectional tunneling time of days, or even weeks, between the el e c t r on microscopy (TEM) are able to provide full two- gate patterning steps, and electrical test of dimensional profile metrology with requisite precision the transistor performance. As a result, the for proper control of advanced gate patterning proc e s s e s . ability to accurately measure physical profile However, throughput for both techniques is inadequate characteristics of the gate inline at the pat- to allow for proper statistical sampling ne c e s s a r y to te r ning steps, and subsequently correlate co n t r ol a volume manufacturing line. TEM has the those measurements to back-end electrical additional drawback of being a destructive process. test results, is critical for ensuring prop e r disposition of prod u c t i o n material, in order This article describes the use of a CD metrology technique to maximize yield and minimize overall cost based on spectroscopic ellipsometry to provide fast, per good die. This importance is underscored accurate, and precise two-dimensional profi le informa t i o n by the significant increase in the number of on polysilicon gate struc t u r es. This metrology technique, chips on today’s 300-mm wafers. which is the basis of KLA-Ten c o r ’s SpectraCD™, is cur-

6 Summer 2003 Yield Management Solutions M E T R O L O G Y

ren t l y being utilized for inline process control and product disposition, at the gate lithography and etch process steps, on 130 nm generation logic devices manufactured in Texas Instruments’ DMOS6 300 mm wafer fabrication facility. A brief description of the SpectraCD measurement theory and measurement solution for both gate litho and etch will be provided. Precision results will be presented for CD, height, and profile sidewall angle that demonstrate the capability of SpectraCD to control a 130 nm node process. F i g u re 1. Schematic of spectroscopic ellipsometry-based CD (SpectraCD) measure m e n t .

Correlation results of inline gate etch line. The grating targets are comprised of line/space SpectraCD measurements, to post-metallization tran- features of uniform period, with the linewidth (CD) sistor drive current (IDr i v e ) will be shown. A comparison and period designed to represent the physical device between SpectraCD and existing inline electrical CD feature that is being controlled. measurements was completed, and the ability of SpectraCD to provide gate etch process control will be A typical SpectraCD measurement process consists of an demonstrated. offline library generation process, and an on-tool profile measurement using the library. The offline library By cou p l i n g ful l two-dimensional profi le information with generation involves using the process information high throughput, SpectraCD has also proven to be a (dispersion prop e r ties and nominal thickness of all film s valuable tool for detecting process excursions. Examples in the grating region) and the grating information of proc e s s excursions, ranging from etch profile changes (pitch, nominal CD, HT) to create a theoretical model to punch-through, have been detected by of the grating geometry. The library is a compilation Sp e c t r a C D . of theoretical spectral signatures, obtained by varying the grating parameters. This library is then linked to Spectroscopic ellipsometry based the recipe on the metrology tool. As the gratings are measurement technique measured, the experimental spectra are compared against the theoretical spectra in the library (Figure 2). The SpectraCD measurement technique based on spectro- The best match between the measured spectra and the scopic ellipsometry is described below. A typical setup theoretical spectra determines the parameter values for a spectroscopic ellipsometer is shown in Figure 1. that best describe the grating.1 Light from a broadband light source is reflected off the sample of interest. The polarizer and the analyzer determine the state of polarization of the incident and Measurement models the reflected beams respectively. A prism separates the A schematic representation of the measurement models wavelengths in the reflected light and the intensity is at both the gate litho and gate etch steps are shown in measured using an array detector. To conduct a typical Figures 3 and 4. For the gate litho process, the struc- ellipsometry measurement, the intensity of the ellip- tu r es of interest are resist lines/spaces — which sit on tically polarized light is measured for the wavelength to p of an anti-reflective coating layer — on top of range from 220 nm to 800 nm, at diffe r ent orientations blanket polysilicon, gate oxide, and bulk silicon of the polarizer or analyzer. Ellipsometry offers both (Figure 3). For gate etch, the struc t u r es of interest are amplitude and phase information, in relation to reflec- etched polysilicon lines/spaces on top of gate oxide, and tometry which only provides amplitude information. bulk silicon (Figure 4). In both cases, the lines in the grating structures were modeled as single trapezoids in Spectroscopic ellipsometry technique is widely used in the library. The library generation time for both the the for thin film metrology. In cases was less than half an hour. Cross-section TEM the SpectraCD technique the sample of interest is the analysis of representative gratings confirmed that the grating targets added to the wafer, usually in the scribe single simple trapezoid model closely approximates the

Summer 2003 Yield Management Solutions 7 M ETROLOGY

Poly-Si

Gate Ox

Silicon

Figure 4. Schematic of gate etch trapezoid model.

litho and etch layers, the wafers measured were pat- terned with a focus-exposure (FE) matrix encompassing a process window of ±20 percent from nominal. A total of 16 fields per wafer (see Figure 5), and two sites per field were measured. One site was a grating from a doped region of polysilicon; the other site was a grat- ing from an undoped region of polysilicon.

During the two-week period, a five-cycle short-term dynamic precision test was repeated six times for a total of 30 measurements at each site. The variance of each set of 30 measurements was calculated, and then the average variance for the 16 doped, 16 undoped, and the combined

Figure 2. SpectraCD measurement and library match. 32 sites were calculated. From these values, a pooled 3 sigma was calculated as three times the square root of actual resist and etched poly profiles. Gratings with the mean variance, for each of the profile parameters. line:pitch ratios varying between 1:3 and 1:7 were used to monitor the litho and etch processes. The aspect Results are shown in Figure 6 and Figure 7. For both ratios on the lines in the gratings are approximately the gate litho and gate etch processes, precision on 2.3:1 for gate litho, and approximately 1.6:1 for gate CD and height parameters is well below 0.5 nm, and etch.

Precision results

In this section we are going to present the long-term 1234 precision results generated by measuring the same wafers repeatedly over a two-week period. For both the - Exposure +

8765

Resist 9101112

ARC 16 15 14 13 Poly-Si Gate Ox Silicon - Focus +

Figure 3. Schematic of gate litho trapezoid model. Figure 5. Wafermap layout for long-term precision testing.

8 Summer 2003 Yield Management Solutions M E T R O L O G Y

F i g u re 6. Gate litho long-term precision results. F i g u re 7. Gate etch long-term precision re s u l t s . precision on sidewall angle is below 0.1 degree. These measure a test structure in the scribe that simulates the precision values generate precision-to-tolerance ratios actual device. While ECD has historically provided (P/T) well below 0.1, providing sufficient capability to good correlation to IDrive, at the 130 nm process node, control a 130 nm node process. some challenges have been encountered with maintaining this correlation. While ECD provides relatively high th r oughput compared to other metrology techniques, it SpectraCD correlation to drive current does face some limitations. Theref o r e, there is motivation One of the most important parameters for determining to find a viable metrology alternative that provides better device perfo r mance is the transistor drive current (IDr i v e ). correlation to IDrive, with higher throughput. IDrive cannot be measured until after metallization process steps have been completed. However, one of the Figures 8 and 9 show the results of a study comparing primary contributors to determining IDrive is the phys- the correlation of ECD and SpectraCD measurements ical gate length defined by the width of the polysilicon to IDrive. The limitations of the ECD measurement are line (Gate CD). Therefore, the ability to correlate a clearly seen. SpectraCD shows a much higher level of physical measurement of gate length measured inline at correlation to IDrive (0.67-0.68), for both minimum post-gate etch, to IDr i v e , is critical to provide meaningful contacted pitch (MCP) struc t u r es and isolated struc t u re s . process control and product disposition that will maxi- The slope and correlation of SpectraCD versus IDrive mize yield and minimize cost-per-good-die. demonstrate that IDrive can be controlled and modified through the use of inline SpectraCD measurements. Historically, electrical measurements of the gate CD have provided the best correlation to IDr i v e . The ECD Fi g u r es 10, 11, and 12 refl ect an actual production measurement is completed immediately after the gate ca s e , further demonstrating the capability of SpectraCD etch process step, using a parametric test system to to correlate and affect IDrive distribution. Figure 10

F i g u re 8. Correlation of electrical CD to ID r i v e. F i g u re 9. Correlation of SpectraCD BCD to ID r i v e.

Summer 2003 Yield Management Solutions 9 M E T R O L O G Y

F i g u re 10. Gate etch SpectraCD SPC chart . F i g u re 11. Gate etch ECD SPC Chart. is a pr oduction SPC chart for SpectraCD gate etch detection and response time for process excursions. me a s u r ements. A shift of roughly two percent in the CD distribution is seen to the right of the vertical line Sidewall angle and CD shift detected after etch on the chart. Figure 11 shows the corresponding ECD chamber PM SPC chart for the same production lots. No shift in CD One example is shown in Figure 13 below. After rou t i n e is picked up by ECD. Figure 12 is the corresponding preventative maintenance (PM) was performed on an chart showing IDrive distribution for the same group of etch chamber, SpectraCD SPC charts for both sidewall lots. The two percent shift in SpectraCD measurements angle and CD parameters refl ected a two percent shift in correlates to roughly a five percent shift in IDrive. the process means from the pre-PM baseline condition. Due to the high sampling rate afforded by SpectraCD, the excursion was reliably detected within a handful of Process excursion detection with product lots. TEM analysis confirmed the process shift SpectraCD seen by SpectraCD. Follow-up maintenance was perfo rm e d An additional benefit seen with the use of SpectraCD, is on the etch chamber to ret u r n the process to its baseline. its capability to detect a variety of process excursions. The ability to generate full two-dimensional profi le informa - Prior to SpectraCD implementation, this process excur- tion has provided additional sensitivity to process changes. sion would have almost certainly gone undetected for a The high throughput of SpectraCD (<4 seconds/site longer period of time. Figure 14 highlights where EC D move-acquire-measure time) allows for a significant did not detect any shift in the process. Furth e rm o re , increase in production sampling. This leads to faster while the process shift was confirmed by using TEM, if accumulation of statistically significant data, which red u c e s TEM alone was used, confirmation and reaction time to the excursion would have been greatly increased due to tu rn - a r ound-time and sampling rate limitations of TEM.

Gate oxide punch-through detection The ability to detect gate oxide punch-through is an area where SpectraCD has demonstrated unique capability. Gate oxide punch-through is a yield-limiting defect that has proven difficult to detect in low levels us i n g optical and/or CD SEM inspection. In the example shown F i g u re 12. nMOS ID r i v e c h a rt reflecting 5 percent shift.

F i g u re 13. Etch chamber post-PM excursion detected by SpectraCD.

10 Summer 2003 Yield Management Solutions M E T R O L O G Y

Conclusions In this article we have presented the results obtained from the SpectraCD spectroscopic ellipsometry-based metrology tool being utilized at the Texas Instruments DMOS6 production facility for inline process control and product disposition at the gate lithography and etch process steps. The results demonstrate the capability of this technique in providing accurate and precise profile F i g u re 14. Etch chamber post-PM excursion not detected by ECD. information of the polysilicon gate structures. The long-term precision results for the gate litho and etch in Figure 15, very low levels of gate oxide punch-throu g h structures, show that SpectraCD is capable of meeting were detected by monitoring the goodness-of-fit (GOF) the precision requirements for the 130 nm node of the of the SpectraCD measurements. In t e r national Technology Roadmap for .

When the measured spectrum from a grating target is A critical parameter in determining device performance compared against the theoretical library, SpectraCD is the transistor drive current, which can be measured generates a GOF value, which mathematically rep re s e n t s only after the metallization process steps have been how closely the measured spectrum matches the solution completed. SpectraCD measurements of the grating from the library. The small holes in the gate oxide target in the scribe line show good correlation with the underneath the grating target scatter the incident SE transistor drive current, thus providing an inline mea- beam, introducing random noise into the measured surement technique at the gate etch step, which can be spectra, leading to a decrease in GOF. used to perform effective process control and product disposition. Process excursions caused due to the etcher The plot in Figure 15 shows a clear decrease of 0.02- PM and oxide punch-through were captured by 0.06 in GOF from a mean value that is typically stable SpectraCD measurements, which would have otherwise to within ±.01. Subsequent CD SEM inspection of the gone undetected for a longer period of time. grating targets highlighted the small holes rep re s e n t i n g the gate oxide punch-through. References As a result of the reliable method of detection with 1. J. Allgair, D. Benoit, M. Dre w, R. Hershey, L. Litt, P. Herre r a , SpectraCD, an inline CD SEM inspection has been U. Whitney, M. Guevremont, A. Levy, S. Lakkapragada, eliminated, saving cost without sacrificing reliable “Implementation of Spectroscopic Critical Dimension detection of punch-through defects and proper disposi- (SCD™) for Gate CD Control and Stepper Characterization,” P roceedings of SPIE, Volume 4344-57, March 2001. tion of production material. 2. H. Tompkins, W. McGahan, S p e c t roscopic Ellipsometry and Reflectometry, John Wiley & Sons, 1999.

A version of this art i c l e originally published in the 2003 SPIE Micro l i t h o g r a- phy proceedings 5038, SPIE Micro l i t h o g r a p h y C o n f e rence, Fe bru a ry 2003, Santa Clara, Cali- f o rnia, USA.

F i g u re 15. SpectraCD GOF plot with corresponding SEM images confirming detection of gate oxide punch-thro u g h .

Summer 2003 Yield Management Solutions 11