Week 11: Differential Amplifiers

ELE 2110A Electronic Circuits

Reading Assignment: Chap 15.1-15.8 of Jaeger and Blalock or Chap 7.1 - 7.3, of Sedra and Smith

z Two identical transistors with emitters shorted together, connecting to a resistor or a current source. Transistors operate in active mode. z Designed to amplify voltage difference between the two inputs z One of the most used circuit building blocks – E.g., as the input stage of opamps

I = iE1 + iE 2 = iC1 /α + iC 2 /α

αI iC 2 αI ⇒ = + 1 iC1 = i i −vid /VT C1 C1 1+ e αI ⇒ i = αI C1 i iC 2 = C 2 + 1 1+ e +vid /VT iC1

vBE 1 /VT iC1 = I S e

vBE 2 /VT iC 2 = I S e

(vBE 1 −vBE 2 ) /VT vid /VT iC1 / iC 2 = e = e where vBE1 − vBE 2 = vB1 − vB 2 = vid

z |vd| = |vB1-vB2| < VT for use as a linear amplifier

z For |vd| > 4VT (≈100mV), the tail current flows almost entirely in one of the two transistors – This high sensitivity makes the differential pair a fast current switch – The transistors are either in active mode or in cutoff mode

z Also contributes to high switching speed

ELE2110A © 2008 Lecture 11 - 6 Large Signal Analysis Assuming identical devices and neglecting the output resistance and body effect, the drain currents are ⎧ W i = 1 k ' (v −V )2 ⎪ D1 2 n L GS1 t ⎨ W ⎪i = 1 k ' (v −V )2 ⎩ D2 2 n L GS 2 t ⎧ 1 ' W ⎪ iD1 = kn (vGS1 −Vt ) ⎪ 2 L ⎨ ⎪ 1 ' W iD2 = kn (vGS 2 −Vt ) Fig. 6.29 The MOSFET differential pair. ⎩⎪ 2 L Solving eqs (1) & (2) yields Since, vGS1 − vGS 2 = vid ⎧ 2 W I ' W ⎛ vid ⎞ (vid / 2) We have1 ' (1) ⎪i = + k I ⎜ ⎟ 1− iD1 − iD2 = 2 kn vid D1 n W L ⎪ 2 L ⎝ 2 ⎠ I k ' ⎪ n L The current-source bias imposes the ⎨ 2 ⎪ I ' W ⎛ vid ⎞ (vid / 2) constrain iD2 = − kn I ⎜ ⎟ 1− ⎪ 2 L ⎝ 2 ⎠ ' W iD1 + iD2 = I (2) ⎪ I kn ⎩ L ELE2110A © 2008 Lecture 11 - 7 Large Signal Analysis

I ⎧ 2 At the bias point, v = 0, leading to i = i = I I ⎛ v ⎞ ⎛ v / 2 ⎞ id D1 D2 ⎪ id ⎜ id ⎟ 2 iD1 = + ⎜ ⎟ 1− ⎜ ⎟ ⎪ 2 VGS −Vt ⎝ 2 ⎠ VGS −Vt Correspondingly, v = v = V ∴ ⎝ ⎠ GS1 GS 2 GS ⎨ 2 ⎪ I I ⎛ vid ⎞ ⎛ vid / 2 ⎞ I 1 ' W 2 ⎪iD2 = − ⎜ ⎟ 1− ⎜ ⎟ where = kn ()VGS −Vt 2 V −V 2 ⎜V −V ⎟ 2 2 L ⎩⎪ GS t ⎝ ⎠ ⎝ GS t ⎠

For vid / 2 << VGS −Vt (small signal approximation)

⎧ I I ⎛ vid ⎞ ⎪iD1 = + ⎜ ⎟ ⎪ 2 V −V ⎝ 2 ⎠ ⎨ GS t I I v ⎪ ⎛ id ⎞ iD2 = − ⎜ ⎟ ⎩⎪ 2 VGS −Vt ⎝ 2 ⎠

2(I / 2) I Since gm = = VGS −Vt VGS −Vt

We have the signal component id of iD as id = gm (vid / 2)

At full switching situation (that is, iD1=I and v = 2(V −V ) id max GS t iD2=0, or vice versa), the value of vid is:

v + v Common-mode component: v = 1 2 (the average) ic 2

Differential-mode component: vid = v1 − v2 (the difference)

Analyze the circuit by superposition of DM and CM signals

v First set the common-mode input to 0: − id 2

v − id 2

v v id v =− id −v v = −ve 4 e 3 2 2 v v v 1 v g v + 3 +g v + 4 = e (g + )(v +v )= e Ignoring ro, we have m m m 3 r 4 r R r 3 4 R π π EE π EE

v 1 e Emitter = AC ground for DM input. (gm+ )(−2ve)= ve =0 r R π EE No bypass cap is needed!

v − id 2

ve =0 ∴v =v /2 v =−v /2 3 id 4 id v v id id v =−gmR v =+gmR c1 C 2 c2 C 2 Differential-mode gain is: Differential output: v od v =v −v =−g R v A ≡ =−gmR od c1 c2 m C id dd v C id v =0 ic ELE2110A © 2008 Lecture 11 - 14 Voltage Gain for Single-ended Output

v − id 2

v v id v =+g R id v =−gmR c2 m C c1 C 2 ve =0 2

If either vc1 or vc2 is used alone as output, output is said to be single- ended. v g R A v g R A A ≡ c1 =− m C = dd A ≡ c2 = m C =− dd dd1 v 2 2 dd2 v 2 2 id v =0 id v =0 ic ic

v − id 2

ve =0

Differential-mode input resistance:

v (v /2) id id ∴R ≡ =2rπ since i = id i b1 r b1 π

v − id 2

ve =0

Differential-mode output resistance is the resistance seen between VC1 and VC2: R =2(R r )≅2R od C o C Single-ended output resistance is the resistance seen

between VC1 (or VC2) and ground: R ≅ R od C

0 0

Set differential-mode input to 0:

Circuit is symmetrical v ve Ignoring ro: 2(1+ β )i = i = ic b b REE r +2(β +1)R π EE ve = vic − ib rπ − βR R Output voltages are: v =v =−βi R = C v ≅ C v c1 c2 b C r +2(β+1)R ic 2R ic π EE EE Differential output = 0 Common-mode voltage gain for single-ended output

Circuit is symmetrical

v 2(β+1)R i = ic EE ve =2(β+1)i R = v ≅v b r +2(β +1)R b EE r +2(β+1)R ic ic π EE π EE

Emitter not AC ground for CM input.

Circuit is symmetrical

CM input resistance is the resistance seen between the shorted bases

(Vic) and ground: v r +2(β+1)R r R = ic = π EE = π +(β+1)R ic 2i 2 2 EE b

Two ib are drawn from the input voltage source consisting two parallel Vic.

– represents ability of amplifier to amplify desired DM input signal and reject undesired CM input signal. z For output defined differentially, the common-mode gain of a balanced amplifier is zero Æ CMRR is infinite – Many noises appear in common form to the input and thus do not appear at the output

R R v ≅ − C1 v v ≅ − C2 v Δ+-Δ c1 2R ic c2 2R ic EE EE

R −R ∆R R v =v −v ≅ C2 C1v = C C v od c1 c2 2R ic R 2R ic EE C EE

∆R R − R where C = C 1 C 2 represents fractional mismatch RC ()RC1 + RC 2 / 2

⎛ ⎞−1 A g R ⎜ ∆R ⎟ dm m C ⎜ C ⎟ ∴ CMRR ≡ = = g R ⎜ ⎟ REE should be maximized A ∆R R m EE ⎜ ⎟ cm ⎜ R ⎟ C C ⎝ C ⎠ for good CMRR R 2R C EE

Define the DM and CM where outputs as Add = differential-mode gain v = v −v A = common-mode to differential-mode od c1 c2 cd conversion gain v + v c1 c2 Acc = common-mode gain voc = 2 Adc = differential mode to common-mode Output and input are related conversion gain by the gain matrix: For ideal symmetrical amplifier, ⎡v ⎤ ⎡ A A ⎤⎡v ⎤ ⎢ od ⎥ ⎢ dd ⎥⎢ id ⎥ A = A = 0. ⎢ ⎥ = ⎢ cd ⎥⎢ ⎥ cd dc ⎢v ⎥ ⎢ A A ⎥⎢v ⎥ ⎣ oc ⎦ ⎡ ⎤ ⎣⎢ dc cc ⎦⎥⎣ ic ⎦ ⎡v ⎤ A 0 ⎡v ⎤ ⎢ od ⎥ ⎢ ⎥⎢ id ⎥ ∴⎢ ⎥ = ⎢ dd ⎥⎢ ⎥ ⎢ v ⎥ ⎢ A ⎥⎢ v ⎥ ⎣ oc ⎦ ⎣ 0 cc ⎦⎣ ic ⎦

Purely differential-mode input gives purely differential-mode output and vice versa.

z Redraw the differential amplifier in a fully symmetrical form – power supplies are split into two equal halves in parallel – emitter resistor is separated into two equal resistors in parallel z For differential mode signals, points on the line of symmetry are grounds for ac analysis

–VCC and VEE are AC grounds

–ve is AC ground as proven previously z For common-mode signals, points on line of symmetry are replaced by open circuits – b/c no current flows across the line of symmetry

Direct analysis of the half-circuits yield: v id v = −gmR c1 C 2 v id v = +gmR c2 C 2 v = v −v = −g R v o c1 c2 m C id

R = v /i =2r id id b1 π z The two power supply lines and R =2(R r ) emitter become ac grounds od C o z The half-circuit represents a C-E amplifier stage

For DC For AC

Half circuit z All points on line of symmetry become open circuits

vic ≤ 5mV (1+ gm 2REE )

z REE is very large in most cases Æ Wide common-mode input range

Another condition is that BJT must be in active mode:

αV =V − I R −V ≥ 0 CB CC C C IC V −V +V I = IC BE EE C 2R α EE ⎛ ⎞ ⎜ ⎟ R ⎜V −V ⎟ V − C ⎝ EE BE ⎠ CC 2R ∴V ≤ EE IC αR 1+ C 2R EE

For example, if VCC=VEE, VEE >> VBE, and RC = REE,

V V ≤ CC IC 3

z Differential amplifiers biased using current sources has – A more stabilized operating point

– A higher effective value of REE to improve CMRR

V Equivalent of Iss I = I − 0 DC SS R SS

IS = ISS /2.

DC Half-circuit

K 2 n ⎛ ⎞ V =V =V − I R and V =0 I = ⎜V −V ⎟ D1 D2 DD D D OD D ⎝ GS TN ⎠ 2 2I I V =V + D =V + SS V =V −V =V − I R +V GS TN TN DS D S DD D D GS Kn Kn

ELE2110A © 2008 Lecture 11 - 32 Example z Problem: Find Q-points of transistors in the differential amplifier and the upper limit of input CM voltage. z Given data: VDD=VSS=12 V, ISS =200 µA, RSS = 500 kΩ, RD = 62 kΩ, -1 2 λ = 0.0133 V , Kn = 5 mA/ V , VTN =1V z Analysis: I I = SS =100µA D 2 200µA V =1+ =1.20V GS 5mA/V 2

V =12V-(100µA)(62kΩ)+1.2V =7V DS

To maintain pinch-off operation of M1 for nonzero VIC ,

⎛ ⎞ ⎜ ⎟ V =V - ⎜V - I R ⎟ ≤V GD IC ⎝ DD D D ⎠ TN ∴V ≤V - I R +V = 6.8V IC DD D D TN

Gain for DM output is ac ground v od A = = −gmR dd v D id v = 0 ic Gain for single-ended output is

Half Circuit v g R A A = d1 = − m D = dd dd1 v 2 2 v id v = 0 v =−g R id ic m D d1 2 v g R A A = d2 =+ m D =− dd v dd2 v =+g R id v 2 2 m D id v =0 d2 2 ic DM input and output resistance: ∴v =−gmR v od D id R =∞ R =2R id od D

Half Circuit

Rss = Two 2Rss in parallel Common-mode half-circuit = common-source

amplifier with 2RSS as source resistor

−g R v =v = m D v d1 d2 1+2g R ic m SS Common-mode gain: g R R voc m D D Acc = =− ≅ − v 1+2g R 2R ic v =0 m SS SS id CM input to DM output conversion gain = 0 because Half Circuit v =v −v =0 od d1 d2

Common-mode input resistance:

R =∞ ic

A A CMRR = dm = dm →∞ Acm 0 – Mismatch will result in finite CMRR as in the BJT differential pair. z For single-ended output, −(g R )/2 Adm Add /2 m D CMRR = = = = gmR Acm Acc −R /(2R ) SS D SS

– RSS should be maximized

z Most noises, such as power supply noise, appear to be common mode signal and not amplified by the amplifier. – CMRR represents its ability to reject CM input signal. – It can produce AC ground (for DM input) at emitter without using bypass capacitors – Input common mode range is very wide z Half circuit analysis technique – Points on the line of symmetry are open-circuits for CM signal – Points on the line of symmetry are AC grounds for DM signal