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Monolithically Integrated Boost Converter Based on 0.5- M CMOS

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Monolithically Integrated Boost Converter Based on 0.5- M CMOS 628 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 3, MAY 2005 Monolithically Integrated Boost Converter Based on 0.5-"m CMOS Process Haifei Deng, Student Member, IEEE, Xiaoming Duan, Nick Sun, Yan Ma, Alex Q. Huang, Senior Member, IEEE, and Dan Chen, Fellow, IEEE Abstract—Today and in the future, a huge market arises for mo- in monolithic integration. In order to reduce cost, logic CMOS bile power [1]. Efficient performance, functionality, small profile technology is considered to be a good option for portable ICs and low cost are the most desired features for mobile power man- due to its low cost and the good electrical performance of the agement integrated circuits. Compared with the discrete-switching dc–dc converter, monolithic integration offers many benefits and sub-micron NMOS and PMOS [4]–[6]. In particular, sub-mi- new design challenges. In this paper, a monolithically integrated cron MOSFETs outperforms the vertical power MOSFET in high-efficiency boost dc–dc converter for nickel metal hydride or terms of switching speed; this makes the CMOS-based mono- alkaline battery-powered applications is designed based on the lithic converter suitable for high-frequency applications. Since low-voltage CMOS process. Several novel concepts are proposed the battery source for portable power can be a single 1.2-V for compensator design, low-voltage startup, light-load efficiency and power device optimization. nickel metal hydride with a final discharge voltage of 0.8 V to several 4.3-V LiIon batteries in series [1], both low-voltage Index Terms—CMOS, dc–dc converter, monolithic. and high-voltage operation may be required for portable power ICs. At the low-voltage end, low-voltage analog IC design is I. INTRODUCTION a challenge in terms of safely starting up the boost converter chip. At the high-voltage end, higher-voltage CMOS or CMOS ORTABLE power is increasingly becoming the most variants are needed for high-input-voltage applications. P important application area for power semiconductor in- tegrated circuits (ICs). Small form factor, high efficiency and II. STRUCTURE OF THE MONOLITHIC BOOST CONVERTER low cost are the most desired features for portable power ICs. In order to reduce the form factor, monolithic integration is In this paper, a monolithic low-voltage high-efficiency boost preferred, which means that everything from the compensator, dc–dc converter for Ni-Metal hydride or alkaline battery- pow- external ramp, driver and power switches will be integrated ered application is designed based on the low-voltage 0.5- onto a single chip. With current technology, the energy storage m CMOS process. Fig. 1 shows the simplified block diagram elements like inductor and output capacitor have to be placed for the converter chip. Table I lists the key operation speci- off silicon because of the low value of inductor and high cost fications for this converter. Peak-current control pulse width to build large size on-silicon capacitor. Future development will modulation (PWM) and pulse frequency modulation (PFM) are even make it possible to integrate the energy storage elements, used for heavy-load and light-load operations respectively. A such as the inductor and capacitor. This development relies start-up controller is used for low-voltage start-up. 0.5- mlow- on further technology development in the area of high-density voltage NMOSFET is used as the boost switch and a sub-mi- inductor and capacitor design that is compatible with semi- cron PMOSFET is used as a synchronous rectifier to further im- conductor technology, as well as the techniques to operate the prove efficiency. An external Schottky diode is paralleled with converter at extremely high frequencies [2], [3]. Since the right the PMOSFET to prevent the body diode from conduction and half-plane zero and resonant poles of the boost converter move to conduct the inductor current during the dead-time period. The according to input voltage, output voltage and load current, controller power is supplied by the output voltage. The min- how to design a fixed compensator built inside the chip for a imum start-up voltage is 1.1 V, which is limited by the threshold wide operation range is a big challenge. Since the power device voltage of the PMOSFET and NMOSFET. After start-up, the and driver are integrated with the control circuit, noise can be converter can operate with an input voltage as low as 0.7 V, easily injected from the power stage to the analog control part. which is determined by the maximum duty cycle of the con- Noise separation between these areas is therefore a major issue verter. Manuscript received April 7, 2004; revised November 9, 2004. Recom- III. CHIP DESIGN CONSIDERATIONS mended by Associate Editor J. A. Ferreira. H. Deng, N. Sun, and Y. Ma are with the Center for Power Electronics A. Stability Modeling and Adaptive Compensation Design for Systems, Department of Electrical and Computer Engineering, Virginia a Wide Application Range Polytechnic Institute and State University, Blacksburg, VA 24060-0179 USA (e-mail: [email protected]). Fig. 2 shows the simplified diagram for peak-current PWM X. Duan and A. Q. Huang are with the Semiconductor Power Electronics control. Since the right half-plane zero and resonant poles of the Center, Department of Electrical and Computer Engineering, North Carolina power stage for boost move according to duty cycle State University, Raleigh, NC 27695-7571 USA. D. Chen is with National Taiwan University, Taipei, Taiwan, R.O.C. and load current, it is quite difficult to design a fixed Digital Object Identifier 10.1109/TPEL.2005.846551 on-chip compensator to stabilize the converter system for a wide 0885-8993/$20.00 © 2005 IEEE DENG et al.: MONOLITHICALLY INTEGRATED BOOST CONVERTER 629 Fig. 1. Functional block diagram of the developed monolithic boost converter chip. TABLE I KEY PARAMETERS FOR THE CHIP Fig. 2. Simplified block diagram of peak current control PWM controller. operation range. For monolithic integration, since the compen- sator, ramp compensation and current sensor are fixed inside the Fig. 3. q with different load and input voltage (a) q without constant silicon; the loop-gain design for the monolithic boost converter ripple assumptions and (b) q with constant ripple assumptions. becomes very challenging. According to Ridley [7], when the current loop is closed, the this purpose, we proposed the following two constant-ripple de- power stage is degraded to a one-order system. The compensa- sign approaches: Constant inductor current ripple assumption tion is designed based on the transfer function from to as shown in Fig. 2. Fig. 3 shows the bode plot of . There are a dominant pole , a right half-plane zero and a double-pole at the half switching frequency in . For different applications, the dominant pole and right half-plane zero (1) move with duty cycle and the load current, as shown in Fig. 3(a). In order to make the system stable for all cases, it Constant output voltage ripple assumption is desirable to keep and constant for different ap- plications (different and load current) so that a fixed compensator can be used to compensate the whole system. For (2) 630 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 3, MAY 2005 In this design approach, and should be selected as constants by choosing correct values for and in different applications. Based on (1) and (2), the and can be simplified as (3) (4) Now, is close to a constant and will only change with load current. Fig. 3(b) shows under these two assump- tions. Compared with the in Fig. 3(a), the in Fig. 3(b) allows for much easier compensation by a two-pole-one-zero network. Fig. 3(b) shows that when the load current increases, the dc gain of will drop down and will move to a lower frequency. If the second pole of the compensator is much higher than due to the rise of load current, the final system loop gain may rise above unity gain and cause the system to be unstable. In order to achieve high bandwidth and stability for different series of duty cycle and different load current; an adaptive compensation concept is proposed. In the adaptive compensation, when the load current increases, the dc gain of the compensator will increase; meanwhile, the second pole will move to lower frequency to damp the of so that the gain of will not rise above 0 dB and cause stability problems. Fig. 4(a) shows the adaptive compensation concept, and Fig. 4(b) shows the system loop gain at different conditions. The bandwidth of the system loop gain is close to a constant 10 kHz for different application conditions. The stability is obviously improved by constant ripple assumptions and adaptive compensation. Fig. 4(a) shows that the compensator requires a zero at around 1 kHz and one pole at around 30 kHz; Fig. 5(a) shows the widely used op-amp-based two-pole-one-zero compensator network. According to the equations in the right hand part of Fig. 5(a), the needed passive components are 17.5 k 10 k , 16.7 K , 500 k , 308 pF and 18.2 pF. However, it is typically very difficult to implement large-value resistors and capacitors on silicon. The capacitors needed for this op-amp-based compensator are too large to be integrated. In order to reduce the area needed for the compensator, a novel Fig. 4. Adaptive compensation concept and system loop gain with constant compensator structure called active feedback compensator is ripple assumption and adaptive compensation (a) adaptive compensation and proposed for this chip. The basic idea of this compensator is (b) system loop gain.
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