AN-1051

APPLICATION NOTE One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Reference Design for the AD9552 Oscillator Frequency Upconverter by Ken Gentile

INTRODUCTION PCB are strictly auxiliary. For instance, P1 in the upper left The AD9552 is a low cost, programmable device that accepts corner serves only to bring power (3.3 V) to the board. Like- a low frequency input signal (between approximately 10 MHz wise, components J1, T1, C4, C5, R11, and R12 in the lower and 70 MHz) and upconverts it to a high frequency output right corner serve only as a convenient means of measuring the signal (up to 900 MHz). This application note provides a AD9552 output signal. The switch (SST) to the right of P1 is reference design for the AD9552 and includes the performance an auxiliary method for resetting the AD9952 (in lieu of cycling measurements of the output signal. It demonstrates that the the power). The bottom side of the PCB contains no compo- AD9552 (and all necessary supporting components) fits within nents other than pads for several grounding jumpers (0 Ω a 9 mm × 14 mm footprint—the same size as some currently resistors) to facilitate pin programming of the AD9552. The available oscillator packages. Refer to AN-0988 for additional reference design includes jumpers only to allow for different information on the features and function of the AD9552. crystal types or output frequencies. An end user application typically consists of one crystal type and a fixed output PRINTED CIRCUIT BOARD frequency. Thus, jumpers are not required on an end user A photograph of the 1” × 1.25” reference design circuit board circuit board. Instead, one would route copper traces directly appears in Figure 1. Note the silkscreened 9 mm × 14 mm from the appropriate programming pins to ground to select the rectangle, which contains the following: desired crystal frequency and output frequency for the specific application. • the AD9552 • a crystal resonator This particular reference design uses a 19.44 MHz crystal • power supply bypass capacitors resonator with the AD9552 pin programmed for 625 MHz at • PLL loop filter components OUT1. Note that this demonstrates the ability of the AD9552 to perform noninteger frequency translation (19.44 MHz in, These constitute all the necessary components to create an 625 MHz out). Furthermore, the design makes use of the oscillator frequency upconverter. The other components on the AD9552’s default output driver operating mode (LVPECL).

08639-001 Figure 1. AD9552 Reference Design PCB

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The PCB is a 4-layer board using standard FR4 material. The top and bottom layers are for signal routing, whereas the two inner layers are dedicated copper planes for power (VDD) and ground (GND). To ensure the best possible performance, it is important to place bypass capacitors as close as possible to the AD9552. In addition, it is best to use two vias (through holes), instead of only one, from the grounded pad of each bypass capacitor to the ground plane. This reduces the series inductance from the bypass capacitor to the ground plane, thereby improving high DOUBLE frequency coupling to the ground layer (see Figure 2). VIAS

08639-002 Figure 2. PCB Top Layer Showing Double Vias

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SCHEMATIC DIAGRAM To facilitate measurement of the signal at OUT1, the device drives a balanced load (50 Ω) into a 1:1 transformer routed to a coaxial cable connector (see Figure 3). T1 J1

3 4 OUT

24.9Ω 2 5

0Ω = PIN PROGRAMMING JUMPERS 0.1µF 1 6 1:1 0.1µF 3.3V 24.9Ω 0.1µF Ω Ω Ω Ω 0 0 0 0

32 31 30 29 28 27 26 25 Y3 Y2 Y1 Y0 VDD GND 1 OUT1 OUT1 24 0Ω Y4 PIN 1 GND INDICATOR 2 0Ω Y5 OUT2 23 3 0Ω A0 OUT2 22 4 21 0Ω A1 AD9552 VDD 3.3V TOP VIEW 0.1µF 5 0Ω A2 (Not to Scale) LOCKED 20 0.47µF SST 6 19 RESET LDO NC 7 18 3.3V VDD VDD 3.3V 0.1µF 0.1µF 8 17 LDO LDO 0.47µF 0.47µF XTAL XTAL REF CS SCLK SDIO OUTSEL FILTER

910111213141516 Ω

0 12nF CRYSTAL

3.3V 3.3V

P1 08639-003

VDD GND Figure 3. Schematic Diagram

PERFORMANCE MEASUREMENTS Performance measurements include two phase-noise plots (see Figure 4 and Figure 5) obtained with an Agilent Technologies E5052B Signal Source Analyzer, and a spectral plot (see Figure 6) from a Rhode and Schwarz FSQ-26 Signal Analyzer. The measurement setup consists of only a 3.3 VDC power supply connected to P1 and a co-axial cable connected between J1 and the measurement instrument.

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0 RMS JITTER ANALYSIS OF THE RESULTS –20 12kHz TO 20MHz: 726fs 50kHz TO 80MHz: 524fs The phase-noise plot in Figure 5 (spurious = on) indicates 4MHz TO 80MHz: 112fs –40 spurious artifacts at offset frequencies that are multiples of 19.44 MHz (a consequence of the 19.44 MHz crystal resonator). –60 However, the rms jitter values suggest that the spurious artifacts

–80 are sufficiently low in magnitude and, thus, of no concern for

dBc/Hz applications using the 12 kHz to 20 MHz integration band. This –100 is because Figure 4 and Figure 5 differ by only 4 fs in this band. –120 The 50 kHz to 80 MHz integration band, however, indicates a degradation of 170 fs in jitter performance for spurious = on, –140 while the 4 MHz to 80 MHz integration band indicates a –160 degradation of 361 fs. The latter shows such a large degradation 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) (an increase in jitter of 322%) because most of the phase-noise 08639-004 Figure 4. Phase Noise at 625 MHz (Spurious = Off) energy in the 4 MHz to 80 MHz integration band is spurious rather than random.

0 The spectral plot (Figure 6) shows the output signal centered RMS JITTER at 625 MHz with a measurement span of 50 MHz. Note the –20 12kHz TO 20MHz: 730fs 50kHz TO 80MHz: 694fs relatively low noise floor (near −90 dBm with a resolution 4MHz TO 80MHz: 473fs –40 bandwidth of 3 kHz) and the two spurs with a magnitude of approximately −70 dBc positioned 19.44 MHz to either side –60 of the 625 MHz carrier. –80 These are reference spurs due to the 19.44 MHz input frequency dBc/Hz –100 of the crystal resonator. These spurs are a normal consequence of the PLL function. The magnitude of the reference spurs –120 directly relates to the bandwidth of the PLL loop filter relative

–140 to the reference frequency. The nominal bandwidth of the AD9552 loop filter is 100 kHz, which results in reducing the –160 10 100 1k 10k 100k 1M 10M 100M reference spurs to the −70 dBc range. FREQUENCY (Hz) 08639-005 Although the reference spurs and their associated harmonics Figure 5. Phase Noise at 625 MHz (Spurious = On) degrade wideband jitter performance, applications requiring low wideband jitter have two options for mitigating this effect. *RBW 3kHz DELTA 1 [T1] The first option is to provide band-pass filtering of the output VBW 10kHz –70.33dB signal. In this particular case, a 20 MHz band-pass filter REF 0dBm *ATT 20dB 1 SWT 5.6s –19.471153846MHz centered at 625 MHz can significantly reduce the wideband MARKER 1 [T1] –10 –1.01dBm spurious content, thus improving wideband jitter performance. 625.000000000MHz The second option is to pass the output signal through a second –20 PLL that has a 1:1 frequency translation ratio and a loop –30 bandwidth that is well below 20 MHz (several hundred

–40 kilohertz, for example). The second PLL effectively acts as a jitter cleanup PLL by rejecting the wideband spurious signals –50 (reference spurs in this case) that are outside of its loop –60 bandwidth. 1 –70

–80

–90

CENTER 625MHz 5MHz/ SPAN 50MHz 08639-006 Figure 6. Output Signal Spectrum

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