DOCSLIB.ORG

Bibliography

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

Bibliography [1] D. Abramson and G. Egan: "The RMIT Data Flow Computer, a Hybrid Architecture" in Computer Journal, Vol. 33, No.3 (Special Issue, June 1990), pp/230-240. [2] E. Abreu et al.: "The APx Accelerator" in Proceedings of the 2nd Symposium on the Frontiers of Massively Parallel Computation, 1988, pp/413-417. [3] Z. Abuhamadeh: "The GAM II Pyramid" in Proceedings of the 2nd Symposium on the Frontiers of Massively Parallel Computation,1988, pp/443-448. [4] A. Agarwal et al.: "The MIT Alewife Machine: A Large-Scale Distributed-Memory Mul­ tiprocessor" in Workshop on Scalable Shared-Memory Multiprocessors, Seattle, June 1990, published by Kluwer Academic Publishers. [5] H. Aiso, K. Sakamura and T. Ichikawa: "A Multi-Microprocessor Architecture for Asso­ ciative Processing of Image Data" in M. Onoe, K. Preston, Jr. and A. Rosenfeld (Eds.): "Real Time/Parallel Computers," , Plenum Press, 1981, pp/203-217. [6] D. L. Allen et al.: "MUSE: A Wafer Scale Systolic DSP" in Proceedings of the Inter­ national Conference on Wafer Scale Integration, 1990, pp/27-35. [7] G. S. Almasi: "Overview of Parallel Processing" in Parallel Computing, Vol. 2 (1985), pp/191-203. [8] G. S. Almasi and A. Gottlieb: "Highly Parallel Computing," Benjamin/Cummings, 1989. [9] M. Amamiya et al.: "Implementation and Evaluation of a List Processing Oriented Dataflow Machine" in Proceedings of the 13th Annual International Symposium on Computer Architecture, 1986, pp/10-19. [10] H. Amano et al.: "(SM)2_II - A New Version of the Sparse Matrix Solving Machine" in 12th Annual International Symposium on Computer Architecture, 1983, pp/1OQ-107. [11] AMETEK Computer Research: "AMETEK Series 2010 Multicomputer" in Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988, Vol. I, pp/836-839. [12] J. M. Anderson et al: "The Architecture of FAIM-1" in IEEE Computer, Vol. 20, No.1 (January 1987), pp/55-65. [13] J. P. Anderson et al.: "D825: A Multiple Computer System for Command and Con­ trol" in AFIPS Conference Proceedings, Vo1.22, 1962 Fall Joint Computer Conference, Spartan Books, pp/86-96. Reprinted in [43], pp/447-455. [14] M. Annaratone et al.: "The Warp Computer: Architecture, Implementation and Per­ formance" in IEEE Transactions on Computers, Vol. C-36, No. 12 (December 1987), pp/1523-1538. [15] M. Annaratone and R. Riihl: "Performance Measurements on a Commercial Multipro­ cessor Running Parallel Code" in Proceeding of the 16th Annual International Sympo­ sium on Computer Architecture, 1989, pp/307-314. [16] M. Annaratone et al.: "The K2 Parallel Processor: Architecture and Hardware Imple­ mentation" in Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990, pp/92-103. 123 124 Bibliography [17J M. Annaratone et al.: "Architecture, Implementation and System Software of K2" in A. Bode (Ed.): Distributed Memory Computing, Proceeding of the 2nd European Conference, EDMCC2, 1991, pp/473-484. [18J E. Appiani et al.: "EMMA 2 - An Industry Developed Hierarchical Multiprocessor for Very High Performance Signal Processing" in Proceeding's of the 1st International Conference on Supercomputing Systems, 1985, pp/310-319. [19J ARCHIPEL, "VOLVOX MACHINES OVERVIEW" Archipel, 24, boulevard de I'Hopital - 75005 Paris, France. [20J R. Arlauskas: "iPSC/2 System: A Second Generation Hypercube" in Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988, Vol. I, pp/38-42. [21J C. V. W. Armstrong and E. T. Fathi: "A Fault-Tolerant Multimicroprocessor-Based Computer System for Space-Based Signal Processing" in IEEE Micro, Vol. 4, No. 6 (December 1984), pp/54-65. [22J Arvind and R. A. Iannucci: "A Critique of Multiprocessing von Neumann Style" in 10th Annual International Symposium on Computer Architecture, 1983, pp/426-436. [23J K. Asanovic and J. R. Chapman: "Spoken Natural Language Understanding as a Paral­ lel Application" in C. R. Jesshope and K. D. Reinartz (Eds.): CONPAR 88, Cambridge University Press, 1989, pp/508-515. [24J P. J. Ashenden, C. J. Barker and C. D. Marlin: "The Leopard Workstation Project" in Computer Architecture News, Vol. 15, No.4 (September 1987), pp/40-51. [25J P. M. Athanas and H. F. Silverman: "Armstrong II: A Loosely Coupled Multiprocessor with a Reconfigurable Communications Architecture" in Proceedings of the 5th Inter­ national Parallel Processing Symposium, 1991, pp/385-388. [26J W. C. Athas and C. L. Seitz: "Multicomputers: Message Passing Concurrent Comput­ ers" in IEEE Computer, Vol. 21, No.8 (August 1988), pp/9-24. [27J R. R. Atkinson and E. M. McCreight: "The Dragon Processor" in Computer Architec­ ture News, Vol. 15, No.5 (October 1987), pp/65-69. [28J T. Baba, K. Ishikawa and K. Okuda: "A Two-Level Microprogrammed Multiprocessor Computer with Non-Numeric Functions" in IEEE Transactions on Computers, Vol. C- 31, No. 12 (December 1982), pp/1l42-1156. [29J R. G. Babb II (Ed.): "Programming Parallel Processors," Addison-Wesley, 1988. [30J J.-1. Baer: "Whither a Taxonomy of Computer Systems" in IEEE International Work­ shop on Computer Systems Organization, 1983, pp/3-9. [31J A. F. Bakker et al.: "A Special Purpose Computer for Molecular Dynamics Computa­ tion" in Journal of Computational Physics, Vol. 90, No.2 (October 1990), pp/313-335. [32J J. Ballam: "Future Plans For HEP Computing in the U.S." in L. O. Hertzberger and W. Hoogland (Eds.): Proceedings of the Conference on Computing in High Energy Physics, North-Holland 1986, pp/146-164. [33J J.-L. Basille et al.: "A Typical Propagation Algorithm on the Line Processor SY.MP.A.T.I.: The Regional Labeling" in K. Preston, Jr. and L. Uhr (Eds.): "Multi­ computers and Image Processing, Algorithms and Programs," Academic Press, 1982, pp/99-110. [34J F. Baskett, T. Jermoluk and D. Solomon: "The 4D-MP Graphics Superworkstation: Computing + Graphics = 40MIPS + 40MFLOPS and 100,000 Lighted Polygons per Second" in Spring COMPCON '88, pp/468-471. [35J H. B. Baskin, B. R. Borgerson and R. Roberts: "PRIME: A Modular Architecture for Terminal Oriented Systems" in AFIPS Conference Proceedings, Vol. 40, 1972 Spring Joint Computer Conference, pp/431-437. [36J K. E. Batcher: "The Massively Parallel Processor System Overview" in J. L. Potter (Ed.): "The Massively Parallel Processor," MIT Press, 1985, pp/142-149. [37J A. Bauch, R. Braam and E. Maele: "DAMP - A Dynamic Reconfigurable Multipro­ cessor System with a Distributed Switching Network" in A. Bode (ed.): Distributed Memory Computing, Proceeding of the 2nd European Conference, EDMCC2, 1991, pp/495-504. Bibliography 125 [38] A. Bauch et al.: "The Software-Monitor DELTA-T and Its Use for Performance Mea­ surements of Some Farming Variants on the Multi-Mansputer System DAMP" in L. Bouge et al. (Eds.): Proceedings of Parallel Processing CONPAR 92 - VAPP V, Springer-Verlag LNCS 634, pp/67-78. [39] BBN Advanced Computers Inc.: "Parallel Computing: Past, Present and Future", BBN, November 1990. [40] M. S. Beckerman: "IBM 3090" in R. G. Babb II (Ed.) : "Programming Parallel Pro­ cessors," Addison-Wesley, 1988, pp/93-103. [41] J. Beetem, M. Dennea and D. Weingarten: "The GFll Supercomputer" in Proceedings of the 12th Annual International Symposium on Computer Architecture, 1985, pp/108- 115. [42] G. Bell: "Ultracomputers: A Teraflop Before Its Time" in Communication of the ACM, Vol. 35, No.8 (August 1992), pp/27--47. [43] G. Bell and A. Newell: "Computer Structures: Readings and Examples," McGraw-Hill, 1971. [44] M. Beltrametti, K. Bobey and J. R. Zorbas: "The Control Mechanism of the Myrias Parallel Computer System" in Computer Architecture News, Vol. 16, No.4 (September 1988), pp/21-30. [45] R. Berger et al.: "The Lincoln Programmable Image Processing Wafer" in Proceedings of the International Conference on Wafer Scale Integration, 1990, pp/20-26. [46] V. P. Bhaktar: "Parallel Computing: An Indian Perspective" in H. Burkhart (Ed.): CONPAR '90 - VAPP IV, Springer-Verlag LNCS 457, pp/1O-25. [47] L. N. Bhuyan and D. P. Agrawal: "Design and Performance of Generalized Intercon­ nection Networks" in IEEE Transaction on Computers, Vol. C-32, No. 12 (December 1983), pp/l081-1089. [48] W. Bibel et al.:"Parallel Inference Machines" in P. Treleaven and M. Vanneschi (Eds.): "Future Parallel Computers," Springer-Verlag LNCS 272, 1987, pp/185-226. [49] L. Bic and R. L. Hartmann: "AGM: A Dataflow Database Machine" in ACM Transac­ tion on Database Systems, Vol. 14, No.1 (March 1989), pp/114-146. [50] L. Bic: "AGM: The Irvine Dataflow Database Machine" in V. M. Milutinovic (Ed.): "High Level Language Computer Architecture," Computer Science Press, 1989, pp/387- 412. [51] J. R. Biel et al.: "The ACP Cooperative Processes User's Manual" Fermilab Computing Division, DOcument #GA0006, NOv. 1990. [52] E. BinagJi et al.: "HCRC - Parallel Computer - A Massively Parallel Combined Ar­ chitecture Supercomputer" in Microprocessing and Microprogramming, Vol. 25, No. 1-5 (January 1989), pp/287-292. [53] R. Bisiani: "The Harpy Machine: A Data Structure Oriented Architecture" in Papers of the 5th Workshop on Computer Architecture for Non-Numeric Processing, ACM Press, pp/128-136. [54] R. Bisiani and M. Ravishankar: "PLUS: A Distributed Shared-Memory System" in Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990, pp/115-124. [55] R. Bisiani and M. Ravishankar: "Local Area Memory in PLUS" in M. Dubois and S. S. Thakker (Eds.): "Scalable Shared Memory Multiprocessors," Kluwer Academic Publishers, 1992, pp/301-311. [56] T. Blank: "The MasPar MP-l Architecture" in Proceedings of the IEEE COMPCON Spring '90, pp/20-24. [57] R. BlaSko: "Highly-Parallel Computation Model and Machine for Logic Programming" inDo J. Evans, G. R. Joubert and F. J. Peters (Eds.): Proceedings of Parallel Computing 89, North-Holland, 1990, pp/541-546. [58] D. W. Blevins et al.: "BLITZEN: A Highly Integrated Massively Parallel Machine" in Proceedings of the 2nd Symposium on the Frontiers of Massively Parallel Computation, pp/399-406.
Recommended publications
  • Memory Profiling on Shared-Memory Multiprocessors

    Memory Profiling on Shared-Memory Multiprocessors

    MEMORY PROFILING ON SHARED-MEMORY MULTIPROCESSORS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Jeffrey S. Gibson June 2004 c Copyright by Jeffrey S. Gibson 2004 All Rights Reserved ii I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Dr. John Hennessy (Principal Advisor) I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Dr. Mark Horowitz I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Dr. Mendel Rosenblum Approved for the University Committee on Graduate Studies: iii Abstract Tuning application memory performance can be difficult on any system but is particularly so on distributed shared-memory (DSM) multiprocessors. This is due to the implicit nature of communication, the unforeseen interactions among the processors, and the long remote memory latencies. Tools, called memory profilers, that allow the user to map memory behavior back to application data structures can be invaluable aids to the programmer. Un- fortunately, memory profiling is difficult to implement efficiently since most systems lack the requisite hardware support. This dissertation introduces two techniques for efficient memory profiling, each requiring hardware support on either the processor or the system node controller.
  • Microsparc-II-Usersm

    Microsparc-II-Usersm

    Products Rights Notice: Copyright © 1991-2008 Sun Microsystems, Inc. 4150 Network Circle, Santa Clara, California 95054, U.S.A. All Rights Reserved You understand that these materials were not prepared for public release and you assume all risks in using these materials. These risks include, but are not limited to errors, inaccuracies, incompleteness and the possibility that these materials infringe or misappropriate the intellectual property right of others. You agree to assume all such risks. THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND OTHER CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS (INCLUDING ANY OF OWNER'S PARTNERS, VENDORS AND LICENSORS) BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Sun, Sun Microsystems, the Sun logo, Solaris, OpenSPARC T1, OpenSPARC T2 and UltraSPARC are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the U.S. and other countries. Products bearing SPARC trademarks are based upon architecture developed by Sun Microsystems, Inc.
  • The Supersparc Microprocessor

    The Supersparc Microprocessor

    The SuperSPARC™ Microprocessor Technical White Paper 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. © 1992 Sun Microsystems, Inc.—Printed in the United States of America. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A All rights reserved. This product and related documentation is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® and Berkeley 4.3 BSD systems, licensed from UNIX Systems Laboratories, Inc. and the University of California, respectively. Third party font software in this product is protected by copyright and licensed from Sun’s Font Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, are trademarks or registered trademarks of Sun Microsystems, Inc. UNIX and OPEN LOOK are registered trademarks of UNIX System Laboratories, Inc. All other product names mentioned herein are the trademarks of their respective owners. All SPARC trademarks, including the SCD Compliant Logo, are trademarks or registered trademarks of SPARC International, Inc. SPARCstation, SPARCserver, SPARCengine, SPARCworks, and SPARCompiler are licensed exclusively to Sun Microsystems, Inc.
  • Deliveringperformanceonsun:Optimizing Applicationsforsolaris

    Deliveringperformanceonsun:Optimizing Applicationsforsolaris

    DeliveringPerformanceonSun:Optimizing ApplicationsforSolaris TechnicalWhitePaper 1997-1999 Sun Microsystems, Inc. 901 San Antonio Road, Palo Alto, California 94303 U.S.A All rights reserved. This product and related documentation is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® and Berkeley 4.3 BSD systems, licensed from UNIX Systems Laboratories, Inc. and the University of California, respectively. Third party font software in this product is protected by copyright and licensed from Sun’s Font Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, Sun WorkShop, and Sun Enterprise are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. UltraSPARC, SPARCompiler, SPARCstation, SPARCserver, microSPARC, and SuperSPARC are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. All other product names mentioned herein are the trademarks of their respective owners. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc.
  • Sun-4 Handbook - Home Page

    Sun-4 Handbook - Home Page

    Sun-4 Handbook - Home Page Sun Internal ONLY !! The Sun-4 Handbook describes and illustrates the Sun-4 and Sun-4e products for service providers who service these products after the End of Support Life in April 1997. End of Support Life is the end of Sun's commitment to support the product. Sun may help customers locate alternative sources for support on a case-by-case basis if ongoing support is needed beyond 5 years. Spares availability after End of Support Life may be limited and repair service will be at Sun's discretion. http://lios.apana.org.au/~cdewick/sunshack/data/feh/1.4/wcd00000/wcd00036.htm (1 von 2) [25.04.2002 15:56:23] Sun-4 Handbook - Home Page [ Configurations ] [ CPU ] [ Memory ] [ Graphics ] [ IPI ] [ SCSI ] [ SCSI Disk ] [ Removable Media ] [ Communication ] [ Miscellaneous ] [ Backplane ] [ Slot Assignment ] [ Parts Introduction ] [ System ] [ Disk Options ] [ Removable Media Options ] [ Miscellaneous Options ] [ Board ] [ Input Device ] [ Monitor ] [ Printer ] [ CPU Trouble ] [ Disk Trouble ] [ Diagnostics ] [ Power Introduction ] [ AC Power ] [ DC Power ] The original hardcopy publication of the Sun-4 Handbook is part number 805-3028-01. © 1987-1999, Sun Microsystems Inc. http://lios.apana.org.au/~cdewick/sunshack/data/feh/1.4/wcd00000/wcd00036.htm (2 von 2) [25.04.2002 15:56:23] Sun4/II: DC Power - Contents DC Power Power Supplies 300-1020 -- Brown -- 575 Watts 300-1020 -- Fuji -- 575 Watts 300-1022 -- Summit -- 325 Watts 300-1022 -- Brown -- 325 Watts 300-1024 -- Fuji -- 850 Watts 300-1031 -- Delta -- 120 Watts
  • Table of Contents

    Table of Contents

    1 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. Safe Harbor Statement The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle’s products remains at the sole discretion of Oracle. 2 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. Eine phatastische Reise ins Innere der Hardware Franz Haberhauer Stefan Hinker Oracle Hardware in 3D 5 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. T5 and M5 PCIe Carrier Card . Supports standard low-profile PCIe cards Air Flow PCIe Retimer x16 Connector (x8 electrical) 6 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. PCIe Data Paths: Full System . Two root complexes per T5 processor . Each PCIe port on a T5 processor controls a single PCIe slot 7 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. T5-2 Block Diagram DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB T5-0 T5-1 CPU CPU TPM Host & CPU PCIe Debug CPU PCIe Debug Data Flash DC/DCs 0 1 Port DC/DCs 0 1 Port x8 x8 FPGA x8 x4 x8 x1 HDD0 DBG SAS/SATA x1 HDD0 IO Controller x4 x4 PCIe PCIe SP Module HDD0 get rid of all inside x8 x8 SAS/SATA smallSwitch boxes 0 Switch 1 FRUID HDD0 IO Controller Sideband Mgmt DRAM HDD0 USB 1.1 Keyboard Mouse Service SPI x8 USB 3.0 x8 USB 2.0 Storage Flash HDD0 Host Processor SATA DVD NAND USB 2.0 Hub USB USB 3.0 USB Internal USB Hub VGA VGA REAR IO Board USB2 USB3 VGA USB0 USB1 VGA Serial Enet Quad 10Gig Enet DB15 Mgmt Mgmt Slot 2 (8) 2 Slot (8) 3 Slot (8) 4 Slot (8) 5 Slot (8) 6 Slot (8) 7 Slot (8) 8 Slot Slot 1 (8) 1 Slot 10/100 FAN BOARD REAR IO 8 Copyright © 2013, Oracle and/or its affiliates.
  • Datasheet-AMD-Am29202.Pdf

    Datasheet-AMD-Am29202.Pdf

    Advance Information Advanced Am29202 Micro Low-Cost RISC Microcontroller with Devices IEEE-1284-Compliant Parallel Interface DISTINCTIVE CHARACTERISTICS Completely integrated system for IEEE Std 1284-1994-compliant parallel port cost-sensitive embedded applications interface (peripheral-side only) supports fast requiring high performance bidirectional data transfers. Full 32-bit RISC architecture offers faster — Compatibility, Nibble, Byte, and ECP modes instruction execution and higher performance. — Supports Microsoft Windows Printing System — 32-bit instruction/data bus Bidirectional bit serializer/deserializer for direct — 22-bit address bus connection to raster input and output devices — 192 general-purpose registers 12-line programmable I/O port — Fully pipelined, three-address instruction (8 lines interruptible) architecture DRAM page-mode support improves memory — 104-Mbyte address space access time. — 12-, 16-, and 20-MHz operating frequencies On-chip DRAM mapping reduces memory — 16 VAX MIPS sustained at 20 MHz requirements. Glueless system interfaces with on-chip wait Advanced debugging support state control lower total system cost. — IEEE Std 1149.1-1990-compliant Standard — ROM controller supports four banks of ROM, Test Access Port and Boundary Scan Architec- each separately programmable for 8-, 16-, or ture (JTAG) for testing system hardware 32-bit-wide interface. — Instruction tracing — DRAM controller supports four banks of — UART serial port DRAM, each separately programmable for Software and hardware development tools
  • CHERI Concentrate: Practical Compressed Capabilities

    CHERI Concentrate: Practical Compressed Capabilities

    1 CHERI Concentrate: Practical Compressed Capabilities Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony Fox, Robert Norton, Thomas Bauereiss, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel W. Filardo, A. Theodore Markettos, Michael Roe, Peter G. Neumann, Robert N. M. Watson, Simon W. Moore Abstract—We present CHERI Concentrate, a new fat-pointer compression scheme applied to CHERI, the most developed capability-pointer system at present. Capability fat pointers are a primary candidate to enforce fine-grained and non-bypassable security properties in future computer systems, although increased pointer size can severely affect performance. Thus, several proposals for capability compression have been suggested elsewhere that do not support legacy instruction sets, ignore features critical to the existing software base, and also introduce design inefficiencies to RISC-style processor pipelines. CHERI Concentrate improves on the state-of-the-art region-encoding efficiency, solves important pipeline problems, and eases semantic restrictions of compressed encoding, allowing it to protect a full legacy software stack. We present the first quantitative analysis of compiled capability code, which we use to guide the design of the encoding format. We analyze and extend logic from the open-source CHERI prototype processor design on FPGA to demonstrate encoding efficiency, minimize delay of pointer arithmetic, and eliminate additional load-to-use delay. To verify correctness of our proposed high-performance logic, we present a HOL4 machine-checked proof of the decode and pointer-modify operations. Finally, we measure a 50% to 75% reduction in L2 misses for many compiled C-language benchmarks running under a commodity operating system using compressed 128-bit and 64-bit formats, demonstrating both compatibility with and increased performance over the uncompressed, 256-bit format.
  • AMD's Early Processor Lines, up to the Hammer Family (Families K8

    AMD's Early Processor Lines, up to the Hammer Family (Families K8

    AMD’s early processor lines, up to the Hammer Family (Families K8 - K10.5h) Dezső Sima October 2018 (Ver. 1.1) Sima Dezső, 2018 AMD’s early processor lines, up to the Hammer Family (Families K8 - K10.5h) • 1. Introduction to AMD’s processor families • 2. AMD’s 32-bit x86 families • 3. Migration of 32-bit ISAs and microarchitectures to 64-bit • 4. Overview of AMD’s K8 – K10.5 (Hammer-based) families • 5. The K8 (Hammer) family • 6. The K10 Barcelona family • 7. The K10.5 Shanghai family • 8. The K10.5 Istambul family • 9. The K10.5-based Magny-Course/Lisbon family • 10. References 1. Introduction to AMD’s processor families 1. Introduction to AMD’s processor families (1) 1. Introduction to AMD’s processor families AMD’s early x86 processor history [1] AMD’s own processors Second sourced processors 1. Introduction to AMD’s processor families (2) Evolution of AMD’s early processors [2] 1. Introduction to AMD’s processor families (3) Historical remarks 1) Beyond x86 processors AMD also designed and marketed two embedded processor families; • the 2900 family of bipolar, 4-bit slice microprocessors (1975-?) used in a number of processors, such as particular DEC 11 family models, and • the 29000 family (29K family) of CMOS, 32-bit embedded microcontrollers (1987-95). In late 1995 AMD cancelled their 29K family development and transferred the related design team to the firm’s K5 effort, in order to focus on x86 processors [3]. 2) Initially, AMD designed the Am386/486 processors that were clones of Intel’s processors.
  • Vysoké Učení Technické V Brně Návrh Řídicí Jednotky

    Vysoké Učení Technické V Brně Návrh Řídicí Jednotky

    VYSOKÉ UČENÍ TECHNICKÉ V BRNĚ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA STROJNÍHO INŽENÝRSTVÍ ÚSTAV AUTOMATIZACE A INFORMATIKY FACULTY OF MECHANICAL ENGINEERING INSTITUTE OF AUTOMATION AND COMPUTER SCIENCE NÁVRH ŘÍDICÍ JEDNOTKY PRO AUTONOMNÍ MOBILNÍ ROBOT DESIGN OF CONTROL BOARD FOR AUTONOMOUS MOBILE ROBOT BAKALÁŘSKÁ PRÁCE BACHELOR'S THESIS AUTOR PRÁCE PETR MAŠEK AUTHOR VEDOUCÍ PRÁCE ING. STANISLAV VĚCHET, PH.D. SUPERVISOR BRNO 2010 Strana 3 Vysoké učení technické v Brně, Fakulta strojního inženýrství Ústav automatizace a informatiky Akademický rok: 2009/2010 ZADÁNÍ BAKALÁŘSKÉ PRÁCE student(ka): Petr Mašek který/která studuje v bakalářském studijním programu obor: Aplikovaná informatika a řízení (3902R001) Ředitel ústavu Vám v souladu se zákonem č.111/1998 o vysokých školách a se Studijním a zkušebním řádem VUT v Brně určuje následující téma bakalářské práce: Návrh řídicí jednotky pro autonomní mobilní robot v anglickém jazyce: Design of control board for autonomous mobile robot. Stručná charakteristika problematiky úkolu: Cílem práce je návrh a výroba základní řídicí jednotky autonomního mobilního robotu. Účelem této jednotky je zpracování informací z infračervených senzoru vzdálenosti a jejich vyhodnocení. Dále pak řízení aktuátorů. Řídicí jednotka musí být dostatečně výkonná pro zpracování základních navigačních tzv. “bug” algoritmů. Cíle bakalářské práce: Prostudujte možnosti řízení konstrukčně podobných robotů Navrhněte nejvhodnější strukturu řídicí jednotky Tuto řídicí jednotku vyrobte Výsledný produkt prakticky otestujte Strana 4 Seznam odborné literatury: www.robotika.cz www.megarobot.net www.hobbyrobot.cz Vedoucí bakalářské práce: Ing. Stanislav Věchet, Ph.D. Termín odevzdání bakalářské práce je stanoven časovým plánem akademického roku 2009/2010. V Brně, dne L.S. _______________________________ _______________________________ Ing. Jan Roupec, Ph.D. prof. RNDr.
  • Using and Porting the GNU Compiler Collection

    Using and Porting the GNU Compiler Collection

    Using and Porting the GNU Compiler Collection Richard M. Stallman Last updated 14 June 2001 for gcc-3.0 Copyright c 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. For GCC Version 3.0 Published by the Free Software Foundation 59 Temple Place - Suite 330 Boston, MA 02111-1307, USA Last printed April, 1998. Printed copies are available for $50 each. ISBN 1-882114-37-X Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with the Invariant Sections being “GNU General Public License”, the Front-Cover texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled “GNU Free Documentation License”. (a) The FSF’s Front-Cover Text is: A GNU Manual (b) The FSF’s Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development. Short Contents Introduction......................................... 1 1 Compile C, C++, Objective C, Fortran, Java ............... 3 2 Language Standards Supported by GCC .................. 5 3 GCC Command Options ............................. 7 4 Installing GNU CC ............................... 111 5 Extensions to the C Language Family .................. 121 6 Extensions to the C++ Language ...................... 165 7 GNU Objective-C runtime features .................... 175 8 gcov: a Test Coverage Program ...................... 181 9 Known Causes of Trouble with GCC ................... 187 10 Reporting Bugs.................................
  • Using the GNU Compiler Collection

    Using the GNU Compiler Collection

    Using the GNU Compiler Collection Richard M. Stallman Last updated 20 April 2002 for GCC 3.2.3 Copyright c 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. For GCC Version 3.2.3 Published by the Free Software Foundation 59 Temple Place—Suite 330 Boston, MA 02111-1307, USA Last printed April, 1998. Printed copies are available for $50 each. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with the Invariant Sections being “GNU General Public License”, the Front-Cover texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled “GNU Free Documentation License”. (a) The FSF’s Front-Cover Text is: A GNU Manual (b) The FSF’s Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development. i Short Contents Introduction ...................................... 1 1 Compile C, C++, Objective-C, Ada, Fortran, or Java ....... 3 2 Language Standards Supported by GCC ............... 5 3 GCC Command Options .......................... 7 4 C Implementation-defined behavior ................. 153 5 Extensions to the C Language Family ................ 157 6 Extensions to the C++ Language ................... 255 7 GNU Objective-C runtime features.................. 267 8 Binary Compatibility ........................... 273 9 gcov—a Test Coverage Program ................... 277 10 Known Causes of Trouble with GCC ...............