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SPARC/CPU-8VT Technical Reference Manual

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SPARC/CPU-8VT Technical Reference Manual SPARC/CPU-8VT Technical Reference Manual P/N 204718 Edition 2.1 March 1999 FORCE COMPUTERS Inc./GmbH All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE COMPUTERS World Wide Web: www.forcecomputers.com 24-hour access to on-line manuals, driver updates, and application notes is provided via SMART, our SolutionsPLUS customer support program that provides current technical and services information. Headquarters The Americas Europe Asia FORCE COMPUTERS Inc. FORCE COMPUTERS GmbH FORCE COMPUTERS Japan KK 2001 Logic Drive Prof.-Messerschmitt-Str. 1 Miyakeya Building 4F San Jose, CA 95124-3468 D-85579 Neubiberg/München 1-9-12 Hamamatsucho U.S.A. Germany Minato-ku, Tokyo 105 Japan Tel.: +1 (408) 369-6000 Tel.: +49 (89) 608 14-0 Tel.: +81 (03) 3437 3948 Fax: +1 (408) 371-3382 Fax: +49 (89) 609 77 93 Fax: +81 (03) 3437 3968 Email [email protected] Email [email protected] Email [email protected] NOTE The information in this document has been carefully checked and is believed to be entirely reliable. FORCE COMPUTERS makes no warranty of any kind with regard to the material in this document, and assumes no responsibility for any errors which may appear in this document. FORCE COMPUTERS reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance, or design. FORCE COMPUTERS assumes no responsibility for the use of any circuitry other than circuitry which is part of a product of FORCE COMPUTERS Inc./GmbH. FORCE COMPUTERS does not convey to the purchaser of the product described herein any license under the patent rights of FORCE COMPUTERS Inc./GmbH nor the rights of others. All product names as mentioned herein are the trademarks or registered trademarks of their respective companies. Contents Table of Contents Using This Manual . ix 1 Introduction . 1 1.1 Specification . 2 1.2 Product Nomenclature . 4 1.3 Ordering Information . 4 2 Installation . 7 2.1 Safety Note . 7 2.2 Installation Prerequisites and Requirements . 8 2.2.1 Requirements . 8 2.2.2 Terminal Connection . 9 2.2.3 Location Overview . 9 2.3 Switch Settings . 11 2.3.1 Memory Module MEM-5 . 13 2.4 Power Up . 14 2.4.1 VME Slot-1 Device . 14 2.4.2 VMEbus SYSRESET . 14 2.4.3 Serial Ports . 15 2.4.4 RESET and ABORT Key Enable . 15 2.4.5 Boot Flash Memory Write Protection . 15 2.4.6 User Flash Memory Write Protection . 15 2.4.7 Reserved Switches . 15 2.4.8 Floppy Interface or SCSI #2 Availability on P2 . 16 2.4.9 Network Interface Selection (NIS) for Ethernet . 17 2.4.10 Parallel Port . 17 2.5 SCSI Configuration . 17 2.5.1 SCSI #1 Termination . 17 SPARC/CPU-8VT Page i Contents 2.5.2 SCSI #2 Termination . 19 2.6 Connectors . 21 2.6.1 Twisted Pair Ethernet Connector Pinout . 21 2.6.2 Serial Port A and B Connector Pinout . 22 2.6.3 Keyboard/Mouse Connector Pinout . 22 2.6.4 VME P2 Connector Pinout . 23 2.7 IOBP-10 . 24 2.7.1 Jumper Setting for IOBP-10 . 24 2.7.2 IOBP-10 Connector Pinouts . 25 2.8 IOBP-DS . 27 2.8.1 Jumper Setting for IOBP-DS . 27 2.8.2 IOBP-DS Connector Pinouts . 28 2.9 Ethernet Address and Host ID . 30 2.10 OpenBoot Firmware . 31 2.10.1 Boot the System . 31 2.10.2 NVRAM Boot Parameters . 33 2.10.3 Diagnostics . 34 2.10.4 Display System Information . 36 2.10.5 Reset the System . 37 2.10.6 OpenBoot Help . 38 3 Hardware . 41 3.1 Overview . 41 3.2 Block Diagram . 41 3.3 The TurboSPARC Processor . 43 3.3.1 Features of TurboSPARC . 43 3.3.2 Address Mapping for TurboSPARC . 43 3.4 The L2 Cache . 44 3.5 The Shared Memory . 44 3.6 The Memory Module MEM-5 . 46 3.7 SBus Participants . 47 3.7.1 Address Mapping for SBus Slots on the SPARC/CPU-8VT . 47 204718 2 20000146 420 000 1 March 1999 Page ii SPARC/CPU-8VT Contents 3.8 NCR89C100 (MACIO #1 and MACIO #2) . 48 3.8.1 Features of the NCR89C100 . 49 3.8.2 SCSI . 49 3.8.3 Ethernet . 50 3.8.3.1 Network Interface 1 Control And Status Register . 51 3.8.3.2 Network Interface 2 Control And Status Register . 51 3.9 NCR89C105 (SLAVIO) . 52 3.9.1 Features of the NCR89C105 . 53 3.9.2 Address Map of Local I/O Devices . ..
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