DOCSLIB.ORG

Flexible Register Management Using Reference Counting

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Flexible Register Management Using Reference Counting Appears in Proc. HPCA-18 (2012) Flexible Register Management using Reference Counting Steven Battle Andrew D. Hilton Mark Hempstead Amir Roth Drexel University IBM Corporation Drexel University University of Pennsylvania [email protected] [email protected] [email protected] [email protected] Abstract erence count becomes zero. Reference counting is more general and powerful than cicular queue driven regis- Conventional out-of-order processors that use a uni- ter management. In addition to conventional retirement- fied physical register file allocate and reclaim registers driven register reclamation, it supports execution-driven explicitly using a free list that operates as a circular register reclamation used in latency-tolerant, scalable queue. We describe and evaluate a more flexible register instruction window designs like CFP (Continual Flow management scheme—reference counting. Pipelines) [23] and BOLT (Better Out-of-Order Latency We implement reference counting using a bit-matrix Tolerance) [8]. It also supports register sharing which with a column for every physical register and a row for allows multiple logical registers that contain the same every entity that can hold a physical register, e.g., an value to share the same (physical) register, reducing ex- in-flight instruction. Columns are NOR’ed together to ecution overhead and (potentially) the height of the dy- create a bitvector free list from which registers are allo- namic dataflow graph. Register sharing has been used in cated using priority encoders. previously proposed techniques Unified Renaming [10], We describe reference counting designs that sup- RENO (Rename Optimizer) [18], and NoSQ (No Store port micro-architectural techniques including register Queue) [22]. We show how reference counting supports file power gating, dynamic register move elimination, these and other features, both alone and in combination. register file checkpointing, and latency tolerant execu- The first description of reference counting used per- tion. Performance and circuit simulation show that the register multi-input up-down counters [16]. More recent energy cost of reference counting is low and is easily designs use a two-dimensional bit-matrix [20]. The ma- recouped by the savings of the techniques it enables. trix has a column per register and a row per entity that can hold a register, e.g., an in-flight instruction or the rename map table. The bit at row e and column p is 1. Introduction set if entity e holds register p. The bits in each col- Most contemporary out-of-order processors use a umn are NOR’ed together to create a bitvector-style free unified physical register file to hold both architectural list from which registers are allocated using priority en- and speculative register state. This design requires fewer coders. This structure is similar to the register renam- register value copies than one that uses a separate ar- ing and map table checkpointing mechanism used in the chitectural register file and a ROB that holds destina- Alpha 21264 [11], but is used only for register reclama- tion register values. Processors manage registers—for tion and can operate in conjunction with any renaming the rest of the paper, we use register to mean physi- and checkpointing scheme. Reference counts are ma- cal register—using a free list that operates as a circu- nipulated by operating on matrix bits. Different uses lar queue. Dispatching instructions dequeue (allocate) of reference counting require different matrix organiza- registers at one end. Committing instructions enqueue tions. Depending on the type of register-holding entity (free) the registers they overwrite at the other end. The and on manipulation bandwidth requirements, a given destination registers of squashed instructions are freed matrix row may be implemented using RAM or latches. in bulk by moving the free list head pointer. We use cycle-level performance simulation and cir- This paper describes an alternative register manage- cuit simulation, described in Section 2, to evaluate ment algorithm, reference counting, in which processor the performance benefits and area and power costs actions decrement reference counts rather than explicitly of various register reference counting configurations. freeing registers. A register becomes free when its ref- Where analogous free-list configurations exist, we eval- 1 ROB Instruc,ons D O r0 r1 r2 r3 Tail p3 p1 p2 p3 p4 p5 p6 p7 p8 p9 Commit A r1+r2 r3 p1+p2 p4 p4 p3 p0 p1 p2 p4 Arch p5 1 1 0 1 1 1 1 1 0 B r3+r1 r2 p4+p1 p5 p5 p2 Arch+ROB Chkpt p6 Free List Chkpt C r2+r1 r3 p5+p1 p6 p6 p4 p0 p1 p5 p6 Chkpt p7 AND D r0+r3 r1 p0+p6 p7 p7 p1 Head p8 Chkpt Rename E r1+r3 r2 p7+p6 p8 p8 p5 p0 p7 p8 p6 Rename p9 1 1 1 1 1 1 0 0 0 b) Register management using reference counng. a) Convenonal queue-based register management. There are four logical The circular queue free list is replaced by a vector registers (r0−r3) and ten physical registers (p0−p9). Hardwired logical register r0 with one bit per physical register. When instrucDon A is mapped to hardwired register p0. The circular queue free list has six slots. commits, it clears the bit corresponding to its InstrucDon A commits and frees overwriGen (O) physical register p3 by adding it overwriGen register p3. When instrucDon E to the tail of the free list. It also writes its desDnaon (D) physical register p4 dispatches, it sets the bit corresponding to its into the architectural map table. InstrucDon E dispatches and allocates desDnaon register p8. This desDnaon was selected desDnaon physical register p8 from the head of the free list. It also writes p8 from the free list using an encoder. InstrucDon C’s into the rename map table. The processor took a checkpoint immediately aer checkpoint includes a copy of the map table and a renaming instrucDon C. The checkpoint includes a copy of the map table and a copy of bitvector. Restoring the checkpoint involves copy of the free list head pointer. Restoring the checkpoint involves restoring the restoring the map table copy and ANDing the map table copy and the free list head pointer. checkpointed and acDve bitvectors. Figure 1. Implementations of ROB register management. uate those side-by-side. Section 3 introduces reference ory latency is 150 cycles—corresponding to a 3.2GHz counting and shows how it can re-implement traditional clock—and bandwidth is 12.8 Gbytes/s. register management. Section 4 presents register-file We compiled the SPEC2006 benchmarks using gcc power-gating, a new application of reference counting 4.3 at optimization level –O3. We simulate the bench- that exploits its ability to allocate registers in any or- marks to completion on their training inputs, sampling der. Section 5 discusses reference counting support for 10 million of every 500 million instructions with 10 mil- register sharing with an application to dynamic regis- lion instructions of cache and branch predictor warmup. ter move elimination. Although reference counting con- Power and area estimation. We created custom sumes more area and power than a traditional free list, RTL for the reference counting structures and used the the gating and move elimination optimizations it sup- NCSU FabScalar memory generator [4] to create netlists ports offset its energy cost. Sections 6 and 7 demon- for the register file, free list, and checkpoint SRAMs, all strate reference counting support for speculative retire- in NSCU’s 45nm FreePDK CMOS technology. We de- ment and execution-driven register reclamation. rived power estimates for synthesized netlists using the power modeling features in Synopsys PrimeTime and 2. Methodology also used HSPICE for transistor-level netlists. Our in- put activity traces included both the average port access We evaluate reference counting and its applications rate and the average bit toggle rate to accurately reflect using both performance and circuit simulation. energy consumption. Static power is scaled to bring the Performance evaluation. Our cycle-level perfor- P(st):P(dy) ratio in line with the typical 1:3 ratio [27] mance simulator executes user level x86 64 code, break- measured in commercial 45nm processors. ing x86 instructions into RISC-like three-register micro- operations. The simulated core is modeled roughly after 3. Conventional Register Reclamation Nehalem. It is 4-wide issue with a 23-stage pipeline, 128-entry reorder buffer, 36-entry issue queue, and 96 Out-of-order processors with unified register files use rename registers. We model both a single-threaded con- a variant of the MIPS R10000 register management al- figuration with 160 total registers and a dual-threaded gorithm [26]. The rename map table is a multi-ported configuration with 224 registers. The branch predictor is RAM containing (physical) register numbers indexed by a 16 Kbyte 3-table PPM predictor [15]. The three-level logical register number. The free list is a RAM of regis- cache hierarchy has 32 Kbyte 8-way set-associative, 3- ter numbers managed as a circular queue. For P registers cycle access instruction and data caches, a 256 Kbyte, and L logical registers the free list contains P–L entries 8-way set-associative, 10-cycle acccess L2 and an 8 as L registers are always mapped. Each entry is log2P- MByte, 16-way set-associative 40-cycle L3. Main mem- bits wide. At rename, a register-writing instruction is al- disp[0:7] ovwr[0:7] disp2[0:5] disp3[0:5] disp0[0:5] ovwr0[0:7] disp1[0:5] ovwr1[0:7] ovwr2[0:7] ovwr3[0:7] DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC [0:159] set [0:159] clr set0[0:39] clr0[0:159] set1[40:79] clr1[0:159] set3[120:159] clr3[0:159] clr2[0:159] set2[80:119] OR OR OR OR REF[0:159] REF[0:39] REF[40:79] REF[80:119] REF[120:159] PRIO_ENC PRIO_ENC PRIO_ENC PRIO_ENC PRIO_ENC PIPE_LATCH PIPE_LATCH alloc[0:7] alloc1[0:5] a) Reference counng for a scalar processor.
Load more

Recommended publications
  • Review Memory Disambiguation Review Explicit Register Renaming
    5HYLHZ5HRUGHU%XIIHU 52% &6 *UDGXDWH&RPSXWHU$UFKLWHFWXUH 8VHRIUHRUGHUEXIIHU /HFWXUH ² ,QRUGHULVVXH2XWRIRUGHUH[HFXWLRQ,QRUGHUFRPPLW ² +ROGVUHVXOWVXQWLOWKH\FDQEHFRPPLWWHGLQRUGHU ,QVWUXFWLRQ/HYHO3DUDOOHOLVP ª 6HUYHVDVVRXUFHRIYDOXHVXQWLOLQVWUXFWLRQVFRPPLWWHG ² 3URYLGHVVXSSRUWIRUSUHFLVHH[FHSWLRQV6SHFXODWLRQVLPSO\WKURZRXW *HWWLQJWKH&3, LQVWUXFWLRQVODWHUWKDQH[FHSWHGLQVWUXFWLRQ ² &RPPLWVXVHUYLVLEOHVWDWHLQLQVWUXFWLRQRUGHU ² 6WRUHVVHQWWRPHPRU\V\VWHPRQO\ZKHQWKH\UHDFKKHDGRIEXIIHU 6HSWHPEHU ,Q2UGHU&RPPLW LVLPSRUWDQWEHFDXVH 3URI-RKQ.XELDWRZLF] ² $OORZVWKHJHQHUDWLRQRISUHFLVHH[FHSWLRQV ² $OORZVVSHFXODWLRQDFURVVEUDQFKHV &6.XELDWRZLF] &6.XELDWRZLF] /HF /HF 5HYLHZ0HPRU\'LVDPELJXDWLRQ 5HYLHZ([SOLFLW5HJLVWHU5HQDPLQJ 4XHVWLRQ*LYHQDORDGWKDWIROORZVDVWRUHLQSURJUDP 0DNHXVHRIDSK\VLFDO UHJLVWHUILOHWKDWLVODUJHUWKDQ RUGHUDUHWKHWZRUHODWHG" QXPEHURIUHJLVWHUVVSHFLILHGE\,6$ ² 7U\LQJWRGHWHFW5$:KD]DUGVWKURXJKPHPRU\ .H\LQVLJKW$OORFDWHDQHZSK\VLFDOGHVWLQDWLRQUHJLVWHU ² 6WRUHVFRPPLWLQRUGHU 52% VRQR:$5:$:PHPRU\KD]DUGV IRUHYHU\LQVWUXFWLRQWKDWZULWHV ,PSOHPHQWDWLRQ ² 5HPRYHVDOOFKDQFHRI:$5RU:$:KD]DUGV ² .HHSTXHXHRIVWRUHVLQSURJRUGHU ² 6LPLODUWRFRPSLOHUWUDQVIRUPDWLRQFDOOHG6WDWLF6LQJOH$VVLJQPHQW ² :DWFKIRUSRVLWLRQRIQHZORDGVUHODWLYHWRH[LVWLQJVWRUHV ª /LNHKDUGZDUHEDVHGG\QDPLFFRPSLODWLRQ" :KHQKDYHDGGUHVVIRUORDGFKHFNVWRUHTXHXH 0HFKDQLVP".HHSDWUDQVODWLRQWDEOH ² ,IDQ\ VWRUHSULRUWRORDGLVZDLWLQJIRULWVDGGUHVVVWDOOORDG ² ,6$UHJLVWHU⇒ SK\VLFDOUHJLVWHUPDSSLQJ ² ,IORDGDGGUHVVPDWFKHVHDUOLHUVWRUHDGGUHVV DVVRFLDWLYHORRNXS ² :KHQUHJLVWHUZULWWHQUHSODFHHQWU\ZLWKQHZUHJLVWHUIURPIUHHOLVW WKHQZHKDYHDPHPRU\LQGXFHG
    [Show full text]
  • ARM Cortex-A* Brian Eccles, Riley Larkins, Kevin Mee, Fred Silberberg, Alex Solomon, Mitchell Wills
    ARM Cortex-A* Brian Eccles, Riley Larkins, Kevin Mee, Fred Silberberg, Alex Solomon, Mitchell Wills The ARM Cortex­A product line has changed significantly since the introduction of the Cortex­A8 in 2005. ARM’s next major leap came with the Cortex­A9 which was the first design to incorporate multiple cores. The next advance was the development of the big.LITTLE architecture, which incorporates both high performance (A15) and high efficiency(A7) cores. Most recently the A57 and A53 have added 64­bit support to the product line. The ARM Cortex series cores are all made up of the main processing unit, a L1 instruction cache, a L1 data cache, an advanced SIMD core and a floating point core. Each processor then has an additional L2 cache shared between all cores (if there are multiple), debug support and an interface bus for communicating with the rest of the system. Multi­core processors (such as the A53 and A57) also include additional hardware to facilitate coherency between cores. The ARM Cortex­A57 is a 64­bit processor that supports 1 to 4 cores. The instruction pipeline in each core supports fetching up to three instructions per cycle to send down the pipeline. The instruction pipeline is made up of a 12 stage in order pipeline and a collection of parallel pipelines that range in size from 3 to 15 stages as seen below. The ARM Cortex­A53 is similar to the A57, but is designed to be more power efficient at the cost of processing power. The A57 in order pipeline is made up of 5 stages of instruction fetch and 7 stages of instruction decode and register renaming.
    [Show full text]
  • Out-Of-Order Execution & Register Renaming
    Asanovic/Devadas Spring 2002 6.823 Out-of-Order Execution & Register Renaming Krste Asanovic Laboratory for Computer Science Massachusetts Institute of Technology Asanovic/Devadas Spring 2002 6.823 Scoreboard for In-order Issue Busy[unit#] : a bit-vector to indicate unit’s availability. (unit = Int, Add, Mult, Div) These bits are hardwired to FU's. WP[reg#] : a bit-vector to record the registers for which writes are pending Issue checks the instruction (opcode dest src1 src2) against the scoreboard (Busy & WP) to dispatch FU available? not Busy[FU#] RAW? WP[src1] or WP[src2] WAR? cannot arise WAW? WP[dest] Asanovic/Devadas Spring 2002 Out-of-Order Dispatch 6.823 ALU Mem IF ID Issue WB Fadd Fmul • Issue stage buffer holds multiple instructions waiting to issue. • Decode adds next instruction to buffer if there is space and the instruction does not cause a WAR or WAW hazard. • Any instruction in buffer whose RAW hazards are satisfied can be dispatched (for now, at most one dispatch per cycle). On a write back (WB), new instructions may get enabled. Asanovic/Devadas Spring 2002 6.823 Out-of-Order Issue: an example latency 1 LD F2, 34(R2) 1 1 2 2 LD F4, 45(R3) long 3 MULTD F6, F4, F2 3 4 3 4 SUBD F8, F2, F2 1 5 5 DIVD F4, F2, F8 4 6 ADDD F10, F6, F4 1 6 In-order: 1 (2,1) . 2 3 4 4 3 5 . 5 6 6 Out-of-order: 1 (2,1) 4 4 . 2 3 . 3 5 .
    [Show full text]
  • Dynamic Register Renaming Through Virtual-Physical Registers
    Dynamic Register Renaming Through Virtual-Physical Registers † Teresa Monreal [email protected] Antonio González* [email protected] Mateo Valero* [email protected] †† José González [email protected] † Víctor Viñals [email protected] †Departamento de Informática e Ing. de Sistemas. Centro Politécnico Superior - Univ. de Zaragoza, Zaragoza, Spain. *Departament d’ Arquitectura de Computadors. Universitat Politècnica de Catalunya, Barcelona, Spain. ††Departamento de Ingeniería y Tecnología de Computadores. Universidad de Murcia, Murcia, Spain. Abstract Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel dynamic register renaming scheme that delays the allocation of physical registers until a late stage in the pipeline. We show that it can provide important savings in number of physical registers so it can significantly shorter the register file access time. Delaying the allocation of physical registers requires some artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical registers, which are tags that do not require any storage location. The proposed renaming scheme shortens the average number of cycles that each physical register is allocated, and allows for an early execution of instructions since they can obtain a physical register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in advance. 1. Introduction Dynamically-scheduled superscalar processors exploit instruction-level parallelism (ILP) by overlapping the execution of instructions in an instruction window.
    [Show full text]
  • Computer Architecture Out-Of-Order Execution
    Computer Architecture Out-of-order Execution By Yoav Etsion With acknowledgement to Dan Tsafrir, Avi Mendelson, Lihu Rappoport, and Adi Yoaz 1 Computer Architecture 2013– Out-of-Order Execution The need for speed: Superscalar • Remember our goal: minimize CPU Time CPU Time = duration of clock cycle × CPI × IC • So far we have learned that in order to Minimize clock cycle ⇒ add more pipe stages Minimize CPI ⇒ utilize pipeline Minimize IC ⇒ change/improve the architecture • Why not make the pipeline deeper and deeper? Beyond some point, adding more pipe stages doesn’t help, because Control/data hazards increase, and become costlier • (Recall that in a pipelined CPU, CPI=1 only w/o hazards) • So what can we do next? Reduce the CPI by utilizing ILP (instruction level parallelism) We will need to duplicate HW for this purpose… 2 Computer Architecture 2013– Out-of-Order Execution A simple superscalar CPU • Duplicates the pipeline to accommodate ILP (IPC > 1) ILP=instruction-level parallelism • Note that duplicating HW in just one pipe stage doesn’t help e.g., when having 2 ALUs, the bottleneck moves to other stages IF ID EXE MEM WB • Conclusion: Getting IPC > 1 requires to fetch/decode/exe/retire >1 instruction per clock: IF ID EXE MEM WB 3 Computer Architecture 2013– Out-of-Order Execution Example: Pentium Processor • Pentium fetches & decodes 2 instructions per cycle • Before register file read, decide on pairing Can the two instructions be executed in parallel? (yes/no) u-pipe IF ID v-pipe • Pairing decision is based… On data
    [Show full text]
  • Hardware-Sensitive Database Operations - II
    Faculty of Computer Science Database and Software Engineering Group Hardware-Sensitive Database Operations - II Balasubramanian (Bala) Gurumurthy Advanced Topics in Databases, 2019/May/17 Otto-von-Guericke University of Magdeburg So Far... ● Hardware evolution and current challenges ● Hardware-oblivious vs. hardware-sensitive programming ● Pipelining in RISC computing ● Pipeline Hazards ○ Structural hazard ○ Data hazard ○ Control hazard ● Resolving hazards ○ Loop-Unrolling ○ Predication Bala Gurumurthy | Hardware-Sensitive Database Operations Part II We will see ● Vectorization ○ SIMD Execution ○ SIMD in DBMS Operation ● GPUs in DBMSs ○ Processing Model ○ Handling Synchronization Bala Gurumurthy | Hardware-Sensitive Database Operations Vectorization Leveraging Modern Processing Capabilities Hardware Parallelism One we know already: Pipelining ● Separate chip regions for individual tasks to execute independently ● Advantage: parallelism + sequential execution semantics ● We discussed problems of hazards ● VLSI tech. limits degree up to which pipelining is feasible [Kaeslin, 2008] Bala Gurumurthy | Hardware-Sensitive Database Operations Hardware Parallelism Chip area can be used for other types of parallelism: Computer systems typically use identical hardware circuits, but their function may be controlled by different instruction stream Si: Bala Gurumurthy | Hardware-Sensitive Database Operations Special instances Example of this architecture? Bala Gurumurthy | Hardware-Sensitive Database Operations Special instances Example of this architecture?
    [Show full text]
  • Trends in Processor Architecture
    A. González Trends in Processor Architecture Trends in Processor Architecture Antonio González Universitat Politècnica de Catalunya, Barcelona, Spain 1. Past Trends Processors have undergone a tremendous evolution throughout their history. A key milestone in this evolution was the introduction of the microprocessor, term that refers to a processor that is implemented in a single chip. The first microprocessor was introduced by Intel under the name of Intel 4004 in 1971. It contained about 2,300 transistors, was clocked at 740 KHz and delivered 92,000 instructions per second while dissipating around 0.5 watts. Since then, practically every year we have witnessed the launch of a new microprocessor, delivering significant performance improvements over previous ones. Some studies have estimated this growth to be exponential, in the order of about 50% per year, which results in a cumulative growth of over three orders of magnitude in a time span of two decades [12]. These improvements have been fueled by advances in the manufacturing process and innovations in processor architecture. According to several studies [4][6], both aspects contributed in a similar amount to the global gains. The manufacturing process technology has tried to follow the scaling recipe laid down by Robert N. Dennard in the early 1970s [7]. The basics of this technology scaling consists of reducing transistor dimensions by a factor of 30% every generation (typically 2 years) while keeping electric fields constant. The 30% scaling in the dimensions results in doubling the transistor density (doubling transistor density every two years was predicted in 1975 by Gordon Moore and is normally referred to as Moore’s Law [21][22]).
    [Show full text]
  • WCAE 2003 Workshop on Computer Architecture Education
    WCAE 2003 Proceedings of the Workshop on Computer Architecture Education in conjunction with The 30th International Symposium on Computer Architecture DQG 2003 Federated Computing Research Conference Town and Country Resort and Convention Center b San Diego, California June 8, 2003 Workshop on Computer Architecture Education Sunday, June 8, 2003 Session 1. Welcome and Keynote 8:45–10:00 8:45 Welcome Edward F. Gehringer, workshop organizer 8:50 Keynote address, “Teaching and teaching computer Architecture: Two very different topics (Some opinions about each),” Yale Patt, teacher, University of Texas at Austin 1 Break 10:00–10:30 Session 2. Teaching with New Architectures 10:30–11:20 10:30 “Intel Itanium floating-point architecture,” Marius Cornea, John Harrison, and Ping Tak Peter Tang, Intel Corp. ................................................................................................................................. 5 10:50 “DOP — A CPU core for teaching basics of computer architecture,” Miloš BeþváĜ, Alois Pluháþek and JiĜí DanƟþek, Czech Technical University in Prague ................................................................. 14 11:05 Discussion Break 11:20–11:30 Session 3. Class Projects 11:30–12:30 11:30 “Superscalar out-of-order demystified in four instructions,” James C. Hoe, Carnegie Mellon University ......................................................................................................................................... 22 11:50 “Bridging the gap between undergraduate and graduate experience in
    [Show full text]
  • MIPS Architecture with Tomasulo Algorithm [12]
    CALIFORNIA STATE UNIVERSITY NORTHRIDGE TOMASULO ARCHITECTURE BASED MIPS PROCESSOR A graduate project submitted in partial fulfilment for the requirement Of the degree of Master of Science In Electrical Engineering By Sameer S Pandit May 2014 The graduate project of Sameer Pandit is approved by: ______________________________________ ____________ Dr. Ali Amini, Ph.D. Date _______________________________________ ____________ Dr. Shahnam Mirzaei, Ph.D. Date _______________________________________ ____________ Dr. Ramin Roosta, Ph.D., Chair Date California State University Northridge ii ACKNOWLEDGEMENT I would like to express my gratitude towards all the members of the project committee and would like to thank them for their continuous support and mentoring me for every step that I have taken towards the completion of this project. Dr. Roosta, for his guidance, Dr. Shahnam for his ideas, and Dr. Ali Amini for his utmost support. I would also like to thank my family and friends for their love, care and support through all the tough times during my graduation. iii Table of Contents SIGNATURE PAGE .......................................................................................................... ii ACKNOWLEDGEMENT ................................................................................................. iii LIST OF FIGURES .......................................................................................................... vii ABSTRACT .......................................................................................................................
    [Show full text]
  • In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (Tlbs)
    IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO. 5, MAY 2006 1 In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs) Aamer Jaleel, Student Member, IEEE, and Bruce Jacob, Member, IEEE Abstract—The effects of the general-purpose precise interrupt mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors handle interrupts precisely, they typically begin by flushing the pipeline to make the CPU available to execute handler instructions. In doing so, the CPU ends up flushing many instructions that have been brought in to the reorder buffer. In particular, these instructions may have reached a very deep stage in the pipeline—representing significant work that is wasted. In addition, an overhead of several cycles and wastage of energy (per exception detected) can be expected in refetching and reexecuting the instructions flushed. This paper concentrates on improving the performance of precisely handling software managed translation look-aside buffer (TLB) interrupts, one of the most frequently occurring interrupts. The paper presents a novel method of in-lining the interrupt handler within the reorder buffer. Since the first level interrupt-handlers of TLBs are usually small, they could potentially fit in the reorder buffer along with the user-level code already there. In doing so, the instructions that would otherwise be flushed from the pipe need not be refetched and reexecuted. Additionally, it allows for instructions independent of the exceptional instruction to continue to execute in parallel with the handler code. By in-lining the TLB interrupt handler, this provides lock-up free TLBs.
    [Show full text]
  • Improving the Precise Interrupt Mechanism of Software- Managed TLB Miss Handlers
    Improving the Precise Interrupt Mechanism of Software- Managed TLB Miss Handlers Aamer Jaleel and Bruce Jacob Electrical & Computer Engineering University of Maryland at College Park {ajaleel,blj}@eng.umd.edu Abstract. The effects of the general-purpose precise interrupt mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors handle interrupts precisely, they typically begin by flushing the pipeline to make the CPU available to execute handler instructions. In doing so, the CPU ends up flushing many instructions that have been brought in to the reorder buffer. In par- ticular, many of these instructions have reached a very deep stage in the pipeline - representing significant work that is wasted. In addition, an overhead of several cycles can be expected in re-fetching and re-executing these instructions. This paper concentrates on improving the performance of precisely handling software managed translation lookaside buffer (TLB) interrupts, one of the most frequently occurring interrupts. This paper presents a novel method of in-lining the interrupt handler within the reorder buffer. Since the first level interrupt-handlers of TLBs are usually small, they could potentially fit in the reorder buffer along with the user-level code already there. In doing so, the instructions that would otherwise be flushed from the pipe need not be re-fetched and re-executed. Additionally, it allows for instructions independent of the exceptional instruction to continue to execute in parallel with the handler code. We simulate two different schemes of in-lining the interrupt on a pro- cessor with a 4-way out-of-order core similar to the Alpha 21264.
    [Show full text]
  • Complex Pipelining: Out-Of-Order Execution & Register Renaming
    1 Complex Pipelining: Out-of-Order Execution & Register Renaming Arvind Computer Science and Artificial Intelligence Laboratory M.I.T. Based on the material prepared by Krste Asanovic and Arvind 6.823 L12-2 Arvind In-Order Issue Pipeline ALU Mem IF ID Issue WB Fadd GPR’s FPR’s Fmul Fdiv October 24, 2005 6.823 L12-3 Arvind Scoreboard for In-order Issues Busy[FU#] : a bit-vector to indicate FU’s availability. (FU = Int, Add, Mult, Div) These bits are hardwired to FU's. WP[reg#] : a bit-vector to record the registers for which writes are pending. These bits are set to true by the Issue stage and set to false by the WB stage Issue checks the instruction (opcode dest src1 src2) against the scoreboard (Busy & WP) to dispatch FU available? Busy[FU#] RAW? WP[src1] or WP[src2] WAR? cannot arise WAW? WP[dest] October 24, 2005 6.823 L12-4 Arvind In-Order Issue Limitations: an example latency 1 2 1 LD F2, 34(R2) 1 2 LD F4, 45(R3) long 4 3 3 MULTD F6, F4, F2 3 4 SUBD F8, F2, F2 1 5 5 DIVD F4, F2, F8 4 6 ADDD F10, F6, F4 1 6 In-order: 1 (2,1) . 2 3 4 4 3 5 . 5 6 6 In-order restriction prevents instruction 4 from being dispatched October 24, 2005 6.823 L12-5 Arvind Out-of-Order Issue ALU Mem IF ID Issue WB Fadd Fmul • Issue stage buffer holds multiple instructions waiting to issue. • Decode adds next instruction to buffer if there is space and the instruction does not cause a WAR or WAW hazard.
    [Show full text]