Chapter 6 Combinational CMOS Circuit and Logic Design
Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan Jin-Fu Li, EE, NCU 2 Outline Advanced CMOS Logic Design I/O Structures
Advanced Reliable Systems (ARES) Lab. n
/ p
e Tim 2 |) tp V | DD ) V ( T V P 2
Jin-Fu Li, EE, NCU 3 t DD V L V L DD ( V V V ) n P tp
tn F V 2 V p n L tn depends strongly on the ratio depends strongly on the ratio DD V V L V Pseudo-NMOS Logic ( n
for A The low output voltage can be calculated as The low output voltage Thus V The logic is also called ratioed logic The logic is also A pseudo-NMOS inverter
Advanced Reliable Systems (ARES) Lab. gn out C V
Jin-Fu Li, EE, NCU 4 NMOS network only N+1 transistors are needed an N- for Pseudo-NMOS Logic inputs Low area cost input gate input gate-load capacitance Low dissipation power Non-zero static Advantages Disadvantage An N-input pseudo-NMOS gate logic Features of pseudo-NMOS
Advanced Reliable Systems (ARES) Lab. 2 X 1 X Y 2 X 1 X 2 X 1 X 2 X 1 X 2 X Jin-Fu Li, EE, NCU 5 1 X 2 X 1 X 2 2 X X 1 X Pseudo-NMOS XOR Gate 1 X Y The XOR is defined by An example of XOR gate realized with pseudo- NMOS logic
Advanced Reliable Systems (ARES) Lab. ) L n
/ p Jin-Fu Li, EE, NCU 6 is determined by Choosing Transistor Sizes L V Noise margin Power consumption Speed by the low output It is affected voltage (V The larger the W/L of load transistor, the faster the gate will be, particularly when driving many other gates the power dissipation Unfortunately, this increases the area of driver network and Goals Noise margin Speed
Advanced Reliable Systems (ARES) Lab. dd V 2 ) tp V gs V Jin-Fu Li, EE, NCU 7 ( P ) L W ( ox C 2 p
dc P The static power dissipation is equal to the current of The static power dissipation the is equal to the PMOS load transistor multiplied by the power supply voltage. Thus, the power is given by Choosing Transistor Sizes A pseudo-NMOS logic gate having a “1” output has no logic gate A pseudo-NMOS static (DC) power dissipation. having a “0” output However, a pseudo-NMOS gate power dissipation has a static power dissipation large PMOS results in The large Select an appropriate PMOS the bias voltage of PMOS Increase Power dissipation Power-reduction methods
Advanced Reliable Systems (ARES) Lab. . i , determine the maximum i
Jin-Fu Li, EE, NCU 8 (W/L)eq i be equal to one-half of the W/L =n i eq Choosing Transistor Sizes Take (W/L) PMOS load transistor Let (W/L) Q For each transistor for it will be in series, number of drive transistors all possible inputs. Denote this number n The relative size (W/L) of the PMOS load transistor is (W/L) of the PMOS load transistor size The relative chosen as a compromise between speed and size versus power dissipation Once the size of load transistor has been chosen, then a simple procedure can be used to choose the W/Ls of the NMOS transistors in the NMOS network A simple procedure for choosing transistor sizes of pseudo-NMOS logic gates
Advanced Reliable Systems (ARES) Lab. Y 7 4 5 6 Q Q Q Q 4 5 6 7 X X X X 5/0.8 8 2 3 Q Q Q 2 3 X X 1 Q 1 X
Jin-Fu Li, EE, NCU 9 An Example Size 2.5um/0.8um 5.0um/0.8um 5.0um/0.8um 10um/0.8um 10um/0.8um 10um/0.8um 10um/0.8um is (5/0.8)/2=3.125 is 5 um/0.8 um 8 eq 1 2 3 4 5 6 7 Q Q Q Q Q Q Q Transistor Transistor Gate lengths of drive transistors Gate lengths are taken at their minimum 0.8um obtain can Thus we (W/L) (W/L) Choose appropriate sizes for the pseudo- NMOS logic gate shown below
Advanced Reliable Systems (ARES) Lab. out
dynamic precharging V
Jin-Fu Li, EE, NCU 10 NMOS network PR Dynamic Logic inputs This is usually not possible This is usually not called dynamic logic as shown below Normally, during the time output is being precharged, conducting the NMOS network should not be An alternative technique is to use is technique An alternative To eliminate the static power dissipation of pseudo-NMOS logic
Advanced Reliable Systems (ARES) Lab. Evaluate Precharge CLK out V
Jin-Fu Li, EE, NCU 11 NMOS network Dynamic Logic inputs Another dynamic logic technique Two-phase operation: precharge & evaluate This can fully eliminate static power dissipation CLK
Advanced Reliable Systems (ARES) Lab. Y=ABC A B C clk clk
Jin-Fu Li, EE, NCU 12 Z=(A+B).C Examples of Dynamic Logic Examples of C clk clk Two examples AB
Advanced Reliable Systems (ARES) Lab. 0.5 12 12 C 12 () CC C CC C DA /2 D DD ADD CV C C C V VV V E.g., if then output voltage is C A 1 C 2 C charge sharing model
Jin-Fu Li, EE, NCU 13 C A 1 2 C C B C Problems of Dynamic Logic Charge sharing Simple single-phase dynamic logic can not be cascaded 1 1 0 Two major problems of dynamic logic Charge sharing clk=1 clk=1
Advanced Reliable Systems (ARES) Lab. Erroneous State 2 d d1 T T 1 2 N N clock 2 N
Jin-Fu Li, EE, NCU 14 N Logic 1 N N Logic Problems of Dynamic Logic Simple single-phase dynamic logic can not be cascaded inputs clock
Advanced Reliable Systems (ARES) Lab. out V NMOS network
Jin-Fu Li, EE, NCU 15 inputs CMOS Domino Logic CLK Each gate must be buffered structures are possible Only noninverting Domino logic can be cascaded The basic structure of domino logic Some limitations of this structure
Advanced Reliable Systems (ARES) Lab. out V NMOS network evaluate NMOS network
Jin-Fu Li, EE, NCU 16 A Domino Cascade precharge Stage 1 Stage 2 Stage 3 NMOS network An example of cascaded domino logics CLK
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 Charge-Keeper Circuits This means that charge sharing and leakage processes that reduce the internal voltage may be limiting factors Static version Latched version The domino cascade must have an domino cascade must have The evaluation interval that is long enough to allow every stage time to discharge Two types of modified domino logics can cope with this problem
Advanced Reliable Systems (ARES) Lab. Z Weak PMOS Weak Block N-logic Latched version Clk Inputs Z
Jin-Fu Li, EE, NCU 18 Weak PMOS Weak Block Charge-Keeper Circuits Static version N-logic The aspect ratio of the charge-keeper MOS must be charge-keeper ratio of the The aspect event with discharge not interfere small so that it does Modified domino logics Modified domino Clk
Inputs Advanced Reliable Systems (ARES) Lab. F N-logic N-logic
Jin-Fu Li, EE, NCU 19 N-logic N-logic Complex Domino Gate CLK In a complex domino gate, intermediate nodes have been provided with their own precharge transistor
Advanced Reliable Systems (ARES) Lab. 1 2 F F A B
Jin-Fu Li, EE, NCU 20 CLK Multiple-Output Domino Logic Multiple-Output Domino Multiple-output domino logic (MODL) allows two or more outputs from a single logic gate The basic structure of MODL
Advanced Reliable Systems (ARES) Lab. D C C B B B A A A 1 2 3 F F F B D’ Jin-Fu Li, EE, NCU 21 C’ A’ CC B’ A D C BB’ CLK
A Multiple-Output Domino Logic Gate Advanced Reliable Systems (ARES) Lab. N-logic CLK Other N blocks Other N P-logic
Jin-Fu Li, EE, NCU 22 -CLK Other P blocks Other P NP Domino Logic N-logic The domino buffer is removed, while are alternately blocks cascaded logic composed of P- and N-transistors A further refinement of the domino logic is shown below CLK
Advanced Reliable Systems (ARES) Lab. N-logic CLK Other N blocks Other N Other P blocks Other P P-logic
Jin-Fu Li, EE, NCU 23 -CLK Other P blocks Other P NP Domino Logic Other N blocks Other N N-logic NP domino logic with multiple fanouts CLK
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 Pass-Transistor Logic Advanced CMOS Logic Design
Advanced Reliable Systems (ARES) Lab. ,- i Product term (F) are the true and i th input variable and Z is the i
i Jin-Fu Li, EE, NCU 25 n P V n and –X i Control signals +…+P 2 V 2 +P 1 Pass-Transistor Logic V 1 ,Z}, where X i i X complement of the high-impedance F=P The pass variables can take the values {0,1,X V Model for pass transistor logic The product term Pass signals
Advanced Reliable Systems (ARES) Lab. OUT Cross-coupled A B OUT
Jin-Fu Li, EE, NCU 26 A -A B -B OUT Pass-Transistor Logics A A -A Different types of pass-transistor logics for pass-transistor logics Different types of XNOR gate implementation two-input Complementary Single-polarity B -B
Advanced Reliable Systems (ARES) Lab. Y
Jin-Fu Li, EE, NCU 27 B A It adds hysteresis to the inverter, which makes it It adds hysteresis less likely to have glitches Modifying NMOS pass-transistor logic so Modifying NMOS pass-transistor logic full-level swings are realized Adding the additional PMOS has another advantages Full-Swing Pass-Transistor Logic Full-Swing Pass-Transistor
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 Differential Logic Design Logic inversions are trivially obtained by simply inversions are trivially obtained Logic delay a time without incurring interchanging wires of two cross- networks will often consist The load coupled PMOS only. This minimizes both area and the PMOS transistors number of series the every signal, to represent used must be Two wires interconnect area can be significantly greater. In are being gates only a few close in which applications as not as significant is often driven, this disadvantage the advantages Features of the differential logic design differential logic Features of the Disadvantage differential circuits are often a logic Thus preferable consideration
Advanced Reliable Systems (ARES) Lab. + out V NMOS Network
Fully Differential Jin-Fu Li, EE, NCU 29 - out V + - + - n n 1 1 V V V V The inputs to the drive network come in pairs, a single- ended signal and its inverse into two separate divided be The NMOS network can output the inverting and ground, networks, one between noninverting a complementary network between the and ground output and One simple and popular approach for realizing differential logic circuit is shown below A Fully Differential Logic Circuit
Advanced Reliable Systems (ARES) Lab. A+B A B B A A+B
Jin-Fu Li, EE, NCU 30 AB Examples B A Differential CMOS realizations of AND and OR functions A B AB
Advanced Reliable Systems (ARES) Lab. out V E C A B A
Jin-Fu Li, EE, NCU 31 E A Examples =(A+B’)C+A’E C B out out V A Differential CMOS realization of the realization of Differential CMOS function V
Advanced Reliable Systems (ARES) Lab. + ref V out V + V
Jin-Fu Li, EE, NCU 32 Differential NMOS Network - V - out ref V + - + - V 1 1 n n V V V V A variation of fully differential logic differential A variation of fully no with a cross-coupled load A compromise between with a continuously-on load and d.c. power dissipation d.c. power dissipation Differential Split-Level Logic Differential split-level (DSL) logic
Advanced Reliable Systems (ARES) Lab. tn -V ref
Jin-Fu Li, EE, NCU 33 Both outputs begin to change immediately power dissipation, normally have d.c. but The loads do less than pseudo-NMOS much gates and dynamic power dissipation This reduced voltage swing increases the speed the of logic gates short-channel effects This greatly minimizes the The loads have some of the features of both continuous loads and cross-coupled load The nodes V+, V-, and all internal of the voltage changes between NMOS network have greater than 0V and V the across drain-source voltage The maximum is reduced by about one-half NMOS transistors Differential Split-Level Logic Features of DSL logic Features of DSL
Advanced Reliable Systems (ARES) Lab. + out V
Network Jin-Fu Li, EE, NCU 34 Pass-Transistor - out V + - + - n 1 n 1 V V V V Pass-transistor networks for most required logic of the cross- in which both sides functions exist simultaneously driven are coupled loads This minimizes the time from when inputs changes to when the low-to-high transition occurs It is not necessary to wait until one side goes It is not necessary to wait until to low before the other side goes high Differential Pass-Transistor Logic Differential Pass-Transistor
Advanced Reliable Systems (ARES) Lab. - A A+B + B + A - A - B + A A+B
Jin-Fu Li, EE, NCU 35 + A AB + B - A levels, thereby eliminating the voltage + dd A - B drop It removes the ratio requirements on It removes the logic guaranteed functionality and has to signal levels The cross-coupled loads restore full V - Other features of pass-transistor logic Examples: A Differential Pass-Transistor Logic Differential Pass-Transistor AB
Advanced Reliable Systems (ARES) Lab. + out V CLK
Jin-Fu Li, EE, NCU 36 Differential NMOS Network CLK + - + - n n 1 1 V V V V Dynamic Differential Logic - out A differential Domino logic gate V
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37 Dynamic Differential Logic Its d.c. power dissipation is very small, good whereas its speed still quite Because of the buffers at output, its output drive capability is also very good One of major limitations Domino logic, the difficulty in realizing inverting functions, is eliminated because of the circuits the of differential nature Features of dynamic Domino logic
Advanced Reliable Systems (ARES) Lab. + out V CLK
Jin-Fu Li, EE, NCU 38 Differential NMOS Network CLK + - + - 1 1 n n V V V V - out V Dynamic Differential Logic When the fan-out is small, inverters at the output can be eliminated and the inputs to the charge-keeper transistors can be taken from the opposite output
Advanced Reliable Systems (ARES) Lab. out X CLK=0 f out CLK V MOS) - + 2 out C
Jin-Fu Li, EE, NCU 39 PMOS NMOS Network Network MOS gate 2 … … CLK CLK Clocked CMOS (C Ideally, clocks are non-overlapping CLK=1, f is valid is CLK=1, f CLK=0, the output During is in a high-impedance state. on C this time interval, the output is held voltage Structure of a C
Advanced Reliable Systems (ARES) Lab. A+B out C A A B CLK CLK B MOS Logic Gates
2 Jin-Fu Li, EE, NCU 40 AB out C A B A CLK CLK Examples of C Examples of B
Advanced Reliable Systems (ARES) Lab. t L out t I C 1 V ) t ( X V V ) h t X h V dt t L L out 1 out I I V C C ( t 0 V(t) 0 L X 1 out 1 I V V C V ) dV h MOS Logic Gates h ) t t t ( 2 ( 1 V V out V V
Jin-Fu Li, EE, NCU 41 - + out very long i out L C dd n out V i p i dt dV out dt C out is a constant I out i C p out i i Cause that the output node cannot hold the charge on V n i CLK=1 CLK=0 dV The problem of charge leakage The basics of charge leakage are shown below out i Assume
The Drawback of C Advanced Reliable Systems (ARES) Lab. I/O circuitry PAD Pad-limited pad
Jin-Fu Li, EE, NCU 42 I/O Pads pad PAD ss I/O circuitry Core-limited pad , V dd Input pad (ESD) Input pad (driver) Output pad (ESD+driver) I/O pad V Types of pads pads need guard ring for latch-up All protection Core-limited pad & pad-limited
Advanced Reliable Systems (ARES) Lab. the gate is about 330volts the gate is =0.03pF, and t=1us =0.03pF, g
Jin-Fu Li, EE, NCU 43 electrostatic discharge Assume I=10uA, C The voltage that appears on ESD Protection PAD PAD Input pad without (ESD) protection Input pad with ESD protection
Advanced Reliable Systems (ARES) Lab. 0 1 Z OUT P 1 1 0 0 1 0 N 0 1 X 0 1 1 OE D PAD PAD OUT N P
Jin-Fu Li, EE, NCU 44 D OE Tristate & Bidirectional Pads Tristate pad Bidirectional pad data output-enable
Advanced Reliable Systems (ARES) Lab. T- T+ =V =V in in in V T- DD V -V T+ T+ V =V H
Jin-Fu Li, EE, NCU 45 T- V out V DD V Schmitt Trigger Circuit Hysteresis voltage V When the input is rising, it switches when V when V falling, it switches input is When the Voltage transfer curve of Schmitt circuit
Advanced Reliable Systems (ARES) Lab. Time in V Jin-Fu Li, EE, NCU 46 out V T- T+ DD V V V Schmitt Trigger Circuit Voltage waveform for slow input Schmitt trigger turns a signal with very slow transition into a signal with sharp transition
Advanced Reliable Systems (ARES) Lab. is given
2
N out V of the transistor
GS V 3 3 P N
FP Jin-Fu Li, EE, NCU 47 DD FN V V V 2 1 1 2 P P N N enters in conduction mode which means which enters in conduction mode
2
N Tn V in FN T V V V T V in V in Tn V FN 2 V V Schmitt Trigger Circuit GS V 2 GS V by When , Then When the input is rising, When the the A CMOS version of the Schmitt trigger circuit
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48 Summary CMOS Logic Gate Design Design Logic Advanced CMOS Clocking Strategies I/O Structures The following topics have been introduced in this chapter
Advanced Reliable Systems (ARES) Lab.