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Effective Virtual CPU Configuration with QEMU and Libvirt
Undocumented CPU Behavior: Analyzing Undocumented Opcodes on Intel X86-64 Catherine Easdon Why Investigate Undocumented Behavior? the “Golden Screwdriver” Approach
Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3C: System Programming Guide, Part 3
FRVT General Evaluation Specifications
SGX Secure Enclaves in Practice Security and Crypto Review
Beyond MOV ADD XOR – the Unusual and Unexpected
A Survey of Published Attacks on Intel
Intel® Software Guard Extensions (Intel® SGX)
Assembly Language Programming Processor Architecture
X86 Intrinsics Cheat Sheet Jan Finis
[email protected]
Intel® Architecture Instruction Set Extensions and Future Features
Intel(R) Advanced Vector Extensions Programming Reference
10Th Gen Intel® Core™ Processor Families Datasheet, Vol. 1
DRNG) Sssoftwaresoftware Iiimplementationimplementation Guide
Processor Package Security Infrastructure SAFE G0 Review
Solving the Platform Entropy Problem Phase 2
Decentralised Draw Systems Version 1.0
Intel SGX Explained
Top View
An Overview of Vulnerabilities and Mitigations of Intel SGX Applications
An Analysis of X86-64 Inline Assembly in C Programs
Randomness Generation
Safe and Efficient Execution of LLVM-Based Languages
Hardware Testing of TRNG
A Provable Security Analysis of Intel's Secure Key RNG
Intel® Quickassist Technology & Openssl-1.1.0: Performance
17. Risc, Cisc, and Vliw
Intel Xeon Silver 4114
Mcafee Core Cryptographic Module (Kernel) Version 1.0 and 1.1.0.203.0 FIPS 140-2 Non-Proprietary Security Policy Level 1 Valid
Intel® Architecture Instruction Set Extensions Programming Reference
Vysok´E Uˇcení Technick´Ev Brnˇe Rdrand
Calling Conventions for Different C++ Compilers and Operating Systems
CROSSTALK: Speculative Data Leaks Across Cores Are Real
The Entropic Principle /Dev/U?Random and Netbsd
Manual Vectorization @ Lhcb Trigger a CASE STUDY Vectors 101 2
Breaking the X86 ISA W
Practical Vectorization Intro Measure Prereq Techniques Expectations
Hardware Is the New Software
Intel® Processor Identification and the CPUID Instruction Application Note
A Provable-Security Analysis of Intel's Secure Key
Introduction to Intel® Advanced Vector Extensions by Chris Lomont
4. Instruction Tables Lists of Instruction Latencies, Throughputs and Micro-Operation Breakdowns for Intel, AMD, and VIA Cpus
Arbeitspaket 2: Random Number Generator
EPYC Offers X86 Compatibility
Intel® Software Guard Extensions (Intel® SGX) SDK for Linux* OS
Exploiting Microarchitectural Optimizations from Software Illustration Natascha Eibl Exploiting Microarchitectural Optimizations from Software
SGX Secure Enclaves in Practice Security and Crypto Review
Specification Update
Discovery and Exploitation of Memory Corruption Vulnerabilities in SGX
The Libgcrypt Reference Manual Version 1.9.0 18 January 2021
Intel® AES-NI and Intel® Secure Key Instructions
AMD’S Processor Lines Belonging to the Low-Power Oriented Cat Family (Families 14H/16H)
Beyond /Dev/Urandom: the State of Randomness in Linux
Intel® 64 and IA-32 Architectures Optimization Reference Manual
Release Notes for Cisco IOS Xrv 9000 Routers, IOS XR Release 7.2.1
Intel Xeon Silver 4110 CPU, 2.10Ghz) Specrate2017 Fp Peak = 86.1 CPU2017 License: 55 Test Date: Apr-2018 Test Sponsor: Dell Inc
Architecture-Instruction-Set-Extensions-Programming-Reference-812319.Pdf
Intel® Digital Random Number Generator (DRNG)
Valgrind Manual
Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
Enhanced Security with Windows® 10 and Intel® Core® Vpro™ Processors
Software Guard Extensions Programming Reference
ANALYSIS of RANDOM NUMBER GENERATION in VIRTUAL ENVIRONMENTS 124-41 BSI:Entropie in Virtuellen Maschinen
AVX AMD 3Dnow!
AMD Secure Random Number Generator Library
Intel's Digital Random Number Generator
Botan Reference Guide Release 2.18.1
Intel(R) Software Guard Extensions Developer Guide