CXD1217Q Synchronizing Signal Generator for Camera

Description The CXD1217Q is a synchronizing signal generator 32 pin QFP (Plastic) for color video cameras.

Features ¥ Compatible with the respective systems, NTSC, PALM, PAL and SECAM ¥ Output is synchronized with the clock of 910fH or 908fH ¥ 25Hz offset processing by PAL system ¥ Color framing by the respective systems, NTSC, PALM and PAL ¥ Possible external synchronization by H reset, V reset and line alternate reset pins

Applications Synchronizing signal generator for color video cameras

Structure Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25¡C) ¥ Supply voltage VDD VSS Ð 0.5 to +7.0 V ¥ Input voltage VI VSS Ð 0.5 to VDD + 0.5 V ¥ Output voltage VO VSS Ð 0.5 to VDD + 0.5 V ¥ Operating temperature Topr Ð20 to +75 ¡C ¥ Storage temperature Tstg Ð55 to +150 ¡C

Recommended Operating Conditions ¥ Supply voltage VDD 4.5 to 5.5 V ¥ Operating temperature Topr Ð20 to +75 ¡C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Ð 1 Ð E90806B0Z CXD1217Q

Block Diagram and Pin Configuration

INT-NTSC 4fscIN 8 1/4

PALM 17 fH OSC 1/9 1/101 2fH PAL 4fscOUT 7 INT- NTSC fH CLOCK 1/7 1/81 1/2 PALM ELIMINATION PAL fH VDD 28 1/625 1/525 1/625, 1/525 PAL PALM

VSS 12 fv/2 fv/8 SC PHASE 1/4 22 HCOMOUT PAL RESET COMPARISON

FIELD 1 TEST 14 RESET

CLIN 24 1/4 SC RESET CLOUT 23

1/454, 1/455 1/625, 1/525 30 OFLD1 MODE1 19 2fH 1/2 3 OFLD DECODE MODE2 20 fH 5 OLALT

EXT 18 COMPOSITE SIGNAL 31 OBF/COLB CONTROL F.F. LINE 4 OBLK LALTRI 13 ALTERNATE

RESET 2 OSYNC OUTPUT F.F. OUTPUT HORIZONTAL 10 OVD HRI 21 RESET 6 OHD

VERTICAL 26 OFH VRI 29 RESET 15 O2FH

Note) Pin 17 output is (a) a signal based on Pin 24 in INT mode at NTSC. (b) each signal is based on Pin 8 in other modes.

Ð 2 Ð CXD1217Q

Pin Description

Pin No. Symbol I/O Description 1 NC — 2 OSYNC O Composite sync output 3 OFLD O Even and Odd output 4 OBLK O Composite blanking output 5 OLALT O Line alternate output 6 OHD O Horizontal drive output 7 4fscOUT O 4fsc output 8 4fscIN I 4fsc input 9 NC — 10 OVD O Vertical drive output 11 NC —

12 VSS — GND pin 13 LALTRI I Line alternate reset input 14 TEST I Test input

15 O2FH O 2fH output (Double the frequency of Pin 27) 16 NC — 17 OSC O Sub carrier output Internal and external synchronizing modes switchover 18 EXT I L: Internal synchronization H: External synchronization 19 MODE1 I System selecting input 1 20 MODE2 I System selecting input 2 21 HRI I Horizontal reset input 22 HCOMOUT O Phase comparator output 23 CLOUT O Clock output 24 CLIN I Clock input 25 NC — 26 OFH O Horizontal frequency output 27 NC —

28 VDD — Power supply pin 29 VRI I Vertical reset signal 30 OFLD1 O First field output 31 OBF/COLB O Burst flag/color blanking output 32 NC —

Ð 3 Ð CXD1217Q

Electrical Characteristics

DC characteristics (VDD = 5V ± 10%, VSS = 0V, Topr = Ð20 to +75¡C)

Item Symbol Conditions Min. Typ. Max. Unit

VOH IOH = Ð2mA VDD Ð 0.5 VDD V Output voltage 1 VOL IOL = 4mA VSS 0.4 V

∗ VOH IOH = Ð4mA VDD Ð 0.5 VDD V Output voltage 2 1 VOL IOL = 4mA VSS 0.4 V

∗ VOH IOH = Ð4mA VDD/2 V Output voltage 3 2 VOL IOL = 8mA VDD/2 V

VIH 0.7VDD V Input voltage VIL 0.3VDD V ∗ Input current 3 IIH VIH = VDD 20 50 120 µA (Pull-down pin) Output leak ∗ ILZ At high impedance ±30 nA current 1 Power current IDD At output pin in no-load 8 mA supply Feedback ∗ RFB VDD = 5V 250k 2.5M Ω resistance 4 ∗ 1 HCOMOUT pin ∗ 2 4fscOUT and CLOUT pins ∗ 3 LALTRI, TEST, EXT, MODE1 and MODE2 pins ∗ 4 4fscOUT, 4fscIN, CLOUT and CLIN pins

I/O capacitance (VDD = VI = 0V, fM = 1MHz) Item Symbol Conditions Min. Typ. Max. Unit

Input pin CIN — — 9 pF

Output pin COUT — — 11 pF

Ð 4 Ð CXD1217Q

Description of Operation (See Block Diagram.) The CXD1217 is applicable to four systems; namely, NTSC, PAL, PALM and SECAM. In order to realize them, the following relative equations of Sub-carrier (4fsclN) and Clock (CLIN) are adopted .

Sub carrier Clock

NTSC 4fsc = 910fH 910fH

PAL 4fsc = 1135fH + 2fv 908fH

PALM 4fsc = 909fH 910fH

SECAM — 908fH

As it is obvious from the above equations, the 4fsc and clock frequency do not coincide with each other in the PAL and PALM. Therefore matching of the clock frequency is carried out by providing PLL.

1 . MODE specified input The CXD1217 provides four inputs to specify the respective modes. ∗ EXT input: Set this pin to VDD side, and it becomes into external synchronizing mode. At this time, the counters in connection with the PLL Ioop as shown in the upper part of the block diagram become into stand still state. ∗ MODE1 and MODE2 inputs: These are inputs for the system selection.

MODE1 MODE2 System 0 0 NTSC 0 1 SECAM

1 0 PALM "0" → VSS

1 1 PAL "1" → VDD ∗ TEST input: An input to be used to measure IC. This input is normally kept opened. (Because it is dropped internally to Vss with MOS resistance.)

2. Reset operation The CXD1217 has three reset inputs ; namely, HRI, VRI, LALTRI, and it works to perform reset operation when it detects falling edge. These three inputs are so designed as to take in synchronization with the IC internal clock. Therefore, it is a prerequisite that both systems should have clock frequencies that are matched as a reset operation to each other (GEN Iocked).

¥ H reset (HRI input) When the HRI input is continuous with H synchronization, resetting is activated with the initial falling edge, and for the subsequent edges they do not have to be reset unless they are deviated more than 2-bit (140ns) against the initial edge in the internal clock. That is, if the jitter of HRI input is less than 140ns, it is absorbed. The minimum resetting pulse width is over 0.3µs. The phase to be reset is the advanced point of 6.3 to 6.37µs (= 90 to 91-bit × 70ns) than the HRI input as shown in the diagram below.

HRI input CXD1217 HD OUT output

Reset Ð 5 Ð 6.3 to 6.37 [µs] CXD1217Q

¥ V reset (VRI input) When the VRI is input as shown in figure below, OSYNC can be reset at the same phase with the SYNC signal.

Counter State 142 36587109121113 14 15 SYNC Signal Falling edge permitted span a VRI Rising edge is to be behind from point a CXD1217 internal clock (2fH) (See Timing Chart Diagram)

V reset pulse AA AA After reset SYNC OUT 91210 11 13 14

Reset State

Since the falling edge point in the diagram above (marked with ↑) is the boundary of reset, if the falling edge of the VRI input traverses that point, it causes 1/2H deviation to the reset state. Accordingly, if resetting is applied between two similar systems whose frequency are different, the V to which resetting is applied generates jitter of 1/2H. (When the resetting is applied continuously.)

¥ LALT reset (LALTRI input) Phase relation between LALTRI pulse polarity and 2fH is the same as in the case of V resetting.

Resetting operation is basically required only in the external synchronizing mode (GEN LOCK mode). However, even in the internal synchronizing mode, it sometimes requires H and V outputs whose phases are deviated against a certain output. In that case, it suffices to use two CXD1217s and conduct the operation as follows:

Clock

VRI2 CXD1217 CXD1217 VRI2 OHD1 OVD1 OHD2 OVD2

Shift Reg. Input Output Clock

Delay ∗ It suffices to set IC-1 and IC-2 into INT mode.

By varying the Delay and Shift Reg. of the above diagram, any phases of OHD2 and OVD2 can be provided against the respective OHD1 and OVD1.

3. Color framing In the case of internal synchronization in the individual NTSC, PAL and PALM systems, the phase relationships between SYNC of the 1st field and sub-carrier are kept stable regardless of the power supply being ON or OFF. However, as the PAL and PALM systems are comprised of PLL, the absolute values concerning the phase according to variation of the ambient temperature drifts. Ð 6 Ð CXD1217Q

Timing Chart

Output Timing Chart Diagram

CXD1217 NTSC, PALM

Field 1 ODD

2 EVEN SYNC OUT 3 ODD

4 EVEN 12H

Field 1

BF/COLB OUT 2 (PALM) 3

4

Field 1

LALT OUT 2 (PALM) 3

4

10H

BF/COLB OUT ODD (NTSC) EVEN

ODD HD OUT EVEN

20H ODD BLK OUT EVEN

9H VD OUT

ODD FLD OUT EVEN

FLD1 OUT (fv/4) 3H (NTSC) Field 1

FLD1 OUT (fv/8) 3H (PALM) Field 1

CLIN 4fscIN (NTSC) (PALM)

SC OUT

Ð 7 Ð CXD1217Q

CXD1217 PAL, SECAM

Field 4 EVEN

1 ODD SYNC OUT 2 EVEN

3 ODD 10H

Field 4

BF/COLB OUT 1 (PAL) 2

3

Field 4

LALT OUT 1 (PAL) 2

3

9H 9H 7H

EVEN BF/COLB OUT 9H (SECAM) 8.5H 7H ODD

EVEN HD OUT ODD

25H EVEN BLK OUT ODD

7.5H OVD

EVEN FLD OUT ODD

FLD1 OUT (fv/8) 2.5H (PAL)

FLD1 OUT (fv/4) 2.5H (SECAM)

4fscIN (PAL)

SC OUT

Ð 8 Ð CXD1217Q P908 N910 P: PAL SECAM N: NTSC PALM Numerical figures show number of clocks H P420 N423 P454 N455 P145 N145 H P388 N387 1 2 P315 N315 P32 N36 P169 N169 P169 N154 P66 N68 P78 N76 P34 N32 P90 N90 P96 N96 P66 N68 P22 N22 P140 N141 P139 N140 H f BF VD EQ FLD H. R. LALT FLD1 HBLK VSYNC HSYNC HD/CBLK H H (Internal clock) 2f CXD1217 f

Ð 9 Ð CXD1217Q

Application Circuit

Basic connection in individual systems Basic connection in individual systems at internal synchronization mode (EXT input = "0") is as follows. See waveform diagram for each output.

¥ NTSC 14.318MHz ( = 910fH) VDD

17 23 24 28 12 OSC CLOUT CLIN VDD VSS

HRI 21 Synthesizer VRI 1/4 29

OLALT

OFLD1

OBF/COLB

OVD

O2FH

OLALT

OSYNC

OFH

OFLD OBLK 4fscIN 4fscOUT OHD 8 7 15 26 6 10 2 4 31 13 3 30

∗ H/2 is output for LALT OUT even in NTSC mode. ∗ MODE1, MODE2, EXT, TEST and LALTRI pins can be kept open. (If noise annoys, connect to Vss by low impedance.)

¥ PAL 14.187MHz ( = 908fH)

L. P. F VCO VDD OSC 10k 10k

17 22 24 23 12 28 19 20 HCOMOUT CLINCLOUT VSS VDD MODE1 MODE2 4fsc 1/4 IN 8 Phase Comparison HRI f'H fH 21 7 Synthesizer VRI 4fsc Clock 1/7 1/81 29 OUT Elimination 17.734MHz S. C. (4fsc) Reset 1/2 Field

1/8 1/625

OBF/COLB

O2FH

OBLK

OSYNC

OFLD1

OVD

OFLD

OHD

OLALT OFH 15 26 6 10 2 4 31 13 3 30

∗ Inverter of CLIN or CLOUT pins are usable as VCO.

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Ð 10 Ð CXD1217Q

¥ PALM 14.318MHz ( = 910fH)

L. P. F VCO VDD OSC 10k

17 22 24 23 12 28 19 HCOMOUT CLINCLOUT VSS VDD MODE1 4fsc 1/4 IN 8 Phase Comparison HRI f'H fH 21 7 Synthesizer 4fsc VRI 1/9 1/101 29 OUT 14.302MHz S. C. (4fsc) 1/8 1/525 Reset Field

1

OLALT

OFH

OBF/COLB

O2FH

OBLK

OSYNC

OFLD1

OVD

OFLD OHD 15 26 6 10 2 4 31 13 3 30

∗ Internal inverter is usable as VCO.

¥ SECAM VDD 14.187MHz ( = 908fH)

10k

23 24 12 28 20 CLOUT CLIN VSS VDD MODE2 4fscIN 8 HRI 21 Synthesizer VRI 29

7

OBLK

OBF/COLB

O2FH

OLALT

OFH

OFLD

OHD

OFLD1

OVD OSYNC 15 26 6 10 2 4 31 13 3 30

∗ COLB is output to BF/COLB OUT pin. ∗ SDR and SDB are formed in PLL using 908fH.

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

Ð 11 Ð CXD1217Q

Package Outline Unit: mm

32PIN QFP (PLASTIC)

9.0 ± 0.2 0.1 + 0.3 + 0.35 7.0 – 0.1 1.5 – 0.15

24 17

25 16

A (8.0)

9 32 + 0.2 0.1 – 0.1

1 8 0.8 b 0˚ to 10˚ 0.24 M 0.50

+ 0.15

b = 0.30 – 0.10 + 0.10 +

( 0.30)

0.127 – 0.05 – 0.127 (0.127)

DETAIL A : SOLDER

PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-QFP32-7x7-0.8 LEAD MATERIAL 42 / COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.2g

Ð 12 Ð CXD1217Q

32PIN QFP (PLASTIC)

9.0 ± 0.2 0.1 + 0.3 + 0.35 7.0 – 0.1 1.5 – 0.15

24 17

25 16

A (8.0)

9 32 + 0.2 0.1 – 0.1

1 8 0.8 b 0˚ to 10˚ 0.24 M 0.50

b = 0.30 ± 0.03

0.04 0.125 ± 0.125

DETAIL A : PALLADIUM

PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-32P-L01 LEAD TREATMENT PALLADIUM PLATING

EIAJ CODE P-QFP32-7x7-0.8 LEAD MATERIAL COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.2g

Ð 13 Ð Sony Corporation